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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_irq.v] - Blame information for rev 19

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Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                 DIGITAL I/O                               */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the Digital I/O interface:                                           */
27 
/*                                   - Interrupts.                           */
28 18 olivier.gi 
/*                                                                           */
29 
/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
31 
/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 19 olivier.gi 
/* $Rev: 19 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
36 2 olivier.gi 
/*===========================================================================*/
37 
 
38 
initial
39 
   begin
40 
      $display(" ===============================================");
41 
      $display("|                 START SIMULATION              |");
42 
      $display(" ===============================================");
43 
      repeat(5) @(posedge mclk);
44 
      stimulus_done = 0;
45 
 
46 
 
47 
      // PORT 1: TEST INTERRUPT FLAGS
48 
      //--------------------------------------------------------
49 
 
50 
      @(r15==16'h0200) p1_din = 8'h01;
51 
      @(r15==16'h0201) p1_din = 8'h03;
52 
      @(r15==16'h0202) p1_din = 8'h07;
53 
      @(r15==16'h0203) p1_din = 8'h0f;
54 
      @(r15==16'h0204) p1_din = 8'h1f;
55 
      @(r15==16'h0205) p1_din = 8'h3f;
56 
      @(r15==16'h0206) p1_din = 8'h7f;
57 
      @(r15==16'h0207) p1_din = 8'hff;
58 
      @(r15==16'h0208);
59 
      if (mem200 !== 16'h0201) tb_error("====== RISING EDGE TEST: P1IFG != 0x0201 =====");
60 
      if (mem202 !== 16'h0804) tb_error("====== RISING EDGE TEST: P1IFG != 0x0804 =====");
61 
      if (mem204 !== 16'h2010) tb_error("====== RISING EDGE TEST: P1IFG != 0x2010 =====");
62 
      if (mem206 !== 16'h8040) tb_error("====== RISING EDGE TEST: P1IFG != 0x8040 =====");
63 
 
64 
 
65 
      @(r15==16'h0210) p1_din = 8'h7f;
66 
      @(r15==16'h0211) p1_din = 8'h3f;
67 
      @(r15==16'h0212) p1_din = 8'h1f;
68 
      @(r15==16'h0213) p1_din = 8'h0f;
69 
      @(r15==16'h0214) p1_din = 8'h07;
70 
      @(r15==16'h0215) p1_din = 8'h03;
71 
      @(r15==16'h0216) p1_din = 8'h01;
72 
      @(r15==16'h0217) p1_din = 8'h00;
73 
      @(r15==16'h0218);
74 
      if (mem210 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
75 
      if (mem212 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
76 
      if (mem214 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
77 
      if (mem216 !== 16'h0000) tb_error("====== RISING EDGE TEST: P1IFG != 0x0000 =====");
78 
 
79 
 
80 
      @(r15==16'h0220) p1_din = 8'h01;
81 
      @(r15==16'h0221) p1_din = 8'h03;
82 
      @(r15==16'h0222) p1_din = 8'h07;
83 
      @(r15==16'h0223) p1_din = 8'h0f;
84 
      @(r15==16'h0224) p1_din = 8'h1f;
85 
      @(r15==16'h0225) p1_din = 8'h3f;
86 
      @(r15==16'h0226) p1_din = 8'h7f;
87 
      @(r15==16'h0227) p1_din = 8'hff;
88 
      @(r15==16'h0228);
89 
      if (mem220 !== 16'h0301) tb_error("====== RISING EDGE TEST: P1IFG != 0x0301 =====");
90 
      if (mem222 !== 16'h0f07) tb_error("====== RISING EDGE TEST: P1IFG != 0x0f07 =====");
91 
      if (mem224 !== 16'h3f1f) tb_error("====== RISING EDGE TEST: P1IFG != 0x3f1f =====");
92 
      if (mem226 !== 16'hff7f) tb_error("====== RISING EDGE TEST: P1IFG != 0xff7f =====");
93 
 
94 
 
95 
      @(r15==16'h0230) p1_din = 8'h7f;
96 
      @(r15==16'h0231) p1_din = 8'h3f;
97 
      @(r15==16'h0232) p1_din = 8'h1f;
98 
      @(r15==16'h0233) p1_din = 8'h0f;
99 
      @(r15==16'h0234) p1_din = 8'h07;
100 
      @(r15==16'h0235) p1_din = 8'h03;
101 
      @(r15==16'h0236) p1_din = 8'h01;
102 
      @(r15==16'h0237) p1_din = 8'h00;
103 
      @(r15==16'h0238);
104 
      if (mem230 !== 16'h4080) tb_error("====== FALLING EDGE TEST: P1IFG != 0x4080 =====");
105 
      if (mem232 !== 16'h1020) tb_error("====== FALLING EDGE TEST: P1IFG != 0x1020 =====");
106 
      if (mem234 !== 16'h0408) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0408 =====");
107 
      if (mem236 !== 16'h0102) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0102 =====");
108 
 
109 
      @(r15==16'h0240) p1_din = 8'h01;
110 
      @(r15==16'h0241) p1_din = 8'h03;
111 
      @(r15==16'h0242) p1_din = 8'h07;
112 
      @(r15==16'h0243) p1_din = 8'h0f;
113 
      @(r15==16'h0244) p1_din = 8'h1f;
114 
      @(r15==16'h0245) p1_din = 8'h3f;
115 
      @(r15==16'h0246) p1_din = 8'h7f;
116 
      @(r15==16'h0247) p1_din = 8'hff;
117 
      @(r15==16'h0248);
118 
      if (mem240 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
119 
      if (mem242 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
120 
      if (mem244 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
121 
      if (mem246 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P1IFG != 0x0000 =====");
122 
 
123 
      @(r15==16'h0250) p1_din = 8'h7f;
124 
      @(r15==16'h0251) p1_din = 8'h3f;
125 
      @(r15==16'h0252) p1_din = 8'h1f;
126 
      @(r15==16'h0253) p1_din = 8'h0f;
127 
      @(r15==16'h0254) p1_din = 8'h07;
128 
      @(r15==16'h0255) p1_din = 8'h03;
129 
      @(r15==16'h0256) p1_din = 8'h01;
130 
      @(r15==16'h0257) p1_din = 8'h00;
131 
      @(r15==16'h0258);
132 
      if (mem250 !== 16'hc080) tb_error("====== FALLING EDGE TEST: P1IFG != 0xc080 =====");
133 
      if (mem252 !== 16'hf0e0) tb_error("====== FALLING EDGE TEST: P1IFG != 0xf0e0 =====");
134 
      if (mem254 !== 16'hfcf8) tb_error("====== FALLING EDGE TEST: P1IFG != 0xfcf8 =====");
135 
      if (mem256 !== 16'hfffe) tb_error("====== FALLING EDGE TEST: P1IFG != 0xfffe =====");
136 
 
137 
 
138 
      // PORT 2: TEST INTERRUPT FLAGS
139 
      //--------------------------------------------------------
140 
 
141 
      @(r15==16'h0200) p2_din = 8'h01;
142 
      @(r15==16'h0201) p2_din = 8'h03;
143 
      @(r15==16'h0202) p2_din = 8'h07;
144 
      @(r15==16'h0203) p2_din = 8'h0f;
145 
      @(r15==16'h0204) p2_din = 8'h1f;
146 
      @(r15==16'h0205) p2_din = 8'h3f;
147 
      @(r15==16'h0206) p2_din = 8'h7f;
148 
      @(r15==16'h0207) p2_din = 8'hff;
149 
      @(r15==16'h0208);
150 
      if (mem200 !== 16'h0201) tb_error("====== RISING EDGE TEST: P2IFG != 0x0201 =====");
151 
      if (mem202 !== 16'h0804) tb_error("====== RISING EDGE TEST: P2IFG != 0x0804 =====");
152 
      if (mem204 !== 16'h2010) tb_error("====== RISING EDGE TEST: P2IFG != 0x2010 =====");
153 
      if (mem206 !== 16'h8040) tb_error("====== RISING EDGE TEST: P2IFG != 0x8040 =====");
154 
 
155 
 
156 
      @(r15==16'h0210) p2_din = 8'h7f;
157 
      @(r15==16'h0211) p2_din = 8'h3f;
158 
      @(r15==16'h0212) p2_din = 8'h1f;
159 
      @(r15==16'h0213) p2_din = 8'h0f;
160 
      @(r15==16'h0214) p2_din = 8'h07;
161 
      @(r15==16'h0215) p2_din = 8'h03;
162 
      @(r15==16'h0216) p2_din = 8'h01;
163 
      @(r15==16'h0217) p2_din = 8'h00;
164 
      @(r15==16'h0218);
165 
      if (mem210 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
166 
      if (mem212 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
167 
      if (mem214 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
168 
      if (mem216 !== 16'h0000) tb_error("====== RISING EDGE TEST: P2IFG != 0x0000 =====");
169 
 
170 
 
171 
      @(r15==16'h0220) p2_din = 8'h01;
172 
      @(r15==16'h0221) p2_din = 8'h03;
173 
      @(r15==16'h0222) p2_din = 8'h07;
174 
      @(r15==16'h0223) p2_din = 8'h0f;
175 
      @(r15==16'h0224) p2_din = 8'h1f;
176 
      @(r15==16'h0225) p2_din = 8'h3f;
177 
      @(r15==16'h0226) p2_din = 8'h7f;
178 
      @(r15==16'h0227) p2_din = 8'hff;
179 
      @(r15==16'h0228);
180 
      if (mem220 !== 16'h0301) tb_error("====== RISING EDGE TEST: P2IFG != 0x0301 =====");
181 
      if (mem222 !== 16'h0f07) tb_error("====== RISING EDGE TEST: P2IFG != 0x0f07 =====");
182 
      if (mem224 !== 16'h3f1f) tb_error("====== RISING EDGE TEST: P2IFG != 0x3f1f =====");
183 
      if (mem226 !== 16'hff7f) tb_error("====== RISING EDGE TEST: P2IFG != 0xff7f =====");
184 
 
185 
 
186 
      @(r15==16'h0230) p2_din = 8'h7f;
187 
      @(r15==16'h0231) p2_din = 8'h3f;
188 
      @(r15==16'h0232) p2_din = 8'h1f;
189 
      @(r15==16'h0233) p2_din = 8'h0f;
190 
      @(r15==16'h0234) p2_din = 8'h07;
191 
      @(r15==16'h0235) p2_din = 8'h03;
192 
      @(r15==16'h0236) p2_din = 8'h01;
193 
      @(r15==16'h0237) p2_din = 8'h00;
194 
      @(r15==16'h0238);
195 
      if (mem230 !== 16'h4080) tb_error("====== FALLING EDGE TEST: P2IFG != 0x4080 =====");
196 
      if (mem232 !== 16'h1020) tb_error("====== FALLING EDGE TEST: P2IFG != 0x1020 =====");
197 
      if (mem234 !== 16'h0408) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0408 =====");
198 
      if (mem236 !== 16'h0102) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0102 =====");
199 
 
200 
      @(r15==16'h0240) p2_din = 8'h01;
201 
      @(r15==16'h0241) p2_din = 8'h03;
202 
      @(r15==16'h0242) p2_din = 8'h07;
203 
      @(r15==16'h0243) p2_din = 8'h0f;
204 
      @(r15==16'h0244) p2_din = 8'h1f;
205 
      @(r15==16'h0245) p2_din = 8'h3f;
206 
      @(r15==16'h0246) p2_din = 8'h7f;
207 
      @(r15==16'h0247) p2_din = 8'hff;
208 
      @(r15==16'h0248);
209 
      if (mem240 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
210 
      if (mem242 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
211 
      if (mem244 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
212 
      if (mem246 !== 16'h0000) tb_error("====== FALLING EDGE TEST: P2IFG != 0x0000 =====");
213 
 
214 
      @(r15==16'h0250) p2_din = 8'h7f;
215 
      @(r15==16'h0251) p2_din = 8'h3f;
216 
      @(r15==16'h0252) p2_din = 8'h1f;
217 
      @(r15==16'h0253) p2_din = 8'h0f;
218 
      @(r15==16'h0254) p2_din = 8'h07;
219 
      @(r15==16'h0255) p2_din = 8'h03;
220 
      @(r15==16'h0256) p2_din = 8'h01;
221 
      @(r15==16'h0257) p2_din = 8'h00;
222 
      @(r15==16'h0258);
223 
      if (mem250 !== 16'hc080) tb_error("====== FALLING EDGE TEST: P2IFG != 0xc080 =====");
224 
      if (mem252 !== 16'hf0e0) tb_error("====== FALLING EDGE TEST: P2IFG != 0xf0e0 =====");
225 
      if (mem254 !== 16'hfcf8) tb_error("====== FALLING EDGE TEST: P2IFG != 0xfcf8 =====");
226 
      if (mem256 !== 16'hfffe) tb_error("====== FALLING EDGE TEST: P2IFG != 0xfffe =====");
227 
 
228 
 
229 
      // PORT 1: TEST INTERRUPT VECTOR
230 
      //--------------------------------------------------------
231 
 
232 
      @(r15==16'h0208);
233 
      if (mem200 !== 16'h0201) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0201 =====");
234 
      if (mem202 !== 16'h0804) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0804 =====");
235 
      if (mem204 !== 16'h2010) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x2010 =====");
236 
      if (mem206 !== 16'h8040) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x8040 =====");
237 
 
238 
 
239 
      // PORT 2: TEST INTERRUPT VECTOR
240 
      //--------------------------------------------------------
241 
 
242 
      @(r15==16'h0218);
243 
      if (mem210 !== 16'h0201) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0201 =====");
244 
      if (mem212 !== 16'h0804) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x0804 =====");
245 
      if (mem214 !== 16'h2010) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x2010 =====");
246 
      if (mem216 !== 16'h8040) tb_error("====== INTERRUPT VECTOR TEST: P1IFG != 0x8040 =====");
247 
 
248 
 
249 
      stimulus_done = 1;
250 
   end
251 
 

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