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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Blame information for rev 18

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            DIGITAL I/O                                    */
/*---------------------------------------------------------------------------*/
/* Test the Digital I/O interface:                                           */
/*                                   - Read/Write register access.           */
/*                                   - I/O Functionality.                    */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   P1IN,  0x0020
.set   P1OUT, 0x0021
.set   P1DIR, 0x0022
.set   P1IFG, 0x0023
.set   P1IES, 0x0024
.set   P1IE,  0x0025
.set   P1SEL, 0x0026
.set   P2IN,  0x0028
.set   P2OUT, 0x0029
.set   P2DIR, 0x002A
.set   P2IFG, 0x002B
.set   P2IES, 0x002C
.set   P2IE,  0x002D
.set   P2SEL, 0x002E
.set   P3IN,  0x0018
.set   P3OUT, 0x0019
.set   P3DIR, 0x001A
.set   P3SEL, 0x001B
.set   P4IN,  0x001C
.set   P4OUT, 0x001D
.set   P4DIR, 0x001E
.set   P4SEL, 0x001F
.set   P5IN,  0x0030
.set   P5OUT, 0x0031
.set   P5DIR, 0x0032
.set   P5SEL, 0x0033
.set   P6IN,  0x0034
.set   P6OUT, 0x0035
.set   P6DIR, 0x0036
.set   P6SEL, 0x0037
 
main:
        /* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P1IN          ; P1IN
        mov.b &P1IN,  &0x0200
        mov.b #0x55,  &P1IN
        mov.b &P1IN,  &0x0201
 
        mov.b #0xaa,  &P1OUT         ; P1OUT
        mov.b &P1OUT, &0x0202
        mov.b #0x55,  &P1OUT
        mov.b &P1OUT, &0x0203
 
        mov.b #0x5a,  &P1DIR         ; P1DIR
        mov.b &P1DIR, &0x0204
        mov.b #0xa5,  &P1DIR
        mov.b &P1DIR, &0x0205
 
        mov.b #0x55,  &P1IFG         ; P1IFG
        mov.b &P1IFG, &0x0206
        mov.b #0xaa,  &P1IFG
        mov.b &P1IFG, &0x0207
 
        mov.b #0xa5,  &P1IES         ; P1IES
        mov.b &P1IES, &0x0208
        mov.b #0x5a,  &P1IES
        mov.b &P1IES, &0x0209
 
        mov.b #0xaa,  &P1IE          ; P1IE
        mov.b &P1IE,  &0x020A
        mov.b #0x55,  &P1IE
        mov.b &P1IE,  &0x020B
 
        mov.b #0xcd,  &P1SEL         ; P1SEL
        mov.b &P1SEL, &0x020C
        mov.b #0x32,  &P1SEL
        mov.b &P1SEL, &0x020D
 
 
        mov.b #0x00,  &P1IN          ; Re-Initialize
        mov.b #0x00,  &P1OUT
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1IFG
        mov.b #0x00,  &P1IES
        mov.b #0x00,  &P1IE
        mov.b #0x00,  &P1SEL
 
        mov   #0x0001, r15
 
 
        /* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P2IN          ; P2IN
        mov.b &P2IN,  &0x0210
        mov.b #0x55,  &P2IN
        mov.b &P2IN,  &0x0211
 
        mov.b #0xaa,  &P2OUT         ; P2OUT
        mov.b &P2OUT, &0x0212
        mov.b #0x55,  &P2OUT
        mov.b &P2OUT, &0x0213
 
        mov.b #0x5a,  &P2DIR         ; P2DIR
        mov.b &P2DIR, &0x0214
        mov.b #0xa5,  &P2DIR
        mov.b &P2DIR, &0x0215
 
        mov.b #0x55,  &P2IFG         ; P2IFG
        mov.b &P2IFG, &0x0216
        mov.b #0xaa,  &P2IFG
        mov.b &P2IFG, &0x0217
 
        mov.b #0xa5,  &P2IES         ; P2IES
        mov.b &P2IES, &0x0218
        mov.b #0x5a,  &P2IES
        mov.b &P2IES, &0x0219
 
        mov.b #0xaa,  &P2IE          ; P2IE
        mov.b &P2IE,  &0x021A
        mov.b #0x55,  &P2IE
        mov.b &P2IE,  &0x021B
 
        mov.b #0xcd,  &P2SEL         ; P2SEL
        mov.b &P2SEL, &0x021C
        mov.b #0x32,  &P2SEL
        mov.b &P2SEL, &0x021D
 
        mov.b #0x00,  &P2IN          ; Re-Initialize
        mov.b #0x00,  &P2OUT
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2IFG
        mov.b #0x00,  &P2IES
        mov.b #0x00,  &P2IE
        mov.b #0x00,  &P2SEL
 
        mov   #0x0002, r15
 
 
        /* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P3IN          ; P3IN
        mov.b &P3IN,  &0x0220
        mov.b #0x55,  &P3IN
        mov.b &P3IN,  &0x0221
 
        mov.b #0xaa,  &P3OUT         ; P3OUT
        mov.b &P3OUT, &0x0222
        mov.b #0x55,  &P3OUT
        mov.b &P3OUT, &0x0223
 
        mov.b #0x5a,  &P3DIR         ; P3DIR
        mov.b &P3DIR, &0x0224
        mov.b #0xa5,  &P3DIR
        mov.b &P3DIR, &0x0225
 
        mov.b #0xcd,  &P3SEL         ; P3SEL
        mov.b &P3SEL, &0x0226
        mov.b #0x32,  &P3SEL
        mov.b &P3SEL, &0x0227
 
        mov.b #0x00,  &P3IN          ; Re-Initialize
        mov.b #0x00,  &P3OUT
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL
 
        mov   #0x0003, r15
 
 
        /* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P4IN          ; P4IN
        mov.b &P4IN,  &0x0230
        mov.b #0x55,  &P4IN
        mov.b &P4IN,  &0x0231
 
        mov.b #0xaa,  &P4OUT         ; P4OUT
        mov.b &P4OUT, &0x0232
        mov.b #0x55,  &P4OUT
        mov.b &P4OUT, &0x0233
 
        mov.b #0x5a,  &P4DIR         ; P4DIR
        mov.b &P4DIR, &0x0234
        mov.b #0xa5,  &P4DIR
        mov.b &P4DIR, &0x0235
 
        mov.b #0xcd,  &P4SEL         ; P4SEL
        mov.b &P4SEL, &0x0236
        mov.b #0x32,  &P4SEL
        mov.b &P4SEL, &0x0237
 
        mov.b #0x00,  &P4IN          ; Re-Initialize
        mov.b #0x00,  &P4OUT
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL
 
        mov   #0x0004, r15
 
 
        /* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P5IN          ; P5IN
        mov.b &P5IN,  &0x0240
        mov.b #0x55,  &P5IN
        mov.b &P5IN,  &0x0241
 
        mov.b #0xaa,  &P5OUT         ; P5OUT
        mov.b &P5OUT, &0x0242
        mov.b #0x55,  &P5OUT
        mov.b &P5OUT, &0x0243
 
        mov.b #0x5a,  &P5DIR         ; P5DIR
        mov.b &P5DIR, &0x0244
        mov.b #0xa5,  &P5DIR
        mov.b &P5DIR, &0x0245
 
        mov.b #0xcd,  &P5SEL         ; P5SEL
        mov.b &P5SEL, &0x0246
        mov.b #0x32,  &P5SEL
        mov.b &P5SEL, &0x0247
 
        mov.b #0x00,  &P5IN          ; Re-Initialize
        mov.b #0x00,  &P5OUT
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL
 
        mov   #0x0005, r15
 
 
        /* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */
 
        mov.b #0xaa,  &P6IN          ; P6IN
        mov.b &P6IN,  &0x0250
        mov.b #0x55,  &P6IN
        mov.b &P6IN,  &0x0251
 
        mov.b #0xaa,  &P6OUT         ; P6OUT
        mov.b &P6OUT, &0x0252
        mov.b #0x55,  &P6OUT
        mov.b &P6OUT, &0x0253
 
        mov.b #0x5a,  &P6DIR         ; P6DIR
        mov.b &P6DIR, &0x0254
        mov.b #0xa5,  &P6DIR
        mov.b &P6DIR, &0x0255
 
        mov.b #0xcd,  &P6SEL         ; P6SEL
        mov.b &P6SEL, &0x0256
        mov.b #0x32,  &P6SEL
        mov.b &P6SEL, &0x0257
 
        mov.b #0x00,  &P6IN          ; Re-Initialize
        mov.b #0x00,  &P6OUT
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL
 
        mov   #0x0006, r15
 
 
        /* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0200, r15        ;# Test Input path
p1_din_loop:
        mov.b &P1IN,  0(r15)
        inc      r15
        cmp     #0x0208, r15
        jne     p1_din_loop
 
 
        mov.b #0x01,   &P1OUT       ; Test Output path
        mov   #0x1100, r15
p1_dout_loop:
        rla.b &P1OUT
        inc      r15
        cmp     #0x1107, r15
        jne     p1_dout_loop
 
 
        mov.b #0x01,   &P1DIR       ; Test Direction register
        mov   #0x1200, r15
p1_dir_loop:
        rla.b &P1DIR
        inc      r15
        cmp     #0x1207, r15
        jne     p1_dir_loop
 
 
        mov.b #0x01,   &P1SEL       ; Test Function Select register
        mov   #0x1300, r15
p1_sel_loop:
        rla.b &P1SEL
        inc      r15
        cmp     #0x1307, r15
        jne     p1_sel_loop
 
 
        mov.b #0x00,  &P1OUT        ; Re-Initialize
        mov.b #0x00,  &P1DIR
        mov.b #0x00,  &P1SEL
 
 
        /* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0210, r15        ;# Test Input path
p2_din_loop:
        mov.b &P2IN,  0(r15)
        inc      r15
        cmp     #0x0218, r15
        jne     p2_din_loop
 
 
        mov.b #0x01,   &P2OUT       ; Test Output path
        mov   #0x2100, r15
p2_dout_loop:
        rla.b &P2OUT
        inc      r15
        cmp     #0x2107, r15
        jne     p2_dout_loop
 
 
        mov.b #0x01,   &P2DIR       ; Test Direction register
        mov   #0x2200, r15
p2_dir_loop:
        rla.b &P2DIR
        inc      r15
        cmp     #0x2207, r15
        jne     p2_dir_loop
 
 
        mov.b #0x01,   &P2SEL       ; Test Function Select register
        mov   #0x2300, r15
p2_sel_loop:
        rla.b &P2SEL
        inc      r15
        cmp     #0x2307, r15
        jne     p2_sel_loop
 
 
        mov.b #0x00,  &P2OUT        ; Re-Initialize
        mov.b #0x00,  &P2DIR
        mov.b #0x00,  &P2SEL
 
 
        /* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0220, r15        ;# Test Input path
p3_din_loop:
        mov.b &P3IN,  0(r15)
        inc      r15
        cmp     #0x0228, r15
        jne     p3_din_loop
 
 
        mov.b #0x01,   &P3OUT       ; Test Output path
        mov   #0x3100, r15
p3_dout_loop:
        rla.b &P3OUT
        inc      r15
        cmp     #0x3107, r15
        jne     p3_dout_loop
 
 
        mov.b #0x01,   &P3DIR       ; Test Direction register
        mov   #0x3200, r15
p3_dir_loop:
        rla.b &P3DIR
        inc      r15
        cmp     #0x3207, r15
        jne     p3_dir_loop
 
 
        mov.b #0x01,   &P3SEL       ; Test Function Select register
        mov   #0x3300, r15
p3_sel_loop:
        rla.b &P3SEL
        inc      r15
        cmp     #0x3307, r15
        jne     p3_sel_loop
 
 
        mov.b #0x00,  &P3OUT        ; Re-Initialize
        mov.b #0x00,  &P3DIR
        mov.b #0x00,  &P3SEL
 
 
        /* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0230, r15        ;# Test Input path
p4_din_loop:
        mov.b &P4IN,  0(r15)
        inc      r15
        cmp     #0x0238, r15
        jne     p4_din_loop
 
 
        mov.b #0x01,   &P4OUT       ; Test Output path
        mov   #0x4100, r15
p4_dout_loop:
        rla.b &P4OUT
        inc      r15
        cmp     #0x4107, r15
        jne     p4_dout_loop
 
 
        mov.b #0x01,   &P4DIR       ; Test Direction register
        mov   #0x4200, r15
p4_dir_loop:
        rla.b &P4DIR
        inc      r15
        cmp     #0x4207, r15
        jne     p4_dir_loop
 
 
        mov.b #0x01,   &P4SEL       ; Test Function Select register
        mov   #0x4300, r15
p4_sel_loop:
        rla.b &P4SEL
        inc      r15
        cmp     #0x4307, r15
        jne     p4_sel_loop
 
 
        mov.b #0x00,  &P4OUT        ; Re-Initialize
        mov.b #0x00,  &P4DIR
        mov.b #0x00,  &P4SEL
 
 
        /* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0240, r15        ;# Test Input path
p5_din_loop:
        mov.b &P5IN,  0(r15)
        inc      r15
        cmp     #0x0248, r15
        jne     p5_din_loop
 
 
        mov.b #0x01,   &P5OUT       ; Test Output path
        mov   #0x5100, r15
p5_dout_loop:
        rla.b &P5OUT
        inc      r15
        cmp     #0x5107, r15
        jne     p5_dout_loop
 
 
        mov.b #0x01,   &P5DIR       ; Test Direction register
        mov   #0x5200, r15
p5_dir_loop:
        rla.b &P5DIR
        inc      r15
        cmp     #0x5207, r15
        jne     p5_dir_loop
 
 
        mov.b #0x01,   &P5SEL       ; Test Function Select register
        mov   #0x5300, r15
p5_sel_loop:
        rla.b &P5SEL
        inc      r15
        cmp     #0x5307, r15
        jne     p5_sel_loop
 
 
        mov.b #0x00,  &P5OUT        ; Re-Initialize
        mov.b #0x00,  &P5DIR
        mov.b #0x00,  &P5SEL
 
 
        /* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */
 
        mov     #0x0250, r15        ;# Test Input path
p6_din_loop:
        mov.b &P6IN,  0(r15)
        inc      r15
        cmp     #0x0258, r15
        jne     p6_din_loop
 
 
        mov.b #0x01,   &P6OUT       ; Test Output path
        mov   #0x6100, r15
p6_dout_loop:
        rla.b &P6OUT
        inc      r15
        cmp     #0x6107, r15
        jne     p6_dout_loop
 
 
        mov.b #0x01,   &P6DIR       ; Test Direction register
        mov   #0x6200, r15
p6_dir_loop:
        rla.b &P6DIR
        inc      r15
        cmp     #0x6207, r15
        jne     p6_dir_loop
 
 
        mov.b #0x01,   &P6SEL       ; Test Function Select register
        mov   #0x6300, r15
p6_sel_loop:
        rla.b &P6SEL
        inc      r15
        cmp     #0x6307, r15
        jne     p6_sel_loop
 
 
        mov.b #0x00,  &P6OUT        ; Re-Initialize
        mov.b #0x00,  &P6DIR
        mov.b #0x00,  &P6SEL
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.s43] - Blame information for rev 18

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* DIGITAL I/O */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Digital I/O interface: */`
27			`/* - Read/Write register access. */`
28			`/* - I/O Functionality. */`
29	18	olivier.gi	`/* */`
30			`/* Author(s): */`
31			`/* - Olivier Girard, olgirard@gmail.com */`
32			`/* */`
33			`/---------------------------------------------------------------------------/`
34			`/* $Rev: 17 $ */`
35			`/* $LastChangedBy: olivier.girard $ */`
36			`/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */`
37	2	olivier.gi	`/===========================================================================/`
38
39			`.global main`
40
41			`.set P1IN, 0x0020`
42			`.set P1OUT, 0x0021`
43			`.set P1DIR, 0x0022`
44			`.set P1IFG, 0x0023`
45			`.set P1IES, 0x0024`
46			`.set P1IE, 0x0025`
47			`.set P1SEL, 0x0026`
48			`.set P2IN, 0x0028`
49			`.set P2OUT, 0x0029`
50			`.set P2DIR, 0x002A`
51			`.set P2IFG, 0x002B`
52			`.set P2IES, 0x002C`
53			`.set P2IE, 0x002D`
54			`.set P2SEL, 0x002E`
55			`.set P3IN, 0x0018`
56			`.set P3OUT, 0x0019`
57			`.set P3DIR, 0x001A`
58			`.set P3SEL, 0x001B`
59			`.set P4IN, 0x001C`
60			`.set P4OUT, 0x001D`
61			`.set P4DIR, 0x001E`
62			`.set P4SEL, 0x001F`
63			`.set P5IN, 0x0030`
64			`.set P5OUT, 0x0031`
65			`.set P5DIR, 0x0032`
66			`.set P5SEL, 0x0033`
67			`.set P6IN, 0x0034`
68			`.set P6OUT, 0x0035`
69			`.set P6DIR, 0x0036`
70			`.set P6SEL, 0x0037`
71
72			`main:`
73			`/* -------------- PORT 1: TEST RD/WR REGISTER ACCESS --------------- */`
74
75			`mov.b #0xaa, &P1IN ; P1IN`
76			`mov.b &P1IN, &0x0200`
77			`mov.b #0x55, &P1IN`
78			`mov.b &P1IN, &0x0201`
79
80			`mov.b #0xaa, &P1OUT ; P1OUT`
81			`mov.b &P1OUT, &0x0202`
82			`mov.b #0x55, &P1OUT`
83			`mov.b &P1OUT, &0x0203`
84
85			`mov.b #0x5a, &P1DIR ; P1DIR`
86			`mov.b &P1DIR, &0x0204`
87			`mov.b #0xa5, &P1DIR`
88			`mov.b &P1DIR, &0x0205`
89
90			`mov.b #0x55, &P1IFG ; P1IFG`
91			`mov.b &P1IFG, &0x0206`
92			`mov.b #0xaa, &P1IFG`
93			`mov.b &P1IFG, &0x0207`
94
95			`mov.b #0xa5, &P1IES ; P1IES`
96			`mov.b &P1IES, &0x0208`
97			`mov.b #0x5a, &P1IES`
98			`mov.b &P1IES, &0x0209`
99
100			`mov.b #0xaa, &P1IE ; P1IE`
101			`mov.b &P1IE, &0x020A`
102			`mov.b #0x55, &P1IE`
103			`mov.b &P1IE, &0x020B`
104
105			`mov.b #0xcd, &P1SEL ; P1SEL`
106			`mov.b &P1SEL, &0x020C`
107			`mov.b #0x32, &P1SEL`
108			`mov.b &P1SEL, &0x020D`
109
110
111			`mov.b #0x00, &P1IN ; Re-Initialize`
112			`mov.b #0x00, &P1OUT`
113			`mov.b #0x00, &P1DIR`
114			`mov.b #0x00, &P1IFG`
115			`mov.b #0x00, &P1IES`
116			`mov.b #0x00, &P1IE`
117			`mov.b #0x00, &P1SEL`
118
119			`mov #0x0001, r15`
120
121
122			`/* -------------- PORT 2: TEST RD/WR REGISTER ACCESS --------------- */`
123
124			`mov.b #0xaa, &P2IN ; P2IN`
125			`mov.b &P2IN, &0x0210`
126			`mov.b #0x55, &P2IN`
127			`mov.b &P2IN, &0x0211`
128
129			`mov.b #0xaa, &P2OUT ; P2OUT`
130			`mov.b &P2OUT, &0x0212`
131			`mov.b #0x55, &P2OUT`
132			`mov.b &P2OUT, &0x0213`
133
134			`mov.b #0x5a, &P2DIR ; P2DIR`
135			`mov.b &P2DIR, &0x0214`
136			`mov.b #0xa5, &P2DIR`
137			`mov.b &P2DIR, &0x0215`
138
139			`mov.b #0x55, &P2IFG ; P2IFG`
140			`mov.b &P2IFG, &0x0216`
141			`mov.b #0xaa, &P2IFG`
142			`mov.b &P2IFG, &0x0217`
143
144			`mov.b #0xa5, &P2IES ; P2IES`
145			`mov.b &P2IES, &0x0218`
146			`mov.b #0x5a, &P2IES`
147			`mov.b &P2IES, &0x0219`
148
149			`mov.b #0xaa, &P2IE ; P2IE`
150			`mov.b &P2IE, &0x021A`
151			`mov.b #0x55, &P2IE`
152			`mov.b &P2IE, &0x021B`
153
154			`mov.b #0xcd, &P2SEL ; P2SEL`
155			`mov.b &P2SEL, &0x021C`
156			`mov.b #0x32, &P2SEL`
157			`mov.b &P2SEL, &0x021D`
158
159			`mov.b #0x00, &P2IN ; Re-Initialize`
160			`mov.b #0x00, &P2OUT`
161			`mov.b #0x00, &P2DIR`
162			`mov.b #0x00, &P2IFG`
163			`mov.b #0x00, &P2IES`
164			`mov.b #0x00, &P2IE`
165			`mov.b #0x00, &P2SEL`
166
167			`mov #0x0002, r15`
168
169
170			`/* -------------- PORT 3: TEST RD/WR REGISTER ACCESS --------------- */`
171
172			`mov.b #0xaa, &P3IN ; P3IN`
173			`mov.b &P3IN, &0x0220`
174			`mov.b #0x55, &P3IN`
175			`mov.b &P3IN, &0x0221`
176
177			`mov.b #0xaa, &P3OUT ; P3OUT`
178			`mov.b &P3OUT, &0x0222`
179			`mov.b #0x55, &P3OUT`
180			`mov.b &P3OUT, &0x0223`
181
182			`mov.b #0x5a, &P3DIR ; P3DIR`
183			`mov.b &P3DIR, &0x0224`
184			`mov.b #0xa5, &P3DIR`
185			`mov.b &P3DIR, &0x0225`
186
187			`mov.b #0xcd, &P3SEL ; P3SEL`
188			`mov.b &P3SEL, &0x0226`
189			`mov.b #0x32, &P3SEL`
190			`mov.b &P3SEL, &0x0227`
191
192			`mov.b #0x00, &P3IN ; Re-Initialize`
193			`mov.b #0x00, &P3OUT`
194			`mov.b #0x00, &P3DIR`
195			`mov.b #0x00, &P3SEL`
196
197			`mov #0x0003, r15`
198
199
200			`/* -------------- PORT 4: TEST RD/WR REGISTER ACCESS --------------- */`
201
202			`mov.b #0xaa, &P4IN ; P4IN`
203			`mov.b &P4IN, &0x0230`
204			`mov.b #0x55, &P4IN`
205			`mov.b &P4IN, &0x0231`
206
207			`mov.b #0xaa, &P4OUT ; P4OUT`
208			`mov.b &P4OUT, &0x0232`
209			`mov.b #0x55, &P4OUT`
210			`mov.b &P4OUT, &0x0233`
211
212			`mov.b #0x5a, &P4DIR ; P4DIR`
213			`mov.b &P4DIR, &0x0234`
214			`mov.b #0xa5, &P4DIR`
215			`mov.b &P4DIR, &0x0235`
216
217			`mov.b #0xcd, &P4SEL ; P4SEL`
218			`mov.b &P4SEL, &0x0236`
219			`mov.b #0x32, &P4SEL`
220			`mov.b &P4SEL, &0x0237`
221
222			`mov.b #0x00, &P4IN ; Re-Initialize`
223			`mov.b #0x00, &P4OUT`
224			`mov.b #0x00, &P4DIR`
225			`mov.b #0x00, &P4SEL`
226
227			`mov #0x0004, r15`
228
229
230			`/* -------------- PORT 5: TEST RD/WR REGISTER ACCESS --------------- */`
231
232			`mov.b #0xaa, &P5IN ; P5IN`
233			`mov.b &P5IN, &0x0240`
234			`mov.b #0x55, &P5IN`
235			`mov.b &P5IN, &0x0241`
236
237			`mov.b #0xaa, &P5OUT ; P5OUT`
238			`mov.b &P5OUT, &0x0242`
239			`mov.b #0x55, &P5OUT`
240			`mov.b &P5OUT, &0x0243`
241
242			`mov.b #0x5a, &P5DIR ; P5DIR`
243			`mov.b &P5DIR, &0x0244`
244			`mov.b #0xa5, &P5DIR`
245			`mov.b &P5DIR, &0x0245`
246
247			`mov.b #0xcd, &P5SEL ; P5SEL`
248			`mov.b &P5SEL, &0x0246`
249			`mov.b #0x32, &P5SEL`
250			`mov.b &P5SEL, &0x0247`
251
252			`mov.b #0x00, &P5IN ; Re-Initialize`
253			`mov.b #0x00, &P5OUT`
254			`mov.b #0x00, &P5DIR`
255			`mov.b #0x00, &P5SEL`
256
257			`mov #0x0005, r15`
258
259
260			`/* -------------- PORT 6: TEST RD/WR REGISTER ACCESS --------------- */`
261
262			`mov.b #0xaa, &P6IN ; P6IN`
263			`mov.b &P6IN, &0x0250`
264			`mov.b #0x55, &P6IN`
265			`mov.b &P6IN, &0x0251`
266
267			`mov.b #0xaa, &P6OUT ; P6OUT`
268			`mov.b &P6OUT, &0x0252`
269			`mov.b #0x55, &P6OUT`
270			`mov.b &P6OUT, &0x0253`
271
272			`mov.b #0x5a, &P6DIR ; P6DIR`
273			`mov.b &P6DIR, &0x0254`
274			`mov.b #0xa5, &P6DIR`
275			`mov.b &P6DIR, &0x0255`
276
277			`mov.b #0xcd, &P6SEL ; P6SEL`
278			`mov.b &P6SEL, &0x0256`
279			`mov.b #0x32, &P6SEL`
280			`mov.b &P6SEL, &0x0257`
281
282			`mov.b #0x00, &P6IN ; Re-Initialize`
283			`mov.b #0x00, &P6OUT`
284			`mov.b #0x00, &P6DIR`
285			`mov.b #0x00, &P6SEL`
286
287			`mov #0x0006, r15`
288
289
290			`/* -------------- PORT 1: TEST I/O FUNCTIONALITY --------------- */`
291
292			`mov #0x0200, r15 ;# Test Input path`
293			`p1_din_loop:`
294			`mov.b &P1IN, 0(r15)`
295			`inc r15`
296			`cmp #0x0208, r15`
297			`jne p1_din_loop`
298
299
300			`mov.b #0x01, &P1OUT ; Test Output path`
301			`mov #0x1100, r15`
302			`p1_dout_loop:`
303			`rla.b &P1OUT`
304			`inc r15`
305			`cmp #0x1107, r15`
306			`jne p1_dout_loop`
307
308
309			`mov.b #0x01, &P1DIR ; Test Direction register`
310			`mov #0x1200, r15`
311			`p1_dir_loop:`
312			`rla.b &P1DIR`
313			`inc r15`
314			`cmp #0x1207, r15`
315			`jne p1_dir_loop`
316
317
318			`mov.b #0x01, &P1SEL ; Test Function Select register`
319			`mov #0x1300, r15`
320			`p1_sel_loop:`
321			`rla.b &P1SEL`
322			`inc r15`
323			`cmp #0x1307, r15`
324			`jne p1_sel_loop`
325
326
327			`mov.b #0x00, &P1OUT ; Re-Initialize`
328			`mov.b #0x00, &P1DIR`
329			`mov.b #0x00, &P1SEL`
330
331
332			`/* -------------- PORT 2: TEST I/O FUNCTIONALITY --------------- */`
333
334			`mov #0x0210, r15 ;# Test Input path`
335			`p2_din_loop:`
336			`mov.b &P2IN, 0(r15)`
337			`inc r15`
338			`cmp #0x0218, r15`
339			`jne p2_din_loop`
340
341
342			`mov.b #0x01, &P2OUT ; Test Output path`
343			`mov #0x2100, r15`
344			`p2_dout_loop:`
345			`rla.b &P2OUT`
346			`inc r15`
347			`cmp #0x2107, r15`
348			`jne p2_dout_loop`
349
350
351			`mov.b #0x01, &P2DIR ; Test Direction register`
352			`mov #0x2200, r15`
353			`p2_dir_loop:`
354			`rla.b &P2DIR`
355			`inc r15`
356			`cmp #0x2207, r15`
357			`jne p2_dir_loop`
358
359
360			`mov.b #0x01, &P2SEL ; Test Function Select register`
361			`mov #0x2300, r15`
362			`p2_sel_loop:`
363			`rla.b &P2SEL`
364			`inc r15`
365			`cmp #0x2307, r15`
366			`jne p2_sel_loop`
367
368
369			`mov.b #0x00, &P2OUT ; Re-Initialize`
370			`mov.b #0x00, &P2DIR`
371			`mov.b #0x00, &P2SEL`
372
373
374			`/* -------------- PORT 3: TEST I/O FUNCTIONALITY --------------- */`
375
376			`mov #0x0220, r15 ;# Test Input path`
377			`p3_din_loop:`
378			`mov.b &P3IN, 0(r15)`
379			`inc r15`
380			`cmp #0x0228, r15`
381			`jne p3_din_loop`
382
383
384			`mov.b #0x01, &P3OUT ; Test Output path`
385			`mov #0x3100, r15`
386			`p3_dout_loop:`
387			`rla.b &P3OUT`
388			`inc r15`
389			`cmp #0x3107, r15`
390			`jne p3_dout_loop`
391
392
393			`mov.b #0x01, &P3DIR ; Test Direction register`
394			`mov #0x3200, r15`
395			`p3_dir_loop:`
396			`rla.b &P3DIR`
397			`inc r15`
398			`cmp #0x3207, r15`
399			`jne p3_dir_loop`
400
401
402			`mov.b #0x01, &P3SEL ; Test Function Select register`
403			`mov #0x3300, r15`
404			`p3_sel_loop:`
405			`rla.b &P3SEL`
406			`inc r15`
407			`cmp #0x3307, r15`
408			`jne p3_sel_loop`
409
410
411			`mov.b #0x00, &P3OUT ; Re-Initialize`
412			`mov.b #0x00, &P3DIR`
413			`mov.b #0x00, &P3SEL`
414
415
416			`/* -------------- PORT 4: TEST I/O FUNCTIONALITY --------------- */`
417
418			`mov #0x0230, r15 ;# Test Input path`
419			`p4_din_loop:`
420			`mov.b &P4IN, 0(r15)`
421			`inc r15`
422			`cmp #0x0238, r15`
423			`jne p4_din_loop`
424
425
426			`mov.b #0x01, &P4OUT ; Test Output path`
427			`mov #0x4100, r15`
428			`p4_dout_loop:`
429			`rla.b &P4OUT`
430			`inc r15`
431			`cmp #0x4107, r15`
432			`jne p4_dout_loop`
433
434
435			`mov.b #0x01, &P4DIR ; Test Direction register`
436			`mov #0x4200, r15`
437			`p4_dir_loop:`
438			`rla.b &P4DIR`
439			`inc r15`
440			`cmp #0x4207, r15`
441			`jne p4_dir_loop`
442
443
444			`mov.b #0x01, &P4SEL ; Test Function Select register`
445			`mov #0x4300, r15`
446			`p4_sel_loop:`
447			`rla.b &P4SEL`
448			`inc r15`
449			`cmp #0x4307, r15`
450			`jne p4_sel_loop`
451
452
453			`mov.b #0x00, &P4OUT ; Re-Initialize`
454			`mov.b #0x00, &P4DIR`
455			`mov.b #0x00, &P4SEL`
456
457
458			`/* -------------- PORT 5: TEST I/O FUNCTIONALITY --------------- */`
459
460			`mov #0x0240, r15 ;# Test Input path`
461			`p5_din_loop:`
462			`mov.b &P5IN, 0(r15)`
463			`inc r15`
464			`cmp #0x0248, r15`
465			`jne p5_din_loop`
466
467
468			`mov.b #0x01, &P5OUT ; Test Output path`
469			`mov #0x5100, r15`
470			`p5_dout_loop:`
471			`rla.b &P5OUT`
472			`inc r15`
473			`cmp #0x5107, r15`
474			`jne p5_dout_loop`
475
476
477			`mov.b #0x01, &P5DIR ; Test Direction register`
478			`mov #0x5200, r15`
479			`p5_dir_loop:`
480			`rla.b &P5DIR`
481			`inc r15`
482			`cmp #0x5207, r15`
483			`jne p5_dir_loop`
484
485
486			`mov.b #0x01, &P5SEL ; Test Function Select register`
487			`mov #0x5300, r15`
488			`p5_sel_loop:`
489			`rla.b &P5SEL`
490			`inc r15`
491			`cmp #0x5307, r15`
492			`jne p5_sel_loop`
493
494
495			`mov.b #0x00, &P5OUT ; Re-Initialize`
496			`mov.b #0x00, &P5DIR`
497			`mov.b #0x00, &P5SEL`
498
499
500			`/* -------------- PORT 6: TEST I/O FUNCTIONALITY --------------- */`
501
502			`mov #0x0250, r15 ;# Test Input path`
503			`p6_din_loop:`
504			`mov.b &P6IN, 0(r15)`
505			`inc r15`
506			`cmp #0x0258, r15`
507			`jne p6_din_loop`
508
509
510			`mov.b #0x01, &P6OUT ; Test Output path`
511			`mov #0x6100, r15`
512			`p6_dout_loop:`
513			`rla.b &P6OUT`
514			`inc r15`
515			`cmp #0x6107, r15`
516			`jne p6_dout_loop`
517
518
519			`mov.b #0x01, &P6DIR ; Test Direction register`
520			`mov #0x6200, r15`
521			`p6_dir_loop:`
522			`rla.b &P6DIR`
523			`inc r15`
524			`cmp #0x6207, r15`
525			`jne p6_dir_loop`
526
527
528			`mov.b #0x01, &P6SEL ; Test Function Select register`
529			`mov #0x6300, r15`
530			`p6_sel_loop:`
531			`rla.b &P6SEL`
532			`inc r15`
533			`cmp #0x6307, r15`
534			`jne p6_sel_loop`
535
536
537			`mov.b #0x00, &P6OUT ; Re-Initialize`
538			`mov.b #0x00, &P6DIR`
539			`mov.b #0x00, &P6SEL`
540
541
542
543			`/* ---------------------- END OF TEST --------------- */`
544			`end_of_test:`
545			`nop`
546			`br #0xffff`
547
548
549			`/* ---------------------- INTERRUPT VECTORS --------------- */`
550
551			`.section .vectors, "a"`
552			`.word end_of_test ; Interrupt 0 (lowest priority)`
553			`.word end_of_test ; Interrupt 1`
554			`.word end_of_test ; Interrupt 2`
555			`.word end_of_test ; Interrupt 3`
556			`.word end_of_test ; Interrupt 4`
557			`.word end_of_test ; Interrupt 5`
558			`.word end_of_test ; Interrupt 6`
559			`.word end_of_test ; Interrupt 7`
560			`.word end_of_test ; Interrupt 8`
561			`.word end_of_test ; Interrupt 9`
562			`.word end_of_test ; Interrupt 10 Watchdog timer`
563			`.word end_of_test ; Interrupt 11`
564			`.word end_of_test ; Interrupt 12`
565			`.word end_of_test ; Interrupt 13`
566			`.word end_of_test ; Interrupt 14 NMI`
567			`.word main ; Interrupt 15 (highest priority) RESET`