OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [gpio_rdwr.v] - Blame information for rev 76

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                 DIGITAL I/O                               */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the Digital I/O interface:                                           */
27 
/*                                   - Read/Write register access.           */
28 
/*                                   - I/O Functionality.                    */
29 18 olivier.gi 
/*                                                                           */
30 
/* Author(s):                                                                */
31 
/*             - Olivier Girard,    olgirard@gmail.com                       */
32 
/*                                                                           */
33 
/*---------------------------------------------------------------------------*/
34 19 olivier.gi 
/* $Rev: 19 $                                                                */
35 
/* $LastChangedBy: olivier.girard $                                          */
36 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
37 2 olivier.gi 
/*===========================================================================*/
38 
 
39 
initial
40 
   begin
41 
      $display(" ===============================================");
42 
      $display("|                 START SIMULATION              |");
43 
      $display(" ===============================================");
44 
      repeat(5) @(posedge mclk);
45 
      stimulus_done = 0;
46 
 
47 
      // PORT 1: TEST RD/WR REGISTER ACCESS
48 
      //--------------------------------------------------------
49 
      @(r15==16'h0001);
50 
 
51 
      if (mem200 !== 16'h0000) tb_error("====== P1IN  != 0x0000 =====");
52 
      if (mem202 !== 16'h55aa) tb_error("====== P1OUT != 0x55aa =====");
53 
      if (mem204 !== 16'ha55a) tb_error("====== P1DIR != 0xa55a =====");
54 
      if (mem206 !== 16'haa55) tb_error("====== P1IFG != 0xaa55 =====");
55 
      if (mem208 !== 16'h5aa5) tb_error("====== P1IES != 0x5aa5 =====");
56 
      if (mem20A !== 16'h55aa) tb_error("====== P1IE  != 0x55aa =====");
57 
      if (mem20C !== 16'h32cd) tb_error("====== P1SEL != 0x32cd =====");
58 
 
59 
 
60 
      // PORT 2: TEST RD/WR REGISTER ACCESS
61 
      //--------------------------------------------------------
62 
      @(r15==16'h0002);
63 
 
64 
      if (mem210 !== 16'h0000) tb_error("====== P2IN  != 0x0000 =====");
65 
      if (mem212 !== 16'h55aa) tb_error("====== P2OUT != 0x55aa =====");
66 
      if (mem214 !== 16'ha55a) tb_error("====== P2DIR != 0xa55a =====");
67 
      if (mem216 !== 16'haa55) tb_error("====== P2IFG != 0xaa55 =====");
68 
      if (mem218 !== 16'h5aa5) tb_error("====== P2IES != 0x5aa5 =====");
69 
      if (mem21A !== 16'h55aa) tb_error("====== P2IE  != 0x55aa =====");
70 
      if (mem21C !== 16'h32cd) tb_error("====== P2SEL != 0x32cd =====");
71 
 
72 
 
73 
      // PORT 3: TEST RD/WR REGISTER ACCESS
74 
      //--------------------------------------------------------
75 
      @(r15==16'h0003);
76 
 
77 
      if (mem220 !== 16'h0000) tb_error("====== P3IN  != 0x0000 =====");
78 
      if (mem222 !== 16'h55aa) tb_error("====== P3OUT != 0x55aa =====");
79 
      if (mem224 !== 16'ha55a) tb_error("====== P3DIR != 0xa55a =====");
80 
      if (mem226 !== 16'h32cd) tb_error("====== P3SEL != 0x32cd =====");
81 
 
82 
 
83 
      // PORT 4: TEST RD/WR REGISTER ACCESS
84 
      //--------------------------------------------------------
85 
      @(r15==16'h0004);
86 
 
87 
      if (mem230 !== 16'h0000) tb_error("====== P4IN  != 0x0000 =====");
88 
      if (mem232 !== 16'h55aa) tb_error("====== P4OUT != 0x55aa =====");
89 
      if (mem234 !== 16'ha55a) tb_error("====== P4DIR != 0xa55a =====");
90 
      if (mem236 !== 16'h32cd) tb_error("====== P4SEL != 0x32cd =====");
91 
 
92 
 
93 
      // PORT 5: TEST RD/WR REGISTER ACCESS
94 
      //--------------------------------------------------------
95 
      @(r15==16'h0005);
96 
 
97 
      if (mem240 !== 16'h0000) tb_error("====== P5IN  != 0x0000 =====");
98 
      if (mem242 !== 16'h55aa) tb_error("====== P5OUT != 0x55aa =====");
99 
      if (mem244 !== 16'ha55a) tb_error("====== P5DIR != 0xa55a =====");
100 
      if (mem246 !== 16'h32cd) tb_error("====== P5SEL != 0x32cd =====");
101 
 
102 
 
103 
      // PORT 6: TEST RD/WR REGISTER ACCESS
104 
      //--------------------------------------------------------
105 
      @(r15==16'h0006);
106 
 
107 
      if (mem250 !== 16'h0000) tb_error("====== P6IN  != 0x0000 =====");
108 
      if (mem252 !== 16'h55aa) tb_error("====== P6OUT != 0x55aa =====");
109 
      if (mem254 !== 16'ha55a) tb_error("====== P6DIR != 0xa55a =====");
110 
      if (mem256 !== 16'h32cd) tb_error("====== P6SEL != 0x32cd =====");
111 
 
112 
 
113 
      // PORT 1: TEST I/O FUNCTIONALITY
114 
      //--------------------------------------------------------
115 
 
116 
      @(r15==16'h0200) p1_din = 8'h01;
117 
      @(r15==16'h0201) p1_din = 8'h02;
118 
      @(r15==16'h0202) p1_din = 8'h04;
119 
      @(r15==16'h0203) p1_din = 8'h08;
120 
      @(r15==16'h0204) p1_din = 8'h10;
121 
      @(r15==16'h0205) p1_din = 8'h20;
122 
      @(r15==16'h0206) p1_din = 8'h40;
123 
      @(r15==16'h0207) p1_din = 8'h80;
124 
      @(r15==16'h0208);
125 
      if (mem200 !== 16'h0201) tb_error("====== P1IN  != 0x0201 =====");
126 
      if (mem202 !== 16'h0804) tb_error("====== P1IN  != 0x0804 =====");
127 
      if (mem204 !== 16'h2010) tb_error("====== P1IN  != 0x2010 =====");
128 
      if (mem206 !== 16'h8040) tb_error("====== P1IN  != 0x8040 =====");
129 
 
130 
      @(r15==16'h1100);
131 
      if (p1_dout !== 8'h01) tb_error("====== P1DOUT  != 0x01 =====");
132 
      @(r15==16'h1101);
133 
      if (p1_dout !== 8'h02) tb_error("====== P1DOUT  != 0x02 =====");
134 
      @(r15==16'h1102);
135 
      if (p1_dout !== 8'h04) tb_error("====== P1DOUT  != 0x04 =====");
136 
      @(r15==16'h1103);
137 
      if (p1_dout !== 8'h08) tb_error("====== P1DOUT  != 0x08 =====");
138 
      @(r15==16'h1104);
139 
      if (p1_dout !== 8'h10) tb_error("====== P1DOUT  != 0x10 =====");
140 
      @(r15==16'h1105);
141 
      if (p1_dout !== 8'h20) tb_error("====== P1DOUT  != 0x20 =====");
142 
      @(r15==16'h1106);
143 
      if (p1_dout !== 8'h40) tb_error("====== P1DOUT  != 0x40 =====");
144 
      @(r15==16'h1107);
145 
      if (p1_dout !== 8'h80) tb_error("====== P1DOUT  != 0x80 =====");
146 
 
147 
      @(r15==16'h1200);
148 
      if (p1_dout_en !== 8'h01) tb_error("====== P1DIR  != 0x01 =====");
149 
      @(r15==16'h1201);
150 
      if (p1_dout_en !== 8'h02) tb_error("====== P1DIR  != 0x02 =====");
151 
      @(r15==16'h1202);
152 
      if (p1_dout_en !== 8'h04) tb_error("====== P1DIR  != 0x04 =====");
153 
      @(r15==16'h1203);
154 
      if (p1_dout_en !== 8'h08) tb_error("====== P1DIR  != 0x08 =====");
155 
      @(r15==16'h1204);
156 
      if (p1_dout_en !== 8'h10) tb_error("====== P1DIR  != 0x10 =====");
157 
      @(r15==16'h1205);
158 
      if (p1_dout_en !== 8'h20) tb_error("====== P1DIR  != 0x20 =====");
159 
      @(r15==16'h1206);
160 
      if (p1_dout_en !== 8'h40) tb_error("====== P1DIR  != 0x40 =====");
161 
      @(r15==16'h1207);
162 
      if (p1_dout_en !== 8'h80) tb_error("====== P1DIR  != 0x80 =====");
163 
 
164 
      @(r15==16'h1300);
165 
      if (p1_sel !== 8'h01) tb_error("====== P1SEL  != 0x01 =====");
166 
      @(r15==16'h1301);
167 
      if (p1_sel !== 8'h02) tb_error("====== P1SEL  != 0x02 =====");
168 
      @(r15==16'h1302);
169 
      if (p1_sel !== 8'h04) tb_error("====== P1SEL  != 0x04 =====");
170 
      @(r15==16'h1303);
171 
      if (p1_sel !== 8'h08) tb_error("====== P1SEL  != 0x08 =====");
172 
      @(r15==16'h1304);
173 
      if (p1_sel !== 8'h10) tb_error("====== P1SEL  != 0x10 =====");
174 
      @(r15==16'h1305);
175 
      if (p1_sel !== 8'h20) tb_error("====== P1SEL  != 0x20 =====");
176 
      @(r15==16'h1306);
177 
      if (p1_sel !== 8'h40) tb_error("====== P1SEL  != 0x40 =====");
178 
      @(r15==16'h1307);
179 
      if (p1_sel !== 8'h80) tb_error("====== P1SEL  != 0x80 =====");
180 
 
181 
 
182 
      // PORT 2: TEST I/O FUNCTIONALITY
183 
      //--------------------------------------------------------
184 
 
185 
      @(r15==16'h0210) p2_din = 8'h01;
186 
      @(r15==16'h0211) p2_din = 8'h02;
187 
      @(r15==16'h0212) p2_din = 8'h04;
188 
      @(r15==16'h0213) p2_din = 8'h08;
189 
      @(r15==16'h0214) p2_din = 8'h10;
190 
      @(r15==16'h0215) p2_din = 8'h20;
191 
      @(r15==16'h0216) p2_din = 8'h40;
192 
      @(r15==16'h0217) p2_din = 8'h80;
193 
      @(r15==16'h0218);
194 
      if (mem210 !== 16'h0201) tb_error("====== P2IN  != 0x0201 =====");
195 
      if (mem212 !== 16'h0804) tb_error("====== P2IN  != 0x0804 =====");
196 
      if (mem214 !== 16'h2010) tb_error("====== P2IN  != 0x2010 =====");
197 
      if (mem216 !== 16'h8040) tb_error("====== P2IN  != 0x8040 =====");
198 
 
199 
      @(r15==16'h2100);
200 
      if (p2_dout !== 8'h01) tb_error("====== P2DOUT  != 0x01 =====");
201 
      @(r15==16'h2101);
202 
      if (p2_dout !== 8'h02) tb_error("====== P2DOUT  != 0x02 =====");
203 
      @(r15==16'h2102);
204 
      if (p2_dout !== 8'h04) tb_error("====== P2DOUT  != 0x04 =====");
205 
      @(r15==16'h2103);
206 
      if (p2_dout !== 8'h08) tb_error("====== P2DOUT  != 0x08 =====");
207 
      @(r15==16'h2104);
208 
      if (p2_dout !== 8'h10) tb_error("====== P2DOUT  != 0x10 =====");
209 
      @(r15==16'h2105);
210 
      if (p2_dout !== 8'h20) tb_error("====== P2DOUT  != 0x20 =====");
211 
      @(r15==16'h2106);
212 
      if (p2_dout !== 8'h40) tb_error("====== P2DOUT  != 0x40 =====");
213 
      @(r15==16'h2107);
214 
      if (p2_dout !== 8'h80) tb_error("====== P2DOUT  != 0x80 =====");
215 
 
216 
      @(r15==16'h2200);
217 
      if (p2_dout_en !== 8'h01) tb_error("====== P2DIR  != 0x01 =====");
218 
      @(r15==16'h2201);
219 
      if (p2_dout_en !== 8'h02) tb_error("====== P2DIR  != 0x02 =====");
220 
      @(r15==16'h2202);
221 
      if (p2_dout_en !== 8'h04) tb_error("====== P2DIR  != 0x04 =====");
222 
      @(r15==16'h2203);
223 
      if (p2_dout_en !== 8'h08) tb_error("====== P2DIR  != 0x08 =====");
224 
      @(r15==16'h2204);
225 
      if (p2_dout_en !== 8'h10) tb_error("====== P2DIR  != 0x10 =====");
226 
      @(r15==16'h2205);
227 
      if (p2_dout_en !== 8'h20) tb_error("====== P2DIR  != 0x20 =====");
228 
      @(r15==16'h2206);
229 
      if (p2_dout_en !== 8'h40) tb_error("====== P2DIR  != 0x40 =====");
230 
      @(r15==16'h2207);
231 
      if (p2_dout_en !== 8'h80) tb_error("====== P2DIR  != 0x80 =====");
232 
 
233 
      @(r15==16'h2300);
234 
      if (p2_sel !== 8'h01) tb_error("====== P2SEL  != 0x01 =====");
235 
      @(r15==16'h2301);
236 
      if (p2_sel !== 8'h02) tb_error("====== P2SEL  != 0x02 =====");
237 
      @(r15==16'h2302);
238 
      if (p2_sel !== 8'h04) tb_error("====== P2SEL  != 0x04 =====");
239 
      @(r15==16'h2303);
240 
      if (p2_sel !== 8'h08) tb_error("====== P2SEL  != 0x08 =====");
241 
      @(r15==16'h2304);
242 
      if (p2_sel !== 8'h10) tb_error("====== P2SEL  != 0x10 =====");
243 
      @(r15==16'h2305);
244 
      if (p2_sel !== 8'h20) tb_error("====== P2SEL  != 0x20 =====");
245 
      @(r15==16'h2306);
246 
      if (p2_sel !== 8'h40) tb_error("====== P2SEL  != 0x40 =====");
247 
      @(r15==16'h2307);
248 
      if (p2_sel !== 8'h80) tb_error("====== P2SEL  != 0x80 =====");
249 
 
250 
 
251 
      // PORT 3: TEST I/O FUNCTIONALITY
252 
      //--------------------------------------------------------
253 
 
254 
      @(r15==16'h0220) p3_din = 8'h01;
255 
      @(r15==16'h0221) p3_din = 8'h02;
256 
      @(r15==16'h0222) p3_din = 8'h04;
257 
      @(r15==16'h0223) p3_din = 8'h08;
258 
      @(r15==16'h0224) p3_din = 8'h10;
259 
      @(r15==16'h0225) p3_din = 8'h20;
260 
      @(r15==16'h0226) p3_din = 8'h40;
261 
      @(r15==16'h0227) p3_din = 8'h80;
262 
      @(r15==16'h0228);
263 
      if (mem220 !== 16'h0201) tb_error("====== P3IN  != 0x0201 =====");
264 
      if (mem222 !== 16'h0804) tb_error("====== P3IN  != 0x0804 =====");
265 
      if (mem224 !== 16'h2010) tb_error("====== P3IN  != 0x2010 =====");
266 
      if (mem226 !== 16'h8040) tb_error("====== P3IN  != 0x8040 =====");
267 
 
268 
      @(r15==16'h3100);
269 
      if (p3_dout !== 8'h01) tb_error("====== P3DOUT  != 0x01 =====");
270 
      @(r15==16'h3101);
271 
      if (p3_dout !== 8'h02) tb_error("====== P3DOUT  != 0x02 =====");
272 
      @(r15==16'h3102);
273 
      if (p3_dout !== 8'h04) tb_error("====== P3DOUT  != 0x04 =====");
274 
      @(r15==16'h3103);
275 
      if (p3_dout !== 8'h08) tb_error("====== P3DOUT  != 0x08 =====");
276 
      @(r15==16'h3104);
277 
      if (p3_dout !== 8'h10) tb_error("====== P3DOUT  != 0x10 =====");
278 
      @(r15==16'h3105);
279 
      if (p3_dout !== 8'h20) tb_error("====== P3DOUT  != 0x20 =====");
280 
      @(r15==16'h3106);
281 
      if (p3_dout !== 8'h40) tb_error("====== P3DOUT  != 0x40 =====");
282 
      @(r15==16'h3107);
283 
      if (p3_dout !== 8'h80) tb_error("====== P3DOUT  != 0x80 =====");
284 
 
285 
      @(r15==16'h3200);
286 
      if (p3_dout_en !== 8'h01) tb_error("====== P3DIR  != 0x01 =====");
287 
      @(r15==16'h3201);
288 
      if (p3_dout_en !== 8'h02) tb_error("====== P3DIR  != 0x02 =====");
289 
      @(r15==16'h3202);
290 
      if (p3_dout_en !== 8'h04) tb_error("====== P3DIR  != 0x04 =====");
291 
      @(r15==16'h3203);
292 
      if (p3_dout_en !== 8'h08) tb_error("====== P3DIR  != 0x08 =====");
293 
      @(r15==16'h3204);
294 
      if (p3_dout_en !== 8'h10) tb_error("====== P3DIR  != 0x10 =====");
295 
      @(r15==16'h3205);
296 
      if (p3_dout_en !== 8'h20) tb_error("====== P3DIR  != 0x20 =====");
297 
      @(r15==16'h3206);
298 
      if (p3_dout_en !== 8'h40) tb_error("====== P3DIR  != 0x40 =====");
299 
      @(r15==16'h3207);
300 
      if (p3_dout_en !== 8'h80) tb_error("====== P3DIR  != 0x80 =====");
301 
 
302 
      @(r15==16'h3300);
303 
      if (p3_sel !== 8'h01) tb_error("====== P3SEL  != 0x01 =====");
304 
      @(r15==16'h3301);
305 
      if (p3_sel !== 8'h02) tb_error("====== P3SEL  != 0x02 =====");
306 
      @(r15==16'h3302);
307 
      if (p3_sel !== 8'h04) tb_error("====== P3SEL  != 0x04 =====");
308 
      @(r15==16'h3303);
309 
      if (p3_sel !== 8'h08) tb_error("====== P3SEL  != 0x08 =====");
310 
      @(r15==16'h3304);
311 
      if (p3_sel !== 8'h10) tb_error("====== P3SEL  != 0x10 =====");
312 
      @(r15==16'h3305);
313 
      if (p3_sel !== 8'h20) tb_error("====== P3SEL  != 0x20 =====");
314 
      @(r15==16'h3306);
315 
      if (p3_sel !== 8'h40) tb_error("====== P3SEL  != 0x40 =====");
316 
      @(r15==16'h3307);
317 
      if (p3_sel !== 8'h80) tb_error("====== P3SEL  != 0x80 =====");
318 
 
319 
 
320 
      // PORT 4: TEST I/O FUNCTIONALITY
321 
      //--------------------------------------------------------
322 
 
323 
      @(r15==16'h0230) p4_din = 8'h01;
324 
      @(r15==16'h0231) p4_din = 8'h02;
325 
      @(r15==16'h0232) p4_din = 8'h04;
326 
      @(r15==16'h0233) p4_din = 8'h08;
327 
      @(r15==16'h0234) p4_din = 8'h10;
328 
      @(r15==16'h0235) p4_din = 8'h20;
329 
      @(r15==16'h0236) p4_din = 8'h40;
330 
      @(r15==16'h0237) p4_din = 8'h80;
331 
      @(r15==16'h0238);
332 
      if (mem230 !== 16'h0201) tb_error("====== P4IN  != 0x0201 =====");
333 
      if (mem232 !== 16'h0804) tb_error("====== P4IN  != 0x0804 =====");
334 
      if (mem234 !== 16'h2010) tb_error("====== P4IN  != 0x2010 =====");
335 
      if (mem236 !== 16'h8040) tb_error("====== P4IN  != 0x8040 =====");
336 
 
337 
      @(r15==16'h4100);
338 
      if (p4_dout !== 8'h01) tb_error("====== P4DOUT  != 0x01 =====");
339 
      @(r15==16'h4101);
340 
      if (p4_dout !== 8'h02) tb_error("====== P4DOUT  != 0x02 =====");
341 
      @(r15==16'h4102);
342 
      if (p4_dout !== 8'h04) tb_error("====== P4DOUT  != 0x04 =====");
343 
      @(r15==16'h4103);
344 
      if (p4_dout !== 8'h08) tb_error("====== P4DOUT  != 0x08 =====");
345 
      @(r15==16'h4104);
346 
      if (p4_dout !== 8'h10) tb_error("====== P4DOUT  != 0x10 =====");
347 
      @(r15==16'h4105);
348 
      if (p4_dout !== 8'h20) tb_error("====== P4DOUT  != 0x20 =====");
349 
      @(r15==16'h4106);
350 
      if (p4_dout !== 8'h40) tb_error("====== P4DOUT  != 0x40 =====");
351 
      @(r15==16'h4107);
352 
      if (p4_dout !== 8'h80) tb_error("====== P4DOUT  != 0x80 =====");
353 
 
354 
      @(r15==16'h4200);
355 
      if (p4_dout_en !== 8'h01) tb_error("====== P4DIR  != 0x01 =====");
356 
      @(r15==16'h4201);
357 
      if (p4_dout_en !== 8'h02) tb_error("====== P4DIR  != 0x02 =====");
358 
      @(r15==16'h4202);
359 
      if (p4_dout_en !== 8'h04) tb_error("====== P4DIR  != 0x04 =====");
360 
      @(r15==16'h4203);
361 
      if (p4_dout_en !== 8'h08) tb_error("====== P4DIR  != 0x08 =====");
362 
      @(r15==16'h4204);
363 
      if (p4_dout_en !== 8'h10) tb_error("====== P4DIR  != 0x10 =====");
364 
      @(r15==16'h4205);
365 
      if (p4_dout_en !== 8'h20) tb_error("====== P4DIR  != 0x20 =====");
366 
      @(r15==16'h4206);
367 
      if (p4_dout_en !== 8'h40) tb_error("====== P4DIR  != 0x40 =====");
368 
      @(r15==16'h4207);
369 
      if (p4_dout_en !== 8'h80) tb_error("====== P4DIR  != 0x80 =====");
370 
 
371 
      @(r15==16'h4300);
372 
      if (p4_sel !== 8'h01) tb_error("====== P4SEL  != 0x01 =====");
373 
      @(r15==16'h4301);
374 
      if (p4_sel !== 8'h02) tb_error("====== P4SEL  != 0x02 =====");
375 
      @(r15==16'h4302);
376 
      if (p4_sel !== 8'h04) tb_error("====== P4SEL  != 0x04 =====");
377 
      @(r15==16'h4303);
378 
      if (p4_sel !== 8'h08) tb_error("====== P4SEL  != 0x08 =====");
379 
      @(r15==16'h4304);
380 
      if (p4_sel !== 8'h10) tb_error("====== P4SEL  != 0x10 =====");
381 
      @(r15==16'h4305);
382 
      if (p4_sel !== 8'h20) tb_error("====== P4SEL  != 0x20 =====");
383 
      @(r15==16'h4306);
384 
      if (p4_sel !== 8'h40) tb_error("====== P4SEL  != 0x40 =====");
385 
      @(r15==16'h4307);
386 
      if (p4_sel !== 8'h80) tb_error("====== P4SEL  != 0x80 =====");
387 
 
388 
 
389 
      // PORT 5: TEST I/O FUNCTIONALITY
390 
      //--------------------------------------------------------
391 
 
392 
      @(r15==16'h0240) p5_din = 8'h01;
393 
      @(r15==16'h0241) p5_din = 8'h02;
394 
      @(r15==16'h0242) p5_din = 8'h04;
395 
      @(r15==16'h0243) p5_din = 8'h08;
396 
      @(r15==16'h0244) p5_din = 8'h10;
397 
      @(r15==16'h0245) p5_din = 8'h20;
398 
      @(r15==16'h0246) p5_din = 8'h40;
399 
      @(r15==16'h0247) p5_din = 8'h80;
400 
      @(r15==16'h0248);
401 
      if (mem240 !== 16'h0201) tb_error("====== P5IN  != 0x0201 =====");
402 
      if (mem242 !== 16'h0804) tb_error("====== P5IN  != 0x0804 =====");
403 
      if (mem244 !== 16'h2010) tb_error("====== P5IN  != 0x2010 =====");
404 
      if (mem246 !== 16'h8040) tb_error("====== P5IN  != 0x8040 =====");
405 
 
406 
      @(r15==16'h5100);
407 
      if (p5_dout !== 8'h01) tb_error("====== P5DOUT  != 0x01 =====");
408 
      @(r15==16'h5101);
409 
      if (p5_dout !== 8'h02) tb_error("====== P5DOUT  != 0x02 =====");
410 
      @(r15==16'h5102);
411 
      if (p5_dout !== 8'h04) tb_error("====== P5DOUT  != 0x04 =====");
412 
      @(r15==16'h5103);
413 
      if (p5_dout !== 8'h08) tb_error("====== P5DOUT  != 0x08 =====");
414 
      @(r15==16'h5104);
415 
      if (p5_dout !== 8'h10) tb_error("====== P5DOUT  != 0x10 =====");
416 
      @(r15==16'h5105);
417 
      if (p5_dout !== 8'h20) tb_error("====== P5DOUT  != 0x20 =====");
418 
      @(r15==16'h5106);
419 
      if (p5_dout !== 8'h40) tb_error("====== P5DOUT  != 0x40 =====");
420 
      @(r15==16'h5107);
421 
      if (p5_dout !== 8'h80) tb_error("====== P5DOUT  != 0x80 =====");
422 
 
423 
      @(r15==16'h5200);
424 
      if (p5_dout_en !== 8'h01) tb_error("====== P5DIR  != 0x01 =====");
425 
      @(r15==16'h5201);
426 
      if (p5_dout_en !== 8'h02) tb_error("====== P5DIR  != 0x02 =====");
427 
      @(r15==16'h5202);
428 
      if (p5_dout_en !== 8'h04) tb_error("====== P5DIR  != 0x04 =====");
429 
      @(r15==16'h5203);
430 
      if (p5_dout_en !== 8'h08) tb_error("====== P5DIR  != 0x08 =====");
431 
      @(r15==16'h5204);
432 
      if (p5_dout_en !== 8'h10) tb_error("====== P5DIR  != 0x10 =====");
433 
      @(r15==16'h5205);
434 
      if (p5_dout_en !== 8'h20) tb_error("====== P5DIR  != 0x20 =====");
435 
      @(r15==16'h5206);
436 
      if (p5_dout_en !== 8'h40) tb_error("====== P5DIR  != 0x40 =====");
437 
      @(r15==16'h5207);
438 
      if (p5_dout_en !== 8'h80) tb_error("====== P5DIR  != 0x80 =====");
439 
 
440 
      @(r15==16'h5300);
441 
      if (p5_sel !== 8'h01) tb_error("====== P5SEL  != 0x01 =====");
442 
      @(r15==16'h5301);
443 
      if (p5_sel !== 8'h02) tb_error("====== P5SEL  != 0x02 =====");
444 
      @(r15==16'h5302);
445 
      if (p5_sel !== 8'h04) tb_error("====== P5SEL  != 0x04 =====");
446 
      @(r15==16'h5303);
447 
      if (p5_sel !== 8'h08) tb_error("====== P5SEL  != 0x08 =====");
448 
      @(r15==16'h5304);
449 
      if (p5_sel !== 8'h10) tb_error("====== P5SEL  != 0x10 =====");
450 
      @(r15==16'h5305);
451 
      if (p5_sel !== 8'h20) tb_error("====== P5SEL  != 0x20 =====");
452 
      @(r15==16'h5306);
453 
      if (p5_sel !== 8'h40) tb_error("====== P5SEL  != 0x40 =====");
454 
      @(r15==16'h5307);
455 
      if (p5_sel !== 8'h80) tb_error("====== P5SEL  != 0x80 =====");
456 
 
457 
 
458 
      // PORT 6: TEST I/O FUNCTIONALITY
459 
      //--------------------------------------------------------
460 
 
461 
      @(r15==16'h0250) p6_din = 8'h01;
462 
      @(r15==16'h0251) p6_din = 8'h02;
463 
      @(r15==16'h0252) p6_din = 8'h04;
464 
      @(r15==16'h0253) p6_din = 8'h08;
465 
      @(r15==16'h0254) p6_din = 8'h10;
466 
      @(r15==16'h0255) p6_din = 8'h20;
467 
      @(r15==16'h0256) p6_din = 8'h40;
468 
      @(r15==16'h0257) p6_din = 8'h80;
469 
      @(r15==16'h0258);
470 
      if (mem250 !== 16'h0201) tb_error("====== P6IN  != 0x0201 =====");
471 
      if (mem252 !== 16'h0804) tb_error("====== P6IN  != 0x0804 =====");
472 
      if (mem254 !== 16'h2010) tb_error("====== P6IN  != 0x2010 =====");
473 
      if (mem256 !== 16'h8040) tb_error("====== P6IN  != 0x8040 =====");
474 
 
475 
      @(r15==16'h6100);
476 
      if (p6_dout !== 8'h01) tb_error("====== P6DOUT  != 0x01 =====");
477 
      @(r15==16'h6101);
478 
      if (p6_dout !== 8'h02) tb_error("====== P6DOUT  != 0x02 =====");
479 
      @(r15==16'h6102);
480 
      if (p6_dout !== 8'h04) tb_error("====== P6DOUT  != 0x04 =====");
481 
      @(r15==16'h6103);
482 
      if (p6_dout !== 8'h08) tb_error("====== P6DOUT  != 0x08 =====");
483 
      @(r15==16'h6104);
484 
      if (p6_dout !== 8'h10) tb_error("====== P6DOUT  != 0x10 =====");
485 
      @(r15==16'h6105);
486 
      if (p6_dout !== 8'h20) tb_error("====== P6DOUT  != 0x20 =====");
487 
      @(r15==16'h6106);
488 
      if (p6_dout !== 8'h40) tb_error("====== P6DOUT  != 0x40 =====");
489 
      @(r15==16'h6107);
490 
      if (p6_dout !== 8'h80) tb_error("====== P6DOUT  != 0x80 =====");
491 
 
492 
      @(r15==16'h6200);
493 
      if (p6_dout_en !== 8'h01) tb_error("====== P6DIR  != 0x01 =====");
494 
      @(r15==16'h6201);
495 
      if (p6_dout_en !== 8'h02) tb_error("====== P6DIR  != 0x02 =====");
496 
      @(r15==16'h6202);
497 
      if (p6_dout_en !== 8'h04) tb_error("====== P6DIR  != 0x04 =====");
498 
      @(r15==16'h6203);
499 
      if (p6_dout_en !== 8'h08) tb_error("====== P6DIR  != 0x08 =====");
500 
      @(r15==16'h6204);
501 
      if (p6_dout_en !== 8'h10) tb_error("====== P6DIR  != 0x10 =====");
502 
      @(r15==16'h6205);
503 
      if (p6_dout_en !== 8'h20) tb_error("====== P6DIR  != 0x20 =====");
504 
      @(r15==16'h6206);
505 
      if (p6_dout_en !== 8'h40) tb_error("====== P6DIR  != 0x40 =====");
506 
      @(r15==16'h6207);
507 
      if (p6_dout_en !== 8'h80) tb_error("====== P6DIR  != 0x80 =====");
508 
 
509 
      @(r15==16'h6300);
510 
      if (p6_sel !== 8'h01) tb_error("====== P6SEL  != 0x01 =====");
511 
      @(r15==16'h6301);
512 
      if (p6_sel !== 8'h02) tb_error("====== P6SEL  != 0x02 =====");
513 
      @(r15==16'h6302);
514 
      if (p6_sel !== 8'h04) tb_error("====== P6SEL  != 0x04 =====");
515 
      @(r15==16'h6303);
516 
      if (p6_sel !== 8'h08) tb_error("====== P6SEL  != 0x08 =====");
517 
      @(r15==16'h6304);
518 
      if (p6_sel !== 8'h10) tb_error("====== P6SEL  != 0x10 =====");
519 
      @(r15==16'h6305);
520 
      if (p6_sel !== 8'h20) tb_error("====== P6SEL  != 0x20 =====");
521 
      @(r15==16'h6306);
522 
      if (p6_sel !== 8'h40) tb_error("====== P6SEL  != 0x40 =====");
523 
      @(r15==16'h6307);
524 
      if (p6_sel !== 8'h80) tb_error("====== P6SEL  != 0x80 =====");
525 
 
526 
 
527 
      stimulus_done = 1;
528 
   end
529 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.