OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_basic.v] - Blame information for rev 202

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 67 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                          HARDWARE MULTIPLIER                              */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the hardware multiplier:                                             */
27 
/*                                - MPY  mode.                               */
28 
/*                                - MPYS mode.                               */
29 
/*                                - MAC  mode.                               */
30 
/*                                - MACS mode.                               */
31 
/*                                                                           */
32 
/* Author(s):                                                                */
33 
/*             - Olivier Girard,    olgirard@gmail.com                       */
34 
/*                                                                           */
35 
/*---------------------------------------------------------------------------*/
36 
/* $Rev: 18 $                                                                */
37 
/* $LastChangedBy: olivier.girard $                                          */
38 
/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $          */
39 
/*===========================================================================*/
40 
 
41 202 olivier.gi 
 
42 67 olivier.gi 
initial
43 
   begin
44 
      $display(" ===============================================");
45 
      $display("|                 START SIMULATION              |");
46 
      $display(" ===============================================");
47 111 olivier.gi 
`ifdef MULTIPLIER
48 67 olivier.gi 
      repeat(5) @(posedge mclk);
49 
      stimulus_done = 0;
50 
 
51 
 
52 
      // UNSIGNED MULTIPLICATION
53 
      //--------------------------------------------------------
54 
 
55 
      @(r15===16'h0001);
56 
      if (r10 !== 16'h7F14) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (1) =====");
57 
      if (r11 !== 16'h007B) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (1) =====");
58 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (1) =====");
59 
 
60 
      @(r15===16'h0002);
61 
      if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (2) =====");
62 
      if (r11 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (2) =====");
63 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (2) =====");
64 
 
65 
      @(r15===16'h0003);
66 
      if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (3) =====");
67 
      if (r11 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (3) =====");
68 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (3) =====");
69 
 
70 
      @(r15===16'h0004);
71 
      if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (4) =====");
72 
      if (r11 !== 16'h3FFF) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (4) =====");
73 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (4) =====");
74 
 
75 
      @(r15===16'h0005);
76 
      if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (5) =====");
77 
      if (r11 !== 16'hFFFE) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (5) =====");
78 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (5) =====");
79 
 
80 
      @(r15===16'h0006);
81 
      if (r10 !== 16'h8001) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (6) =====");
82 
      if (r11 !== 16'h7FFE) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (6) =====");
83 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (6) =====");
84 
 
85 
      @(r15===16'h0007);
86 
      if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (7) =====");
87 
      if (r11 !== 16'h3FFF) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (7) =====");
88 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (7) =====");
89 
 
90 
      @(r15===16'h0008);
91 
      if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (8) =====");
92 
      if (r11 !== 16'h7FFF) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (8) =====");
93 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (8) =====");
94 
 
95 
      @(r15===16'h0009);
96 
      if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: RESLO  (9) =====");
97 
      if (r11 !== 16'h4000) tb_error("====== UNSIGNED MULTIPLICATION: RESHI  (9) =====");
98 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLICATION: SUMEXT (9) =====");
99 
 
100 
      $display("Unsigned Multiplication test completed (MPY mode).");
101 
 
102 
      // SIGNED MULTIPLICATION
103 
      //--------------------------------------------------------
104 
 
105 
      @(r15===16'h0001);
106 
      if (r10 !== 16'h7F14) tb_error("====== SIGNED MULTIPLICATION: RESLO  (1) =====");
107 
      if (r11 !== 16'hE7F9) tb_error("====== SIGNED MULTIPLICATION: RESHI  (1) =====");
108 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (1) =====");
109 
 
110 
      @(r15===16'h0002);
111 
      if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESLO  (2) =====");
112 
      if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI  (2) =====");
113 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (2) =====");
114 
 
115 
      @(r15===16'h0003);
116 
      if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLICATION: RESLO  (3) =====");
117 
      if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI  (3) =====");
118 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (3) =====");
119 
 
120 
      @(r15===16'h0004);
121 
      if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLICATION: RESLO  (4) =====");
122 
      if (r11 !== 16'h3FFF) tb_error("====== SIGNED MULTIPLICATION: RESHI  (4) =====");
123 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (4) =====");
124 
 
125 
      @(r15===16'h0005);
126 
      if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLICATION: RESLO  (5) =====");
127 
      if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI  (5) =====");
128 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (5) =====");
129 
 
130 
      @(r15===16'h0006);
131 
      if (r10 !== 16'h8001) tb_error("====== SIGNED MULTIPLICATION: RESLO  (6) =====");
132 
      if (r11 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: RESHI  (6) =====");
133 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (6) =====");
134 
 
135 
      @(r15===16'h0007);
136 
      if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLICATION: RESLO  (7) =====");
137 
      if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLICATION: RESHI  (7) =====");
138 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (7) =====");
139 
 
140 
      @(r15===16'h0008);
141 
      if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLICATION: RESLO  (8) =====");
142 
      if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESHI  (8) =====");
143 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (8) =====");
144 
 
145 
      @(r15===16'h0009);
146 
      if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: RESLO  (9) =====");
147 
      if (r11 !== 16'h4000) tb_error("====== SIGNED MULTIPLICATION: RESHI  (9) =====");
148 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLICATION: SUMEXT (9) =====");
149 
 
150 
      $display("Signed Multiplication test completed (MPYS mode)");
151 
 
152 202 olivier.gi 
 
153 67 olivier.gi 
      // UNSIGNED MULTIPLY ACCUMULATE
154 
      //--------------------------------------------------------
155 
 
156 
      @(r15===16'h0001);
157 
      if (r10 !== 16'h7F14) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (1) =====");
158 
      if (r11 !== 16'hC07B) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (1) =====");
159 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (1) =====");
160 
 
161 
      @(r15===16'h0002);
162 
      if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (2) =====");
163 
      if (r11 !== 16'hC000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (2) =====");
164 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (2) =====");
165 
 
166 
      @(r15===16'h0003);
167 
      if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (3) =====");
168 
      if (r11 !== 16'hC000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (3) =====");
169 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (3) =====");
170 
 
171 
      @(r15===16'h0004);
172 
      if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (4) =====");
173 
      if (r11 !== 16'hFFFF) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (4) =====");
174 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (4) =====");
175 
 
176 
      @(r15===16'h0005);
177 
      if (r10 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (5) =====");
178 
      if (r11 !== 16'hBFFE) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (5) =====");
179 
      if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (5) =====");
180 
 
181 
      @(r15===16'h0006);
182 
      if (r10 !== 16'h8001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (6) =====");
183 
      if (r11 !== 16'h3FFE) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (6) =====");
184 
      if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (6) =====");
185 
 
186 
      @(r15===16'h0007);
187 
      if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (7) =====");
188 
      if (r11 !== 16'hFFFF) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (7) =====");
189 
      if (r12 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (7) =====");
190 
 
191 
      @(r15===16'h0008);
192 
      if (r10 !== 16'h8000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (8) =====");
193 
      if (r11 !== 16'h3FFF) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (8) =====");
194 
      if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (8) =====");
195 
 
196 
      @(r15===16'h0009);
197 
      if (r10 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESLO  (9) =====");
198 
      if (r11 !== 16'h0000) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: RESHI  (9) =====");
199 
      if (r12 !== 16'h0001) tb_error("====== UNSIGNED MULTIPLY ACCUMULATE: SUMEXT (9) =====");
200 
 
201 
      $display("Unsigned Multiply Accumulate test completed (MAC mode)");
202 
 
203 
 
204 
      // SIGNED MULTIPLY ACCUMULATE
205 
      //--------------------------------------------------------
206 
 
207 
      @(r15===16'h0001);
208 
      if (r10 !== 16'h7F14) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (1) =====");
209 
      if (r11 !== 16'hA7F9) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (1) =====");
210 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (1) =====");
211 
 
212 
      @(r15===16'h0002);
213 
      if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (2) =====");
214 
      if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (2) =====");
215 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (2) =====");
216 
 
217 
      @(r15===16'h0003);
218 
      if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (3) =====");
219 
      if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (3) =====");
220 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (3) =====");
221 
 
222 
      @(r15===16'h0004);
223 
      if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (4) =====");
224 
      if (r11 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (4) =====");
225 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (4) =====");
226 
 
227 
      @(r15===16'h0005);
228 
      if (r10 !== 16'h0001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (5) =====");
229 
      if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (5) =====");
230 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (5) =====");
231 
 
232 
      @(r15===16'h0006);
233 
      if (r10 !== 16'h8001) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (6) =====");
234 
      if (r11 !== 16'hBFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (6) =====");
235 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (6) =====");
236 
 
237 
      @(r15===16'h0007);
238 
      if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (7) =====");
239 
      if (r11 !== 16'h8000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (7) =====");
240 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (7) =====");
241 
 
242 
      @(r15===16'h0008);
243 
      if (r10 !== 16'h8000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (8) =====");
244 
      if (r11 !== 16'hC000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (8) =====");
245 
      if (r12 !== 16'hFFFF) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (8) =====");
246 
 
247 
      @(r15===16'h0009);
248 
      if (r10 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESLO  (9) =====");
249 
      if (r11 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: RESHI  (9) =====");
250 
      if (r12 !== 16'h0000) tb_error("====== SIGNED MULTIPLY ACCUMULATE: SUMEXT (9) =====");
251 
 
252 
      $display("Signed Multiply Accumulate test completed (MACS mode)");
253 
 
254 
 
255 186 olivier.gi 
      // 16-BIT RD/WR ACCESS OPERANDS
256 111 olivier.gi 
      //--------------------------------------------------------
257 
 
258 
      @(r15===16'h0001);
259 186 olivier.gi 
      if (r10 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY  (1) =====");
260 
      if (r11 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
261 
      if (r12 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC  (1) =====");
262 
      if (r13 !== 16'h1234) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
263 
      if (r14 !== 16'h5678) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2      (1) =====");
264 111 olivier.gi 
 
265 
      @(r15===16'h0002);
266 186 olivier.gi 
      if (r10 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY  (2) =====");
267 
      if (r11 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
268 
      if (r12 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC  (2) =====");
269 
      if (r13 !== 16'h4321) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
270 
      if (r14 !== 16'h8765) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2      (2) =====");
271 111 olivier.gi 
 
272 
      @(r15===16'h0003);
273 186 olivier.gi 
      if (r10 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY  (3) =====");
274 
      if (r11 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (3) =====");
275 
      if (r12 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC  (3) =====");
276 
      if (r13 !== 16'h9ABC) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (3) =====");
277 
      if (r14 !== 16'hDEF0) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2      (3) =====");
278 111 olivier.gi 
 
279 
      @(r15===16'h0004);
280 186 olivier.gi 
      if (r10 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPY  (4) =====");
281 
      if (r11 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (4) =====");
282 
      if (r12 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MAC  (4) =====");
283 
      if (r13 !== 16'hCBA9) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP1_MACS (4) =====");
284 
      if (r14 !== 16'h0FED) tb_error("====== 16-BIT RD/WR ACCESS OPERANDS: OP2      (4) =====");
285 111 olivier.gi 
 
286 186 olivier.gi 
      $display("16-BIT RD/WR Access operands test completed");
287 111 olivier.gi 
 
288 202 olivier.gi 
 
289 186 olivier.gi 
      // 8-BIT RD/WR ACCESS OPERANDS
290 
      //--------------------------------------------------------
291 
 
292 
      @(r15===16'h0001);
293 
      if (r10 !== 16'h1234) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY  (1) =====");
294 
      if (r11 !== 16'h00ab) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPY  (2) =====");
295 
 
296 
      @(r15===16'h0002);
297 
      if (r10 !== 16'h5678) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (1) =====");
298 
      if (r11 !== 16'h00bc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MPYS (2) =====");
299 
 
300 
      @(r15===16'h0003);
301 
      if (r10 !== 16'h9abc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC  (1) =====");
302 
      if (r11 !== 16'h00de) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MAC  (2) =====");
303 
 
304 
      @(r15===16'h0004);
305 
      if (r10 !== 16'hdef0) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (1) =====");
306 
      if (r11 !== 16'h00ed) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP1_MACS (2) =====");
307 
 
308 
      @(r15===16'h0005);
309 
      if (r10 !== 16'h4321) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2      (1) =====");
310 
      if (r11 !== 16'h00dc) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: OP2      (2) =====");
311 
 
312 
      @(r15===16'h0006);
313 
      if (r10 !== 16'h8765) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO    (1) =====");
314 
      if (r11 !== 16'h00cb) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESLO    (2) =====");
315 
 
316 
      @(r15===16'h0007);
317 
      if (r10 !== 16'hcba9) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI    (1) =====");
318 
      if (r11 !== 16'h00ba) tb_error("====== 8-BIT RD/WR ACCESS OPERANDS: RESHI    (2) =====");
319 
 
320 
 
321 
      $display("8-BIT RD/WR Access operands test completed");
322 
 
323 
 
324 67 olivier.gi 
      stimulus_done = 1;
325 111 olivier.gi 
`else
326 
 
327 202 olivier.gi 
       tb_skip_finish("|      (hardware multiplier not included)       |");
328 111 olivier.gi 
`endif
329 67 olivier.gi 
   end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.