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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [mpy_mpys.s43] - Blame information for rev 219

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Line No. Rev Author Line
1 67 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                          HARDWARE MULTIPLIER                              */
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/*---------------------------------------------------------------------------*/
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/* Test the hardware multiplier:                                             */
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/*                                - MPYS  mode.                              */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 18 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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38 141 olivier.gi
.include "pmem_defs.asm"
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40 67 olivier.gi
.global main
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main:
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        /* --------------   SIGNED MULTIPLICATION   --------------- */
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        ;; Disable watchdog
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        mov #0x5A80, &WDTCTL
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        ;; Initialize variables
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        mov #0x0000, R15
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        mov #0x0000, R8
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        mov #0x0000, R9
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mpy_loop:
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        ;; Initialize RESLO and RESHI to make sure it is overwritten
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        mov #0x0000, &RESLO
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        mov #0xC000, &RESHI
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        ;; Perform unsigned R8*R9
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        mov R8, &MPYS
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        mov R9, &OP2
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        ;; Read result
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        mov &RESLO,  R10
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        mov &RESHI,  R11
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        mov &SUMEXT, R12
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        ;; Notify verilog checker
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        add #1, R15
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        ;; Update next OP1 (R8)
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        cmp #0xF0F0, R8
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        jeq op2_update
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        mov #0x00FF, R7
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        and R8, R7
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        cmp #0x00F0, R7
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        jeq op1_hi_update
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        add #0x0010, R8
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        jmp mpy_loop
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  op1_hi_update:
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        and #0xff00, R8
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        add #0x1000, R8
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        jmp mpy_loop
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        ;; Update next OP2 (R9)
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  op2_update:
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        cmp #0xF0F0, R9
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        jeq end_of_test
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        mov #0x0000, R8
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        mov #0x00FF, R7
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        and R9, R7
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        cmp #0x00F0, R7
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        jeq op2_hi_update
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        add #0x0010, R9
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        jmp mpy_loop
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  op2_hi_update:
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        and #0xff00, R9
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        add #0x1000, R9
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        jmp mpy_loop
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test  ; Interrupt  0 (lowest priority)    
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.word end_of_test  ; Interrupt  1                      
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.word end_of_test  ; Interrupt  2                      
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.word end_of_test  ; Interrupt  3                      
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.word end_of_test  ; Interrupt  4                      
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.word end_of_test  ; Interrupt  5                      
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.word end_of_test  ; Interrupt  6                      
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.word end_of_test  ; Interrupt  7                      
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.word end_of_test  ; Interrupt  8                      
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.word end_of_test  ; Interrupt  9                      
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.word end_of_test  ; Interrupt 10                      Watchdog timer
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.word end_of_test  ; Interrupt 11                      
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.word end_of_test  ; Interrupt 12                      
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.word end_of_test  ; Interrupt 13                      
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.word end_of_test  ; Interrupt 14                      NMI
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.word main         ; Interrupt 15 (highest priority)   RESET

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