OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [nmi.s43] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 SINGLE-OPERAND ARITHMETIC: CALL  INSTRUCTION              */
25
/*---------------------------------------------------------------------------*/
26
/* Test the CALL  instruction.                                               */
27
/*                                                                           */
28
/* Author(s):                                                                */
29
/*             - Olivier Girard,    olgirard@gmail.com                       */
30
/*                                                                           */
31
/*---------------------------------------------------------------------------*/
32
/* $Rev: 19 $                                                                */
33
/* $LastChangedBy: olivier.girard $                                          */
34
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
35
/*===========================================================================*/
36
 
37 141 olivier.gi
.include "pmem_defs.asm"
38 134 olivier.gi
 
39
.global main
40
 
41
.macro LPM4
42
 bis    #0x00F0, r2
43
.endm
44
.macro LPM4_exit
45
 bic    #0x00F0, @r1
46
.endm
47
 
48
 
49
main:
50
        mov   #DMEM_250, r1   ;# Initialize stack & Enable interrupts
51
        eint
52
 
53
        mov     #0x0000, r6   ;# R6 will be incremented with every NMI serviced interrupts
54
        mov     #0x0000, r7   ;# Save Status register in NMI service routine
55
        mov     #0x0000, r8   ;# Save Stack register in NMI service routine
56
 
57
        ;# Test NMI disabled
58
        ;#-----------------------
59
        mov     #0x1000, r15
60
 
61
        mov.b   &IFG1,   r14 	;# Check reset value
62
        mov     #0x1001, r15
63
 
64
        LPM4
65
 
66
        mov     #0x0100, r9     ;# Wait a while while .v stimulus plays with NMI pin
67
   wait_loop_nmi_dis:
68
        dec     r9
69
        jnz     wait_loop_nmi_dis
70
 
71
        mov.b   &IFG1,   r13    ;# Check the flag
72
        bic.b   #0x10,   &IFG1
73
        mov.b   &IFG1,   r12
74
        nop
75
        nop
76
        nop
77
        nop
78
        mov.b   &IFG1,   r11    ;# Wait a while and re-check the flag
79
 
80
        mov     #0x1002, r15
81
 
82
 
83
        ;# Test NMI rising edge
84
        ;#-----------------------
85
        mov     #0x2000, r15
86
 
87
        mov     #0x5a00, &WDTCTL  ; NMI Edge selection: rising
88
        bic.b   #0x10,   &IFG1    ; Clear NMI flag
89
        bis.b   #0x10,   &IE1     ; Enable NMI
90
 
91
        mov     #0x2001, r15
92
 
93
        LPM4
94
 
95
        mov     #0x0100, r9     ;# Wait a while
96
   wait_loop_nmi_re:
97
        dec     r9
98
        jnz     wait_loop_nmi_re
99
 
100
 
101
        ;# Test NMI falling edge
102
        ;#-----------------------
103
        mov     #0x3000, r15
104
 
105
        bic.b   #0x10,   &IE1     ; Disable NMI
106
        mov     #0x5a40, &WDTCTL  ; NMI Edge selection: falling
107
        bic.b   #0x10,   &IFG1    ; Clear NMI flag
108
        bis.b   #0x10,   &IE1     ; Enable NMI
109
        mov     #0x0000, r6
110
 
111
        mov     #0x3001, r15
112
 
113
        LPM4
114
 
115
        mov     #0x0100, r9     ;# Wait a while
116
   wait_loop_nmi_fe:
117
        dec     r9
118
        jnz     wait_loop_nmi_fe
119
 
120
 
121
        ;# Test NMI nested in maskable IRQ
122
        ;#---------------------------------
123
        mov     #0x4000, r15
124
 
125
        bic.b   #0x10,   &IE1     ; Disable NMI
126
        mov     #0x5a00, &WDTCTL  ; NMI Edge selection: rising
127
        bic.b   #0x10,   &IFG1    ; Clear NMI flag
128
        bis.b   #0x10,   &IE1     ; Enable NMI
129
        mov     #0x0000, r6
130
 
131
        mov     #0x4001, r15
132
 
133
        LPM4
134
 
135
        mov     #0x0100, r9     ;# Wait a while
136
   wait_loop_nmi_nested:
137
        dec     r9
138
        jnz     wait_loop_nmi_nested
139
 
140
        mov     #0x4002, r15
141
 
142
        /* ----------------------    END OF TEST   --------------- */
143
end_of_test:
144
        nop
145
        br #0xffff
146
 
147
 
148
 
149
        /* ----------------------    FUNCTIONS    --------------- */
150
 
151
IRQ00_ROUTINE:
152
        mov #0x5678, r10
153
        add      r6, r10    ; If NMI was taken before, 1 will be added to R10
154
        LPM4_exit
155
        reti
156
 
157
NMI_ROUTINE:
158
        mov #0x1234, r10
159
        inc          r6     ; Increment R6
160
        cmp      #2, r6
161
        jl   end_of_nmi
162
        LPM4_exit
163
    end_of_nmi:
164
        mov       r2, r7    ; Save Status register
165
        mov       r1, r8    ; Save Stack register
166
        bic.b  #0x10, &IFG1 ; Clear NMI flag
167
        bis.b  #0x10, &IE1  ; Enable NMI
168
        reti
169
 
170
 
171
        /* ----------------------         INTERRUPT VECTORS  --------------- */
172
 
173
.section .vectors, "a"
174
.word IRQ00_ROUTINE     ; Interrupt  0 (lowest priority)    
175
.word end_of_test       ; Interrupt  1                      
176
.word end_of_test       ; Interrupt  2                      
177
.word end_of_test       ; Interrupt  3                      
178
.word end_of_test       ; Interrupt  4                      
179
.word end_of_test       ; Interrupt  5                      
180
.word end_of_test       ; Interrupt  6                      
181
.word end_of_test       ; Interrupt  7                      
182
.word end_of_test       ; Interrupt  8                      
183
.word end_of_test       ; Interrupt  9                      
184
.word end_of_test       ; Interrupt 10                      Watchdog timer
185
.word end_of_test       ; Interrupt 11                      
186
.word end_of_test       ; Interrupt 12                      
187
.word end_of_test       ; Interrupt 13                      
188
.word NMI_ROUTINE       ; Interrupt 14                      NMI
189
.word main              ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.