OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.v] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 202 olivier.gi 
/*                  CPU OPERATING MODES (FPGA VERSION)                       */
25 2 olivier.gi 
/*---------------------------------------------------------------------------*/
26 
/* Test the CPU Operating modes:                                             */
27 
/*                                 - CPUOFF (<=> R2[4]): turn off CPU.       */
28 
/*                                 - OSCOFF (<=> R2[5]): turn off LFXT_CLK.  */
29 
/*                                 - SCG1   (<=> R2[7]): turn off SMCLK.     */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 202 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 
integer smclk_cnt;
41 
always @(negedge mclk)
42 
  if (smclk_en) smclk_cnt <= smclk_cnt+1;
43 
 
44 
integer aclk_cnt;
45 
always @(negedge mclk)
46 
  if (aclk_en) aclk_cnt <= aclk_cnt+1;
47 
 
48 
integer inst_cnt;
49 
always @(inst_number)
50 
  inst_cnt = inst_cnt+1;
51 
 
52 
initial
53 
   begin
54 
      $display(" ===============================================");
55 
      $display("|                 START SIMULATION              |");
56 
      $display(" ===============================================");
57 
      repeat(5) @(posedge mclk);
58 
      stimulus_done = 0;
59 
 
60 180 olivier.gi 
`ifdef ASIC_CLOCKING
61 202 olivier.gi 
      tb_skip_finish("|   (this test is not supported in ASIC mode)   |");
62 134 olivier.gi 
`else
63 2 olivier.gi 
 
64 
      // SCG1   (<=> R2[7]): turn off SMCLK
65 
      //--------------------------------------------------------
66 
 
67 
      @(r15==16'h1001);
68 
      smclk_cnt = 0;
69 
      repeat (84) @(posedge mclk);
70 
      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 1: SMCLK IS NOT RUNNING =====");
71 
 
72 
      @(r15==16'h1002);
73 
      smclk_cnt = 0;
74 
      repeat (84) @(posedge mclk);
75 
      if (smclk_cnt !== 16'h0000) tb_error("====== SCG1 TEST 2: SMCLK IS NOT STOPPED =====");
76 
 
77 
      @(r15==16'h1003);
78 
      p1_din[0] = 1'b1;
79 
      repeat (2) @(posedge mclk);
80 
      p1_din[0] = 1'b0;
81 
      smclk_cnt = 0;
82 
      repeat (84) @(posedge mclk);
83 
      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 3: SMCLK IS NOT RUNNING DURING IRQ =====");
84 
 
85 
      @(r15==16'h1004);
86 
      smclk_cnt = 0;
87 
      repeat (84) @(posedge mclk);
88 
      if (smclk_cnt !== 16'h0000) tb_error("====== SCG1 TEST 4: SMCLK IS NOT STOPPED =====");
89 202 olivier.gi 
 
90 2 olivier.gi 
      @(r15==16'h1005);
91 
      smclk_cnt = 0;
92 
      repeat (80) @(posedge mclk);
93 
      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 5: SMCLK IS NOT RUNNING =====");
94 
 
95 202 olivier.gi 
 
96 2 olivier.gi 
      // OSCOFF  (<=> R2[5]): turn off LFXT1CLK
97 
      //--------------------------------------------------------
98 
 
99 
      @(r15==16'h2001);
100 
      aclk_cnt  = 0;
101 
      smclk_cnt = 0;
102 
      repeat (104) @(posedge mclk);
103 
      if (aclk_cnt  !== 16'h0004) tb_error("====== OSCOFF TEST 1: ACLK  IS NOT RUNNING =====");
104 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 1: SMCLK IS NOT RUNNING ON MCLK =====");
105 
 
106 
      @(r15==16'h2002);
107 
      aclk_cnt  = 0;
108 
      smclk_cnt = 0;
109 
      repeat (104) @(posedge mclk);
110 
      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 2: ACLK  IS NOT STOPPED =====");
111 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 2: SMCLK IS NOT RUNNING ON MCLK =====");
112 
 
113 
      @(r15==16'h2003);
114 
      p1_din[0] = 1'b1;
115 
      repeat (2) @(posedge mclk);
116 
      p1_din[0] = 1'b0;
117 
      aclk_cnt  = 0;
118 
      smclk_cnt = 0;
119 
      repeat (104) @(posedge mclk);
120 
      if (aclk_cnt  !== 16'h0003) tb_error("====== OSCOFF TEST 3: ACLK  IS NOT RUNNING DURING IRQ =====");
121 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 3: SMCLK IS NOT RUNNING ON MCLK =====");
122 
 
123 
       @(r15==16'h2004);
124 
      aclk_cnt  = 0;
125 
      smclk_cnt = 0;
126 
      repeat (104) @(posedge mclk);
127 
      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 4: ACLK  IS NOT STOPPED =====");
128 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 4: SMCLK IS NOT RUNNING ON MCLK =====");
129 
 
130 
      @(r15==16'h2005);
131 
      aclk_cnt  = 0;
132 
      smclk_cnt = 0;
133 
      repeat (104) @(posedge mclk);
134 202 olivier.gi 
      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 5: ACLK  IS NOT STOPPED =====");
135 
      if (smclk_cnt !== 16'h0000) tb_error("====== OSCOFF TEST 5: SMCLK IS NOT STOPPED =====");
136 2 olivier.gi 
 
137 
      @(r15==16'h2006);
138 
      aclk_cnt  = 0;
139 
      smclk_cnt = 0;
140 
      repeat (104) @(posedge mclk);
141 
      if (aclk_cnt  !== 16'h0003) tb_error("====== OSCOFF TEST 6: ACLK  IS NOT RUNNING =====");
142 
      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 6: SMCLK IS NOT RUNNING ON MCLK =====");
143 
 
144 202 olivier.gi 
 
145 2 olivier.gi 
      // CPUOFF  (<=> R2[4]): turn off CPU
146 
      //--------------------------------------------------------
147 
 
148 
      @(r15==16'h3001);
149 
      @(negedge mclk);
150 
      inst_cnt  = 0;
151 
      repeat (80) @(negedge mclk);
152 95 olivier.gi 
      if (inst_cnt  <= 16'h0030) tb_error("====== CPUOFF TEST 1: CPU IS NOT RUNNING =====");
153 2 olivier.gi 
 
154 
      @(r15==16'h3002);
155 
      repeat (3) @(negedge mclk);
156 
      inst_cnt  = 0;
157 
      repeat (80) @(negedge mclk);
158 
      if (inst_cnt  !== 16'h0000) tb_error("====== CPUOFF TEST 2: CPU IS NOT STOPPED =====");
159 
 
160 
      @(posedge mclk);
161 
      p1_din[0] = 1'b1;
162 
      repeat (2) @(posedge mclk);
163 
      p1_din[0] = 1'b0;
164 
      @(negedge mclk);
165 
      inst_cnt  = 0;
166 
      repeat (80) @(negedge mclk);
167 95 olivier.gi 
      if (inst_cnt <= 16'h0025) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
168 202 olivier.gi 
 
169 111 olivier.gi 
      @(r1==(`PER_SIZE+16'h0050));
170 2 olivier.gi 
      repeat (3) @(negedge mclk);
171 
      inst_cnt  = 0;
172 
      repeat (80) @(negedge mclk);
173 
      if (inst_cnt  !== 16'h0000) tb_error("====== CPUOFF TEST 4: CPU IS NOT STOPPED AFTER IRQ =====");
174 
 
175 
      @(posedge mclk);
176 
      p2_din[0] = 1'b1;
177 
      repeat (2) @(posedge mclk);
178 
      p2_din[0] = 1'b0;
179 
      @(negedge mclk);
180 
      inst_cnt  = 0;
181 
      repeat (80) @(negedge mclk);
182 95 olivier.gi 
      if (inst_cnt <= 16'h0025) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
183 2 olivier.gi 
 
184 
      @(r15==16'h3003);
185 
      @(negedge mclk);
186 
      inst_cnt  = 0;
187 
      repeat (80) @(negedge mclk);
188 95 olivier.gi 
      if (inst_cnt  <= 16'h0030) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING =====");
189 2 olivier.gi 
 
190 202 olivier.gi 
      // DMA_SCG1
191 
      //--------------------------------------------------------
192 
   `ifdef DMA_IF_EN
193 
      @(r15==16'h4001);
194 
      dma_en    = 1'b1;
195 
      aclk_cnt  = 0;
196 
      smclk_cnt = 0;
197 
      repeat (104) @(posedge mclk);
198 
      dma_en    = 1'b0;
199 
      if (aclk_cnt  !== 16'h0004) tb_error("====== DMA_SCG1 TEST 1: ACLK  IS NOT RUNNING =====");
200 
      if (smclk_cnt !== 16'h0000) tb_error("====== DMA_SCG1 TEST 1: SMCLK IS RUNNING =====");
201 134 olivier.gi 
 
202 202 olivier.gi 
      @(r15==16'h4002);
203 
      dma_en    = 1'b1;
204 
      aclk_cnt  = 0;
205 
      smclk_cnt = 0;
206 
      repeat (104) @(posedge mclk);
207 
      dma_en    = 1'b0;
208 
      if (aclk_cnt  !== 16'h0003) tb_error("====== DMA_SCG1 TEST 2: ACLK  IS NOT RUNNING =====");
209 
      if (smclk_cnt !== 16'h0000) tb_error("====== DMA_SCG1 TEST 2: SMCLK IS RUNNING =====");
210 
 
211 
      @(r15==16'h4003);
212 
      dma_en    = 1'b1;
213 
      aclk_cnt  = 0;
214 
      smclk_cnt = 0;
215 
      repeat (104) @(posedge mclk);
216 
      dma_en    = 1'b0;
217 
      if (aclk_cnt  !== 16'h0003) tb_error("====== DMA_SCG1 TEST 3: ACLK  IS NOT RUNNING =====");
218 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_SCG1 TEST 3: SMCLK IS NOT RUNNING =====");
219 
 
220 
      @(r15==16'h4004);
221 
      dma_en    = 1'b1;
222 
      aclk_cnt  = 0;
223 
      smclk_cnt = 0;
224 
      repeat (104) @(posedge mclk);
225 
      dma_en    = 1'b0;
226 
      if (aclk_cnt  !== 16'h0004) tb_error("====== DMA_SCG1 TEST 4: ACLK  IS NOT RUNNING =====");
227 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_SCG1 TEST 4: SMCLK IS NOT RUNNING =====");
228 
 
229 
      @(r15==16'h4005);
230 
      dma_en    = 1'b1;
231 
      aclk_cnt  = 0;
232 
      smclk_cnt = 0;
233 
      repeat (104) @(posedge mclk);
234 
      dma_en    = 1'b0;
235 
      if (aclk_cnt  !== 16'h0003) tb_error("====== DMA_SCG1 TEST 5: ACLK  IS NOT RUNNING =====");
236 
      if (smclk_cnt !== 16'h0000) tb_error("====== DMA_SCG1 TEST 5: SMCLK IS RUNNING =====");
237 
 
238 
      @(r15==16'h4006);
239 
      dma_en    = 1'b1;
240 
      aclk_cnt  = 0;
241 
      smclk_cnt = 0;
242 
      repeat (104) @(posedge mclk);
243 
      dma_en    = 1'b0;
244 
      if (aclk_cnt  !== 16'h0003) tb_error("====== DMA_SCG1 TEST 6: ACLK  IS NOT RUNNING =====");
245 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_SCG1 TEST 6: SMCLK IS NOT RUNNING =====");
246 
   `endif
247 
 
248 
      @(r15==16'h5000);
249 
 
250 
      // DMA_OSCOFF
251 
      //--------------------------------------------------------
252 
   `ifdef DMA_IF_EN
253 
      @(r15==16'h5001);
254 
      dma_en    = 1'b1;
255 
      aclk_cnt  = 0;
256 
      smclk_cnt = 0;
257 
      repeat (104) @(posedge mclk);
258 
      dma_en    = 1'b0;
259 
      if (aclk_cnt  !== 16'h0000) tb_error("====== DMA_OSCOFF TEST 1: ACLK  IS RUNNING =====");
260 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 1: SMCLK IS RUNNING =====");
261 
 
262 
      @(r15==16'h5002);
263 
      dma_en    = 1'b1;
264 
      aclk_cnt  = 0;
265 
      smclk_cnt = 0;
266 
      repeat (104) @(posedge mclk);
267 
      dma_en    = 1'b0;
268 
      if (aclk_cnt  !== 16'h0004) tb_error("====== DMA_OSCOFF TEST 2: ACLK  IS NOT RUNNING =====");
269 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 2: SMCLK IS NOT RUNNING =====");
270 
 
271 
      @(r15==16'h5003);
272 
      dma_en    = 1'b1;
273 
      aclk_cnt  = 0;
274 
      smclk_cnt = 0;
275 
      repeat (104) @(posedge mclk);
276 
      dma_en    = 1'b0;
277 
      if (aclk_cnt  !== 16'h0000) tb_error("====== DMA_OSCOFF TEST 3: ACLK  IS RUNNING =====");
278 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 3: SMCLK IS NOT RUNNING =====");
279 
 
280 
      @(r15==16'h5004);
281 
      dma_en    = 1'b1;
282 
      aclk_cnt  = 0;
283 
      smclk_cnt = 0;
284 
      repeat (104) @(posedge mclk);
285 
      dma_en    = 1'b0;
286 
      if (aclk_cnt  !== 16'h0003) tb_error("====== DMA_OSCOFF TEST 4: ACLK  IS NOT RUNNING =====");
287 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 4: SMCLK IS NOT RUNNING =====");
288 
 
289 
      @(r15==16'h5005);
290 
      dma_en    = 1'b1;
291 
      aclk_cnt  = 0;
292 
      smclk_cnt = 0;
293 
      repeat (104) @(posedge mclk);
294 
      dma_en    = 1'b0;
295 
      if (aclk_cnt  !== 16'h0000) tb_error("====== DMA_OSCOFF TEST 5: ACLK  IS RUNNING =====");
296 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 5: SMCLK IS NOT RUNNING =====");
297 
 
298 
      @(r15==16'h5006);
299 
      dma_en    = 1'b1;
300 
      aclk_cnt  = 0;
301 
      smclk_cnt = 0;
302 
      repeat (104) @(posedge mclk);
303 
      dma_en    = 1'b0;
304 
      if (aclk_cnt  !== 16'h0003) tb_error("====== DMA_OSCOFF TEST 6: ACLK  IS NOT RUNNING =====");
305 
      if (smclk_cnt !== 16'h000D) tb_error("====== DMA_OSCOFF TEST 6: SMCLK IS NOT RUNNING =====");
306 
   `endif
307 
 
308 
      @(r15==16'h6000);
309 
`endif
310 
 
311 2 olivier.gi 
      stimulus_done = 1;
312 
   end

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.