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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [op_modes.v] - Blame information for rev 83

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1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            CPU OPERATING MODES                            */
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/*---------------------------------------------------------------------------*/
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/* Test the CPU Operating modes:                                             */
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/*                                 - CPUOFF (<=> R2[4]): turn off CPU.       */
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/*                                 - OSCOFF (<=> R2[5]): turn off LFXT_CLK.  */
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/*                                 - SCG1   (<=> R2[7]): turn off SMCLK.     */
30 18 olivier.gi 
/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 79 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2010-11-23 20:36:16 +0100 (Tue, 23 Nov 2010) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
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integer smclk_cnt;
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always @(negedge mclk)
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  if (smclk_en) smclk_cnt <= smclk_cnt+1;
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integer aclk_cnt;
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always @(negedge mclk)
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  if (aclk_en) aclk_cnt <= aclk_cnt+1;
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integer inst_cnt;
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always @(inst_number)
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  inst_cnt = inst_cnt+1;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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60 
 
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      // SCG1   (<=> R2[7]): turn off SMCLK
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      //--------------------------------------------------------
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      @(r15==16'h1001);
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      smclk_cnt = 0;
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      repeat (84) @(posedge mclk);
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      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 1: SMCLK IS NOT RUNNING =====");
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      @(r15==16'h1002);
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      smclk_cnt = 0;
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      repeat (84) @(posedge mclk);
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      if (smclk_cnt !== 16'h0000) tb_error("====== SCG1 TEST 2: SMCLK IS NOT STOPPED =====");
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      @(r15==16'h1003);
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      p1_din[0] = 1'b1;
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      repeat (2) @(posedge mclk);
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      p1_din[0] = 1'b0;
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      smclk_cnt = 0;
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      repeat (84) @(posedge mclk);
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      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 3: SMCLK IS NOT RUNNING DURING IRQ =====");
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      @(r15==16'h1004);
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      smclk_cnt = 0;
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      repeat (84) @(posedge mclk);
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      if (smclk_cnt !== 16'h0000) tb_error("====== SCG1 TEST 4: SMCLK IS NOT STOPPED =====");
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      @(r15==16'h1005);
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      smclk_cnt = 0;
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      repeat (80) @(posedge mclk);
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      if (smclk_cnt !== 16'h000a) tb_error("====== SCG1 TEST 5: SMCLK IS NOT RUNNING =====");
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92 
 
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      // OSCOFF  (<=> R2[5]): turn off LFXT1CLK
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      //--------------------------------------------------------
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      @(r15==16'h2001);
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      aclk_cnt  = 0;
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      smclk_cnt = 0;
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      repeat (104) @(posedge mclk);
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      if (aclk_cnt  !== 16'h0004) tb_error("====== OSCOFF TEST 1: ACLK  IS NOT RUNNING =====");
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      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 1: SMCLK IS NOT RUNNING ON MCLK =====");
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      @(r15==16'h2002);
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      aclk_cnt  = 0;
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      smclk_cnt = 0;
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      repeat (104) @(posedge mclk);
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      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 2: ACLK  IS NOT STOPPED =====");
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      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 2: SMCLK IS NOT RUNNING ON MCLK =====");
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      @(r15==16'h2003);
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      p1_din[0] = 1'b1;
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      repeat (2) @(posedge mclk);
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      p1_din[0] = 1'b0;
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      aclk_cnt  = 0;
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      smclk_cnt = 0;
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      repeat (104) @(posedge mclk);
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      if (aclk_cnt  !== 16'h0003) tb_error("====== OSCOFF TEST 3: ACLK  IS NOT RUNNING DURING IRQ =====");
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      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 3: SMCLK IS NOT RUNNING ON MCLK =====");
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       @(r15==16'h2004);
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      aclk_cnt  = 0;
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      smclk_cnt = 0;
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      repeat (104) @(posedge mclk);
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      if (aclk_cnt  !== 16'h0000) tb_error("====== OSCOFF TEST 4: ACLK  IS NOT STOPPED =====");
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      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 4: SMCLK IS NOT RUNNING ON MCLK =====");
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      @(r15==16'h2005);
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      aclk_cnt  = 0;
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      smclk_cnt = 0;
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      repeat (104) @(posedge mclk);
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      if (aclk_cnt  !== 16'h0004) tb_error("====== OSCOFF TEST 5: ACLK  IS NOT RUNNING =====");
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      if (smclk_cnt !== 16'h0004) tb_error("====== OSCOFF TEST 5: SMCLK IS NOT RUNNING ON LFXT1 =====");
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      @(r15==16'h2006);
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      aclk_cnt  = 0;
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      smclk_cnt = 0;
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      repeat (104) @(posedge mclk);
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      if (aclk_cnt  !== 16'h0003) tb_error("====== OSCOFF TEST 6: ACLK  IS NOT RUNNING =====");
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      if (smclk_cnt !== 16'h0068) tb_error("====== OSCOFF TEST 6: SMCLK IS NOT RUNNING ON MCLK =====");
140 
 
141 
 
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      // CPUOFF  (<=> R2[4]): turn off CPU
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      //--------------------------------------------------------
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      @(r15==16'h3001);
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      @(negedge mclk);
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      inst_cnt  = 0;
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      repeat (80) @(negedge mclk);
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      if (inst_cnt  !== 16'h0034) tb_error("====== CPUOFF TEST 1: CPU IS NOT RUNNING =====");
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      @(r15==16'h3002);
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      repeat (3) @(negedge mclk);
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      inst_cnt  = 0;
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      repeat (80) @(negedge mclk);
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      if (inst_cnt  !== 16'h0000) tb_error("====== CPUOFF TEST 2: CPU IS NOT STOPPED =====");
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      @(posedge mclk);
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      p1_din[0] = 1'b1;
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      repeat (2) @(posedge mclk);
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      p1_din[0] = 1'b0;
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      @(negedge mclk);
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      inst_cnt  = 0;
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      repeat (80) @(negedge mclk);
164 79 olivier.gi 
      if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 3: CPU IS NOT RUNNING DURING IRQ (PORT 1) =====");
165 
 
166 2 olivier.gi 
      @(r1==16'h0250);
167 
      repeat (3) @(negedge mclk);
168 
      inst_cnt  = 0;
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      repeat (80) @(negedge mclk);
170 
      if (inst_cnt  !== 16'h0000) tb_error("====== CPUOFF TEST 4: CPU IS NOT STOPPED AFTER IRQ =====");
171 
 
172 
      @(posedge mclk);
173 
      p2_din[0] = 1'b1;
174 
      repeat (2) @(posedge mclk);
175 
      p2_din[0] = 1'b0;
176 
      @(negedge mclk);
177 
      inst_cnt  = 0;
178 
      repeat (80) @(negedge mclk);
179 79 olivier.gi 
      if (inst_cnt !== 16'h0030) tb_error("====== CPUOFF TEST 5: CPU IS NOT RUNNING DURING IRQ (PORT 2) =====");
180 2 olivier.gi 
 
181 
      @(r15==16'h3003);
182 
      @(negedge mclk);
183 
      inst_cnt  = 0;
184 
      repeat (80) @(negedge mclk);
185 
      if (inst_cnt  !== 16'h0034) tb_error("====== CPUOFF TEST 6: CPU IS NOT RUNNING =====");
186 
 
187 
 
188 
      stimulus_done = 1;
189 
   end
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