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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sfr.s43] - Blame information for rev 145

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1 134 olivier.gi 
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                  Special Function Registers (SFRs)                        */
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/*---------------------------------------------------------------------------*/
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/* Test the SFR registers.                                                   */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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37 141 olivier.gi 
.include "pmem_defs.asm"
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39 134 olivier.gi 
.global main
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main:
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        /* -------   NMI             ------ */
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        mov   #0x1000, r15
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        ;; NMI feature is verified in the NMI.S43 test
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        mov   #0x1001, r15
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        /* -------   WATCHDOG        ------ */
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        mov   #0x2000, r15
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        ;; WATCHDOG feature is verified in the WDT_*.S43 tests
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        mov   #0x5a90, &WDTCTL	  ;# Enable interval mode & disable timer
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        mov   #0x2001, r15
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        /* -------   READ/WRITE IFG1       ------ */
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        mov   #0x3000, r15
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        mov   &IFG1,   r10
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        mov   #0x3001, r15
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        mov   #0x5555, &IFG1
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        mov   &IFG1,   r10
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        mov   #0x3002, r15
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        mov   #0xAAAA, &IFG1
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        mov   &IFG1,   r10
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        mov   #0x3003, r15
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        mov.b #0x55,   &IFG1
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        mov.b &IFG1,   r10
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        mov   #0x3004, r15
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        mov.b #0xAA,    &IFG1_HI
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        mov.b &IFG1_HI, r10
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        mov   #0x3005,  r15
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        mov   #0x0000, &IFG1
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        mov   &IFG1,   r10
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        mov   #0x3006, r15
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        /* -------   READ/WRITE IE1         ------ */
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        mov   #0x4000, r15
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        mov   &IE1,    r10
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        mov   #0x4001, r15
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        mov   #0x5555, &IE1
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        mov   &IE1,    r10
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        mov   #0x4002, r15
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        mov   #0xAAAA, &IE1
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        mov   &IE1,    r10
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        mov   #0x4003, r15
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        mov.b #0x55,   &IE1
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        mov.b &IE1,    r10
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        mov   #0x4004, r15
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        mov.b #0xAA,    &IE1_HI
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        mov.b &IE1_HI,  r10
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        mov   #0x4005,  r15
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        mov   #0x0000, &IE1
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        mov   &IE1,    r10
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        mov   #0x4006, r15
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        /* -------   READ/WRITE CPU_ID     ------ */
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        mov   #0x5000, r15
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        mov   &CPU_ID_LO, r10
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        mov   &CPU_ID_HI, r11
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        mov   #0x5001, r15
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        mov   0x5555,     &CPU_ID_LO
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        mov   0xAAAA,     &CPU_ID_HI
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        mov   &CPU_ID_LO, r10
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        mov   &CPU_ID_HI, r11
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        mov   #0x5002, r15
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        mov   0xAAAA,     &CPU_ID_LO
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        mov   0x5555,     &CPU_ID_HI
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        mov   &CPU_ID_LO, r10
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        mov   &CPU_ID_HI, r11
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        mov   #0x5003, r15
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        /* ----------------------         END OF TEST        --------------- */
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test     ; Interrupt  0 (lowest priority)
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.word end_of_test     ; Interrupt  1
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.word end_of_test     ; Interrupt  2
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.word end_of_test     ; Interrupt  3
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.word end_of_test     ; Interrupt  4
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.word end_of_test     ; Interrupt  5
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.word end_of_test     ; Interrupt  6
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.word end_of_test     ; Interrupt  7
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.word end_of_test     ; Interrupt  8
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.word end_of_test     ; Interrupt  9
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.word end_of_test     ; Interrupt 10                      Watchdog timer
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.word end_of_test     ; Interrupt 11
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.word end_of_test     ; Interrupt 12
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.word end_of_test     ; Interrupt 13
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.word end_of_test     ; Interrupt 14                      NMI
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.word main            ; Interrupt 15 (highest priority)   RESET

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