OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sfr.v] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                  Special Function Registers (SFRs)                        */
25
/*---------------------------------------------------------------------------*/
26
/* Test the SFR registers.                                                   */
27
/*                                                                           */
28
/* Author(s):                                                                */
29
/*             - Olivier Girard,    olgirard@gmail.com                       */
30
/*                                                                           */
31
/*---------------------------------------------------------------------------*/
32
/* $Rev: 85 $                                                                */
33
/* $LastChangedBy: olivier.girard $                                          */
34
/* $LastChangedDate: 2011-01-28 22:05:37 +0100 (Fri, 28 Jan 2011) $          */
35
/*===========================================================================*/
36
 
37
reg  [2:0] cpu_version;
38
reg        cpu_asic;
39
reg  [4:0] user_version;
40
reg  [6:0] per_space;
41
reg        mpy_info;
42
reg  [8:0] dmem_size;
43
reg  [5:0] pmem_size;
44
reg [31:0] dbg_id;
45
 
46 154 olivier.gi
// Set oMSP parameters for later check
47
defparam dut.INST_NR  = 8'h12;
48
defparam dut.TOTAL_NR = 8'h34;
49
 
50 134 olivier.gi
initial
51
   begin
52
      $display(" ===============================================");
53
      $display("|                 START SIMULATION              |");
54
      $display(" ===============================================");
55
      repeat(5) @(posedge mclk);
56
      stimulus_done = 0;
57
 
58
      //  NMI
59
      //------------------------------
60
      @(r15 === 16'h1000);
61
 
62
      // NMI feature is verified in the NMI.S43 test
63
 
64
      @(r15 === 16'h1001);
65
 
66
      //  WATCHDOG
67
      //------------------------------
68
      @(r15 === 16'h2000);
69
 
70
      // WATCHDOG feature is verified in the WDT_*.S43 tests
71
 
72
      @(r15 === 16'h2001);
73
 
74
 
75
      //  READ/WRITE IFG1
76
      //------------------------------
77
      @(r15 === 16'h3000);
78
 
79
      @(r15 === 16'h3001);
80
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 1) =====");
81
 
82
      @(r15 === 16'h3002);
83
      `ifdef NMI
84
         `ifdef WATCHDOG
85
      if (r10 !== 16'h0011)   tb_error("====== IFG1 incorrect (test 2) =====");
86
         `else
87
      if (r10 !== 16'h0010)   tb_error("====== IFG1 incorrect (test 3) =====");
88
         `endif
89
      `else
90
         `ifdef WATCHDOG
91
      if (r10 !== 16'h0001)   tb_error("====== IFG1 incorrect (test 4) =====");
92
         `else
93
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 5) =====");
94
         `endif
95
      `endif
96
 
97
      @(r15 === 16'h3003);
98
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 6) =====");
99
 
100
      @(r15 === 16'h3004);
101
      `ifdef NMI
102
         `ifdef WATCHDOG
103
      if (r10 !== 16'h0011)   tb_error("====== IFG1 incorrect (test 7) =====");
104
         `else
105
      if (r10 !== 16'h0010)   tb_error("====== IFG1 incorrect (test 8) =====");
106
         `endif
107
      `else
108
         `ifdef WATCHDOG
109
      if (r10 !== 16'h0001)   tb_error("====== IFG1 incorrect (test 9) =====");
110
         `else
111
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 10) =====");
112
         `endif
113
      `endif
114
 
115
      @(r15 === 16'h3005);
116
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 11) =====");
117
 
118
      @(r15 === 16'h3006);
119
      if (r10 !== 16'h0000)   tb_error("====== IFG1 incorrect (test 12) =====");
120
 
121
 
122
      //  READ/WRITE IE1
123
      //------------------------------
124
      @(r15 === 16'h4000);
125
 
126
      @(r15 === 16'h4001);
127
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 1) =====");
128
 
129
      @(r15 === 16'h4002);
130
      `ifdef NMI
131
         `ifdef WATCHDOG
132
      if (r10 !== 16'h0011)   tb_error("====== IE1 incorrect (test 2) =====");
133
         `else
134
      if (r10 !== 16'h0010)   tb_error("====== IE1 incorrect (test 3) =====");
135
         `endif
136
      `else
137
         `ifdef WATCHDOG
138
      if (r10 !== 16'h0001)   tb_error("====== IE1 incorrect (test 4) =====");
139
         `else
140
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 5) =====");
141
         `endif
142
      `endif
143
 
144
      @(r15 === 16'h4003);
145
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 6) =====");
146
 
147
      @(r15 === 16'h4004);
148
      `ifdef NMI
149
         `ifdef WATCHDOG
150
      if (r10 !== 16'h0011)   tb_error("====== IE1 incorrect (test 7) =====");
151
         `else
152
      if (r10 !== 16'h0010)   tb_error("====== IE1 incorrect (test 8) =====");
153
         `endif
154
      `else
155
         `ifdef WATCHDOG
156
      if (r10 !== 16'h0001)   tb_error("====== IE1 incorrect (test 9) =====");
157
         `else
158
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 10) =====");
159
         `endif
160
      `endif
161
 
162
      @(r15 === 16'h4005);
163
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 11) =====");
164
 
165
      @(r15 === 16'h4006);
166
      if (r10 !== 16'h0000)   tb_error("====== IE1 incorrect (test 12) =====");
167
 
168
 
169
      // READ/WRITE CPU_ID
170
      //------------------------------
171
      @(r15 === 16'h5000);
172
 
173
      cpu_version  =  `CPU_VERSION;
174
`ifdef ASIC
175
      cpu_asic     =  1'b1;
176
`else
177
      cpu_asic     =  1'b0;
178
`endif
179
      user_version =  `USER_VERSION;
180
      per_space    = (`PER_SIZE  >> 9);
181
`ifdef MULTIPLIER
182
      mpy_info     =  1'b1;
183
`else
184
      mpy_info     =  1'b0;
185
`endif
186
      dmem_size    = (`DMEM_SIZE >> 7);
187
      pmem_size    = (`PMEM_SIZE >> 10);
188
 
189
      dbg_id       = {pmem_size,
190
                      dmem_size,
191
                      mpy_info,
192
                      per_space,
193
                      user_version,
194
                      cpu_asic,
195
                      cpu_version};
196
 
197
      @(r15 === 16'h5001);
198
      if (r10 !== dbg_id[15:0])   tb_error("====== CPU_ID_LO incorrect (test 1) =====");
199
      if (r11 !== dbg_id[31:16])  tb_error("====== CPU_ID_HI incorrect (test 2) =====");
200
 
201
      @(r15 === 16'h5002);
202
      if (r10 !== dbg_id[15:0])   tb_error("====== CPU_ID_LO incorrect (test 3) =====");
203
      if (r11 !== dbg_id[31:16])  tb_error("====== CPU_ID_HI incorrect (test 4) =====");
204
 
205
      @(r15 === 16'h5003);
206
      if (r10 !== dbg_id[15:0])   tb_error("====== CPU_ID_LO incorrect (test 5) =====");
207
      if (r11 !== dbg_id[31:16])  tb_error("====== CPU_ID_HI incorrect (test 6) =====");
208
 
209 154 olivier.gi
 
210
      // READ/WRITE CPU_NR
211
      //------------------------------
212
      @(r15 === 16'h6000);
213
 
214
      @(r15 === 16'h6001);
215
      if (r10 !== 16'h3412)       tb_error("====== CPU_NR incorrect (test 1) =====");
216
 
217
      @(r15 === 16'h6002);
218
      if (r10 !== 16'h3412)       tb_error("====== CPU_NR incorrect (test 2) =====");
219
 
220
      @(r15 === 16'h6003);
221
      if (r10 !== 16'h3412)       tb_error("====== CPU_NR incorrect (test 3) =====");
222
 
223
 
224
 
225 134 olivier.gi
      stimulus_done = 1;
226
   end
227
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.