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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Blame information for rev 134

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: CALL  INSTRUCTION              */
/*---------------------------------------------------------------------------*/
/* Test the CALL  instruction.                                               */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 134 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
/*===========================================================================*/
 
.set    DMEM_BASE, (__data_start     )
.set    DMEM_200,  (__data_start+0x00)
.set    DMEM_250,  (__data_start+0x50)
.set    DMEM_252,  (__data_start+0x52)
.set    DMEM_300,  (__data_start+0x100)
 
.global main
 
        mov     #0x1234, r3
        mov     #0x1234, r4
        mov     #0x1234, r5
        mov     #0x1234, r6
        mov     #0x1234, r7
        mov     #0x1234, r8
        mov     #0x1234, r9
        mov     #0x1234, r10
        mov     #0x1234, r11
        mov     #0x1234, r12
        mov     #0x1234, r13
        mov     #0x1234, r14
main:
        # Test RESET vector
        #------------------------
        mov     #0x1000, r15
 
 
        # Test RETI instruction
        #------------------------
 
        # Pre-initialize stack
        mov             #DMEM_252, r1
        push #RETI_ROUTINE
        push            #0x010f
        mov     #0x0000, &0x0200
 
        # Run RETI test
        mov     #0x0000, r2
        mov     #0x0000, r5
        reti
end_of_reti_test:
 
        mov     #0x2000, r15
 
 
        # Test IRQ  0
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x3000, r15
 
wait_irq00:
        cmp     #0x5678, r6
        jne     wait_irq00
 
        mov     #0x3001, r15
 
 
        # Test IRQ  1
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x4000, r15
 
wait_irq01:
        cmp     #0x9abc, r6
        jne     wait_irq01
 
        mov     #0x4001, r15
 
 
        # Test IRQ  2
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x5000, r15
 
wait_irq02:
        cmp     #0xdef1, r6
        jne     wait_irq02
 
        mov     #0x5001, r15
 
 
        # Test IRQ  3
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x6000, r15
 
wait_irq03:
        cmp     #0x2345, r6
        jne     wait_irq03
 
        mov     #0x6001, r15
 
 
        # Test IRQ  4
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x7000, r15
 
wait_irq04:
        cmp     #0x6789, r6
        jne     wait_irq04
 
        mov     #0x7001, r15
 
 
        # Test IRQ  5
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x8000, r15
 
wait_irq05:
        cmp     #0xabcd, r6
        jne     wait_irq05
 
        mov     #0x8001, r15
 
 
        # Test IRQ  6
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0x9000, r15
 
wait_irq06:
        cmp     #0xef12, r6
        jne     wait_irq06
 
        mov     #0x9001, r15
 
 
        # Test IRQ  7
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xa000, r15
 
wait_irq07:
        cmp     #0x3456, r6
        jne     wait_irq07
 
        mov     #0xa001, r15
 
 
        # Test IRQ  8
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xb000, r15
 
wait_irq08:
        cmp     #0x789a, r6
        jne     wait_irq08
 
        mov     #0xb001, r15
 
 
        # Test IRQ  9
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xc000, r15
 
wait_irq09:
        cmp     #0xbcde, r6
        jne     wait_irq09
 
        mov     #0xc001, r15
 
 
        # Test IRQ 10
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xd000, r15
 
wait_irq10:
        cmp     #0xf123, r6
        jne     wait_irq10
 
        mov     #0xd001, r15
 
 
        # Test IRQ 11
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xe000, r15
 
wait_irq11:
        cmp     #0x4567, r6
        jne     wait_irq11
 
        mov     #0xe001, r15
 
 
        # Test IRQ 12
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf000, r15
 
wait_irq12:
        cmp     #0x89ab, r6
        jne     wait_irq12
 
        mov     #0xf001, r15
 
 
        # Test IRQ 13
        #-------------------------
 
        mov     #0x0008, r2  ; Enable interrupts
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf100, r15
 
wait_irq13:
        cmp     #0xcdef, r6
        jne     wait_irq13
 
        mov     #0xf101, r15
 
 
        # Test IRQ NMI:  rising edge
        #----------------------------
 
.set   WDTCTL, 0x0120
.set   IE1,    0x0000
.set   IFG1,   0x0002
 
 
        mov     #0x5a00, &WDTCTL  ; NMI Edge selection: rising
        bic.b   #0x0010, &IFG1    ; Clear NMI flag
        bis.b   #0x0010, &IE1     ; Enable NMI
 
        bit     #0x0010, &IE1     ; skip this test if the NMI is not included
        jz      skip_nmi
 
        mov     #0x0000, r6
        mov     #0xaaaa, r7
        mov     #0x5555, r8
        mov     #0xf200, r15
 
wait_nmi:
        mov     #0xa5a5, &0x0200
        cmp     #0x0123, r6
        jne    wait_nmi
 
        mov.b      &IE1,  r9
        mov.b     &IFG1, r10
        bic.b     #0x10, &IFG1    ; Clear NMI flag
        bis.b     #0x10, &IE1     ; Enable NMI
 
skip_nmi:
        mov     #0xf201, r15
 
 
 
        /* ----------------------    END OF TEST   --------------- */
end_of_test:
        nop
        br #0xffff
 
 
 
        /* ----------------------    FUNCTIONS    --------------- */
 
RETI_ROUTINE:
        mov #0x1234, r5
        jmp end_of_reti_test
 
 
IRQ00_ROUTINE:
        mov #0x5678, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ01_ROUTINE:
        mov #0x9abc, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ02_ROUTINE:
        mov #0xdef1, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ03_ROUTINE:
        mov #0x2345, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ04_ROUTINE:
        mov #0x6789, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ05_ROUTINE:
        mov #0xabcd, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ06_ROUTINE:
        mov #0xef12, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ07_ROUTINE:
        mov #0x3456, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ08_ROUTINE:
        mov #0x789a, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ09_ROUTINE:
        mov #0xbcde, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ10_ROUTINE:
        mov #0xf123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ11_ROUTINE:
        mov #0x4567, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ12_ROUTINE:
        mov #0x89ab, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
IRQ13_ROUTINE:
        mov #0xcdef, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
NMI_ROUTINE:
        mov #0x0123, r6
        mov      r2, r7 ; Save Status register
        mov      r1, r8 ; Save Stack register
        reti
 
        nop
        nop
        nop
        nop
        nop
 
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word IRQ00_ROUTINE     ; Interrupt  0 (lowest priority)    
.word IRQ01_ROUTINE     ; Interrupt  1                      
.word IRQ02_ROUTINE     ; Interrupt  2                      
.word IRQ03_ROUTINE     ; Interrupt  3                      
.word IRQ04_ROUTINE     ; Interrupt  4                      
.word IRQ05_ROUTINE     ; Interrupt  5                      
.word IRQ06_ROUTINE     ; Interrupt  6                      
.word IRQ07_ROUTINE     ; Interrupt  7                      
.word IRQ08_ROUTINE     ; Interrupt  8                      
.word IRQ09_ROUTINE     ; Interrupt  9                      
.word IRQ10_ROUTINE     ; Interrupt 10                      Watchdog timer
.word IRQ11_ROUTINE     ; Interrupt 11                      
.word IRQ12_ROUTINE     ; Interrupt 12                      
.word IRQ13_ROUTINE     ; Interrupt 13                      
.word NMI_ROUTINE       ; Interrupt 14                      NMI
.word main              ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_reti.s43] - Blame information for rev 134

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* SINGLE-OPERAND ARITHMETIC: CALL INSTRUCTION */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the CALL instruction. */`
27	18	olivier.gi	`/* */`
28			`/* Author(s): */`
29			`/* - Olivier Girard, olgirard@gmail.com */`
30			`/* */`
31			`/---------------------------------------------------------------------------/`
32	19	olivier.gi	`/* $Rev: 134 $ */`
33			`/* $LastChangedBy: olivier.girard $ */`
34			`/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $ */`
35	2	olivier.gi	`/===========================================================================/`
36
37	111	olivier.gi	`.set DMEM_BASE, (__data_start )`
38			`.set DMEM_200, (__data_start+0x00)`
39			`.set DMEM_250, (__data_start+0x50)`
40			`.set DMEM_252, (__data_start+0x52)`
41			`.set DMEM_300, (__data_start+0x100)`
42	2	olivier.gi
43			`.global main`
44
45			`mov #0x1234, r3`
46			`mov #0x1234, r4`
47			`mov #0x1234, r5`
48			`mov #0x1234, r6`
49			`mov #0x1234, r7`
50			`mov #0x1234, r8`
51			`mov #0x1234, r9`
52			`mov #0x1234, r10`
53			`mov #0x1234, r11`
54			`mov #0x1234, r12`
55			`mov #0x1234, r13`
56			`mov #0x1234, r14`
57			`main:`
58			`# Test RESET vector`
59			`#------------------------`
60			`mov #0x1000, r15`
61
62
63			`# Test RETI instruction`
64			`#------------------------`
65
66			`# Pre-initialize stack`
67	111	olivier.gi	`mov #DMEM_252, r1`
68	2	olivier.gi	`push #RETI_ROUTINE`
69	134	olivier.gi	`push #0x010f`
70	2	olivier.gi	`mov #0x0000, &0x0200`
71
72			`# Run RETI test`
73			`mov #0x0000, r2`
74			`mov #0x0000, r5`
75			`reti`
76			`end_of_reti_test:`
77
78			`mov #0x2000, r15`
79
80
81			`# Test IRQ 0`
82			`#-------------------------`
83
84			`mov #0x0008, r2 ; Enable interrupts`
85			`mov #0x0000, r6`
86			`mov #0xaaaa, r7`
87			`mov #0x5555, r8`
88			`mov #0x3000, r15`
89
90			`wait_irq00:`
91			`cmp #0x5678, r6`
92			`jne wait_irq00`
93
94			`mov #0x3001, r15`
95
96
97			`# Test IRQ 1`
98			`#-------------------------`
99
100			`mov #0x0008, r2 ; Enable interrupts`
101			`mov #0x0000, r6`
102			`mov #0xaaaa, r7`
103			`mov #0x5555, r8`
104			`mov #0x4000, r15`
105
106			`wait_irq01:`
107			`cmp #0x9abc, r6`
108			`jne wait_irq01`
109
110			`mov #0x4001, r15`
111
112
113			`# Test IRQ 2`
114			`#-------------------------`
115
116			`mov #0x0008, r2 ; Enable interrupts`
117			`mov #0x0000, r6`
118			`mov #0xaaaa, r7`
119			`mov #0x5555, r8`
120			`mov #0x5000, r15`
121
122			`wait_irq02:`
123			`cmp #0xdef1, r6`
124			`jne wait_irq02`
125
126			`mov #0x5001, r15`
127
128
129			`# Test IRQ 3`
130			`#-------------------------`
131
132			`mov #0x0008, r2 ; Enable interrupts`
133			`mov #0x0000, r6`
134			`mov #0xaaaa, r7`
135			`mov #0x5555, r8`
136			`mov #0x6000, r15`
137
138			`wait_irq03:`
139			`cmp #0x2345, r6`
140			`jne wait_irq03`
141
142			`mov #0x6001, r15`
143
144
145			`# Test IRQ 4`
146			`#-------------------------`
147
148			`mov #0x0008, r2 ; Enable interrupts`
149			`mov #0x0000, r6`
150			`mov #0xaaaa, r7`
151			`mov #0x5555, r8`
152			`mov #0x7000, r15`
153
154			`wait_irq04:`
155			`cmp #0x6789, r6`
156			`jne wait_irq04`
157
158			`mov #0x7001, r15`
159
160
161			`# Test IRQ 5`
162			`#-------------------------`
163
164			`mov #0x0008, r2 ; Enable interrupts`
165			`mov #0x0000, r6`
166			`mov #0xaaaa, r7`
167			`mov #0x5555, r8`
168			`mov #0x8000, r15`
169
170			`wait_irq05:`
171			`cmp #0xabcd, r6`
172			`jne wait_irq05`
173
174			`mov #0x8001, r15`
175
176
177			`# Test IRQ 6`
178			`#-------------------------`
179
180			`mov #0x0008, r2 ; Enable interrupts`
181			`mov #0x0000, r6`
182			`mov #0xaaaa, r7`
183			`mov #0x5555, r8`
184			`mov #0x9000, r15`
185
186			`wait_irq06:`
187			`cmp #0xef12, r6`
188			`jne wait_irq06`
189
190			`mov #0x9001, r15`
191
192
193			`# Test IRQ 7`
194			`#-------------------------`
195
196			`mov #0x0008, r2 ; Enable interrupts`
197			`mov #0x0000, r6`
198			`mov #0xaaaa, r7`
199			`mov #0x5555, r8`
200			`mov #0xa000, r15`
201
202			`wait_irq07:`
203			`cmp #0x3456, r6`
204			`jne wait_irq07`
205
206			`mov #0xa001, r15`
207
208
209			`# Test IRQ 8`
210			`#-------------------------`
211
212			`mov #0x0008, r2 ; Enable interrupts`
213			`mov #0x0000, r6`
214			`mov #0xaaaa, r7`
215			`mov #0x5555, r8`
216			`mov #0xb000, r15`
217
218			`wait_irq08:`
219			`cmp #0x789a, r6`
220			`jne wait_irq08`
221
222			`mov #0xb001, r15`
223
224
225			`# Test IRQ 9`
226			`#-------------------------`
227
228			`mov #0x0008, r2 ; Enable interrupts`
229			`mov #0x0000, r6`
230			`mov #0xaaaa, r7`
231			`mov #0x5555, r8`
232			`mov #0xc000, r15`
233
234			`wait_irq09:`
235			`cmp #0xbcde, r6`
236			`jne wait_irq09`
237
238			`mov #0xc001, r15`
239
240
241			`# Test IRQ 10`
242			`#-------------------------`
243
244			`mov #0x0008, r2 ; Enable interrupts`
245			`mov #0x0000, r6`
246			`mov #0xaaaa, r7`
247			`mov #0x5555, r8`
248			`mov #0xd000, r15`
249
250			`wait_irq10:`
251			`cmp #0xf123, r6`
252			`jne wait_irq10`
253
254			`mov #0xd001, r15`
255
256
257			`# Test IRQ 11`
258			`#-------------------------`
259
260			`mov #0x0008, r2 ; Enable interrupts`
261			`mov #0x0000, r6`
262			`mov #0xaaaa, r7`
263			`mov #0x5555, r8`
264			`mov #0xe000, r15`
265
266			`wait_irq11:`
267			`cmp #0x4567, r6`
268			`jne wait_irq11`
269
270			`mov #0xe001, r15`
271
272
273			`# Test IRQ 12`
274			`#-------------------------`
275
276			`mov #0x0008, r2 ; Enable interrupts`
277			`mov #0x0000, r6`
278			`mov #0xaaaa, r7`
279			`mov #0x5555, r8`
280			`mov #0xf000, r15`
281
282			`wait_irq12:`
283			`cmp #0x89ab, r6`
284			`jne wait_irq12`
285
286			`mov #0xf001, r15`
287
288
289			`# Test IRQ 13`
290			`#-------------------------`
291
292			`mov #0x0008, r2 ; Enable interrupts`
293			`mov #0x0000, r6`
294			`mov #0xaaaa, r7`
295			`mov #0x5555, r8`
296			`mov #0xf100, r15`
297
298			`wait_irq13:`
299			`cmp #0xcdef, r6`
300			`jne wait_irq13`
301
302			`mov #0xf101, r15`
303
304
305			`# Test IRQ NMI: rising edge`
306			`#----------------------------`
307	134	olivier.gi
308	2	olivier.gi	`.set WDTCTL, 0x0120`
309			`.set IE1, 0x0000`
310			`.set IFG1, 0x0002`
311
312	134	olivier.gi
313	2	olivier.gi	`mov #0x5a00, &WDTCTL ; NMI Edge selection: rising`
314			`bic.b #0x0010, &IFG1 ; Clear NMI flag`
315			`bis.b #0x0010, &IE1 ; Enable NMI`
316
317	134	olivier.gi	`bit #0x0010, &IE1 ; skip this test if the NMI is not included`
318			`jz skip_nmi`
319
320	2	olivier.gi	`mov #0x0000, r6`
321			`mov #0xaaaa, r7`
322			`mov #0x5555, r8`
323			`mov #0xf200, r15`
324
325			`wait_nmi:`
326			`mov #0xa5a5, &0x0200`
327			`cmp #0x0123, r6`
328			`jne wait_nmi`
329
330			`mov.b &IE1, r9`
331	134	olivier.gi	`mov.b &IFG1, r10`
332			`bic.b #0x10, &IFG1 ; Clear NMI flag`
333			`bis.b #0x10, &IE1 ; Enable NMI`
334	2	olivier.gi
335	134	olivier.gi	`skip_nmi:`
336	2	olivier.gi	`mov #0xf201, r15`
337
338
339
340			`/* ---------------------- END OF TEST --------------- */`
341			`end_of_test:`
342			`nop`
343			`br #0xffff`
344
345
346
347			`/* ---------------------- FUNCTIONS --------------- */`
348
349			`RETI_ROUTINE:`
350			`mov #0x1234, r5`
351			`jmp end_of_reti_test`
352
353
354			`IRQ00_ROUTINE:`
355			`mov #0x5678, r6`
356			`mov r2, r7 ; Save Status register`
357			`mov r1, r8 ; Save Stack register`
358			`reti`
359
360			`IRQ01_ROUTINE:`
361			`mov #0x9abc, r6`
362			`mov r2, r7 ; Save Status register`
363			`mov r1, r8 ; Save Stack register`
364			`reti`
365
366			`IRQ02_ROUTINE:`
367			`mov #0xdef1, r6`
368			`mov r2, r7 ; Save Status register`
369			`mov r1, r8 ; Save Stack register`
370			`reti`
371
372			`IRQ03_ROUTINE:`
373			`mov #0x2345, r6`
374			`mov r2, r7 ; Save Status register`
375			`mov r1, r8 ; Save Stack register`
376			`reti`
377
378			`IRQ04_ROUTINE:`
379			`mov #0x6789, r6`
380			`mov r2, r7 ; Save Status register`
381			`mov r1, r8 ; Save Stack register`
382			`reti`
383
384			`IRQ05_ROUTINE:`
385			`mov #0xabcd, r6`
386			`mov r2, r7 ; Save Status register`
387			`mov r1, r8 ; Save Stack register`
388			`reti`
389
390			`IRQ06_ROUTINE:`
391			`mov #0xef12, r6`
392			`mov r2, r7 ; Save Status register`
393			`mov r1, r8 ; Save Stack register`
394			`reti`
395
396			`IRQ07_ROUTINE:`
397			`mov #0x3456, r6`
398			`mov r2, r7 ; Save Status register`
399			`mov r1, r8 ; Save Stack register`
400			`reti`
401
402			`IRQ08_ROUTINE:`
403			`mov #0x789a, r6`
404			`mov r2, r7 ; Save Status register`
405			`mov r1, r8 ; Save Stack register`
406			`reti`
407
408			`IRQ09_ROUTINE:`
409			`mov #0xbcde, r6`
410			`mov r2, r7 ; Save Status register`
411			`mov r1, r8 ; Save Stack register`
412			`reti`
413
414			`IRQ10_ROUTINE:`
415			`mov #0xf123, r6`
416			`mov r2, r7 ; Save Status register`
417			`mov r1, r8 ; Save Stack register`
418			`reti`
419
420			`IRQ11_ROUTINE:`
421			`mov #0x4567, r6`
422			`mov r2, r7 ; Save Status register`
423			`mov r1, r8 ; Save Stack register`
424			`reti`
425
426			`IRQ12_ROUTINE:`
427			`mov #0x89ab, r6`
428			`mov r2, r7 ; Save Status register`
429			`mov r1, r8 ; Save Stack register`
430			`reti`
431
432			`IRQ13_ROUTINE:`
433			`mov #0xcdef, r6`
434			`mov r2, r7 ; Save Status register`
435			`mov r1, r8 ; Save Stack register`
436			`reti`
437
438			`NMI_ROUTINE:`
439			`mov #0x0123, r6`
440			`mov r2, r7 ; Save Status register`
441			`mov r1, r8 ; Save Stack register`
442			`reti`
443
444			`nop`
445			`nop`
446			`nop`
447			`nop`
448			`nop`
449
450
451
452			`/* ---------------------- INTERRUPT VECTORS --------------- */`
453
454			`.section .vectors, "a"`
455			`.word IRQ00_ROUTINE ; Interrupt 0 (lowest priority)`
456			`.word IRQ01_ROUTINE ; Interrupt 1`
457			`.word IRQ02_ROUTINE ; Interrupt 2`
458			`.word IRQ03_ROUTINE ; Interrupt 3`
459			`.word IRQ04_ROUTINE ; Interrupt 4`
460			`.word IRQ05_ROUTINE ; Interrupt 5`
461			`.word IRQ06_ROUTINE ; Interrupt 6`
462			`.word IRQ07_ROUTINE ; Interrupt 7`
463			`.word IRQ08_ROUTINE ; Interrupt 8`
464			`.word IRQ09_ROUTINE ; Interrupt 9`
465			`.word IRQ10_ROUTINE ; Interrupt 10 Watchdog timer`
466			`.word IRQ11_ROUTINE ; Interrupt 11`
467			`.word IRQ12_ROUTINE ; Interrupt 12`
468			`.word IRQ13_ROUTINE ; Interrupt 13`
469			`.word NMI_ROUTINE ; Interrupt 14 NMI`
470			`.word main ; Interrupt 15 (highest priority) RESET`