OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_swpb.v] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 SINGLE-OPERAND ARITHMETIC: SWPB INSTRUCTION               */
25
/*---------------------------------------------------------------------------*/
26
/* Test the SWPB instruction.                                                */
27 18 olivier.gi
/*                                                                           */
28
/* Author(s):                                                                */
29
/*             - Olivier Girard,    olgirard@gmail.com                       */
30
/*                                                                           */
31
/*---------------------------------------------------------------------------*/
32 19 olivier.gi
/* $Rev: 111 $                                                                */
33
/* $LastChangedBy: olivier.girard $                                          */
34
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
35 2 olivier.gi
/*===========================================================================*/
36
 
37
initial
38
   begin
39
      $display(" ===============================================");
40
      $display("|                 START SIMULATION              |");
41
      $display(" ===============================================");
42
      repeat(5) @(posedge mclk);
43
      stimulus_done = 0;
44
 
45
 
46
      // Addressing mode: Rn
47
      @(r15==16'h1000);
48
      if (r4     !==16'h2475) tb_error("====== SWPB (Rn mode): test 1 (result) =====");
49
      if (r5     !==16'h0102) tb_error("====== SWPB (Rn mode): test 1 (C flag) =====");
50
 
51
      if (r6     !==16'hb61c) tb_error("====== SWPB (Rn mode): test 2 (result) =====");
52
      if (r7     !==16'h0005) tb_error("====== SWPB (Rn mode): test 2 (C flag) =====");
53
 
54
 
55
      // Addressing mode: @Rn
56
      @(r15==16'h2000);
57 111 olivier.gi
      if (mem200 !==16'h2475)             tb_error("====== SWPB (@Rn mode): test 1 (result)  =====");
58
      if (r4     !==(`PER_SIZE+16'h0000)) tb_error("====== SWPB (@Rn mode): test 1 (address) =====");
59
      if (r5     !==16'h0102)             tb_error("====== SWPB (@Rn mode): test 1 (C flag)  =====");
60 2 olivier.gi
 
61 111 olivier.gi
      if (mem202 !==16'hb61c)             tb_error("====== SWPB (@Rn mode): test 2 (result)  =====");
62
      if (r6     !==(`PER_SIZE+16'h0002)) tb_error("====== SWPB (@Rn mode): test 2 (address) =====");
63
      if (r7     !==16'h0005)             tb_error("====== SWPB (@Rn mode): test 2 (C flag)  =====");
64 2 olivier.gi
 
65
 
66
      // Addressing mode: @Rn+
67
      @(r15==16'h3000);
68 111 olivier.gi
      if (mem208 !==16'h2475)             tb_error("====== SWPB (@Rn+ mode): test 1 (result)  =====");
69
      if (r4     !==(`PER_SIZE+16'h000A)) tb_error("====== SWPB (@Rn+ mode): test 1 (address) =====");
70
      if (r5     !==16'h0102)             tb_error("====== SWPB (@Rn+ mode): test 1 (C flag)  =====");
71 2 olivier.gi
 
72 111 olivier.gi
      if (mem20A !==16'hb61c)             tb_error("====== SWPB (@Rn+ mode): test 2 (result)  =====");
73
      if (r6     !==(`PER_SIZE+16'h000C)) tb_error("====== SWPB (@Rn+ mode): test 2 (address) =====");
74
      if (r7     !==16'h0005)             tb_error("====== SWPB (@Rn+ mode): test 2 (C flag)  =====");
75 2 olivier.gi
 
76
 
77
      // Addressing mode: X(Rn)
78
      @(r15==16'h4000);
79
      if (mem210 !==16'h2475) tb_error("====== SWPB (X(Rn) mode): test 1 (result)  =====");
80
      if (r5     !==16'h0102) tb_error("====== SWPB (X(Rn) mode): test 1 (C flag)  =====");
81
 
82
      if (mem212 !==16'hb61c) tb_error("====== SWPB (X(Rn) mode): test 2 (result)  =====");
83
      if (r7     !==16'h0005) tb_error("====== SWPB (X(Rn) mode): test 2 (C flag)  =====");
84
 
85
 
86
      // Addressing mode: EDE
87
      @(r15==16'h5000);
88
      if (mem218 !==16'h2475) tb_error("====== SWPB (EDE mode): test 1 (result)  =====");
89
      if (r5     !==16'h0102) tb_error("====== SWPB (EDE mode): test 1 (C flag)  =====");
90
 
91
      if (mem21A !==16'hb61c) tb_error("====== SWPB (EDE mode): test 2 (result)  =====");
92
      if (r7     !==16'h0005) tb_error("====== SWPB (EDE mode): test 2 (C flag)  =====");
93
 
94
 
95
      // Addressing mode: &EDE
96
      @(r15==16'h6000);
97
      if (mem220 !==16'h2475) tb_error("====== SWPB (&EDE mode): test 1 (result)  =====");
98
      if (r5     !==16'h0102) tb_error("====== SWPB (&EDE mode): test 1 (C flag)  =====");
99
 
100
      if (mem222 !==16'hb61c) tb_error("====== SWPB (&EDE mode): test 2 (result)  =====");
101
      if (r7     !==16'h0005) tb_error("====== SWPB (&EDE mode): test 2 (C flag)  =====");
102
 
103
 
104
      stimulus_done = 1;
105
   end
106
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.