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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: SXT  INSTRUCTION               */
/*---------------------------------------------------------------------------*/
/* Test the SXT  instruction.                                                */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/*===========================================================================*/
 
.set    DMEM_BASE, (__data_start     )
.set    DMEM_200,  (__data_start+0x00)
.set    DMEM_202,  (__data_start+0x02)
.set    DMEM_204,  (__data_start+0x04)
.set    DMEM_206,  (__data_start+0x06)
.set    DMEM_208,  (__data_start+0x08)
.set    DMEM_209,  (__data_start+0x09)
.set    DMEM_20A,  (__data_start+0x0A)
.set    DMEM_20B,  (__data_start+0x0B)
.set    DMEM_20C,  (__data_start+0x0C)
.set    DMEM_20D,  (__data_start+0x0D)
.set    DMEM_20E,  (__data_start+0x0E)
.set    DMEM_20F,  (__data_start+0x0F)
.set    DMEM_210,  (__data_start+0x10)
.set    DMEM_212,  (__data_start+0x12)
.set    DMEM_214,  (__data_start+0x14)
.set    DMEM_216,  (__data_start+0x16)
.set    DMEM_218,  (__data_start+0x18)
.set    DMEM_219,  (__data_start+0x19)
.set    DMEM_21A,  (__data_start+0x1A)
.set    DMEM_21B,  (__data_start+0x1B)
.set    DMEM_21C,  (__data_start+0x1C)
.set    DMEM_21D,  (__data_start+0x1D)
.set    DMEM_21E,  (__data_start+0x1E)
.set    DMEM_21F,  (__data_start+0x1F)
.set    DMEM_220,  (__data_start+0x20)
.set    DMEM_222,  (__data_start+0x22)
.set    DMEM_224,  (__data_start+0x24)
 
.global main
 
main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
 
 
        # Addressing mode: Rn
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, r4
        sxt          r4            ;# SXT (r4=0x7524  =>  r4=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, r6
        sxt          r6            ;# SXT (r6=0x1cb6  =>  r6=0xffb6)
        mov          r2, r7
 
        mov     #0x1000, r15
 
 
        # Addressing mode: @Rn
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_200
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_202
        sxt         @r4            ;# SXT (mem00=0x7524  => {mem00=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_202
        mov   #DMEM_202, r6
        mov     #0xaaaa, &DMEM_204
        sxt         @r6            ;# SXT (mem01=0x1cb6  => {mem01=0xffb6)
        mov          r2, r7
 
        mov     #0x2000, r15
 
 
        # Addressing mode: @Rn+
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_208
        mov   #DMEM_208, r4
        mov     #0xaaaa, &DMEM_20A
        sxt        @r4+            ;# SXT (mem04=0x7524  => {mem04=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_20A
        mov   #DMEM_20A, r6
        mov     #0xaaaa, &DMEM_20C
        sxt        @r6+            ;# SXT (mem05=0x1cb6  => {mem05=0xffb6)
        mov          r2, r7
 
        mov     #0x3000, r15
 
 
        # Addressing mode: X(Rn)
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_210
        mov   #DMEM_200, r4
        mov     #0xaaaa, &DMEM_212
        sxt       16(r4)            ;# SXT (mem08=0x7524  => {mem08=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_212
        mov   #DMEM_200, r6
        mov     #0xaaaa, &DMEM_214
        sxt       18(r6)            ;# SXT (mem09=0x1cb6  => {mem09=0xffb6)
        mov          r2, r7
 
        mov     #0x4000, r15
 
 
        # Addressing mode: EDE
        #------------------------
.set   EDE_218,  DMEM_218
.set   EDE_21A,  DMEM_21A
.set   EDE_21C,  DMEM_21C
.set   EDE_21E,  DMEM_21E
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_218
        mov     #0xaaaa, &DMEM_21A
        sxt     EDE_218            ;# SXT (mem0c=0x7524  => {mem0c=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_21A
        mov     #0xaaaa, &DMEM_21C
        sxt     EDE_21A            ;# SXT (mem0d=0x1cb6  => {mem0d=0xffb6)
        mov          r2, r7
 
        mov     #0x5000, r15
 
 
        # Addressing mode: &EDE
        #------------------------
.set   aEDE_220,  DMEM_220
.set   aEDE_222,  DMEM_222
.set   aEDE_224,  DMEM_224
.set   aEDE_226,  DMEM_226
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &DMEM_220
        mov     #0xaaaa, &DMEM_222
        sxt   &aEDE_220            ;# SXT (mem10=0x7524  => {mem10=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &DMEM_222
        mov     #0xaaaa, &DMEM_224
        sxt   &aEDE_222            ;# SXT (mem11=0x1cb6  => {mem11=0xffb6)
        mov          r2, r7
 
        mov     #0x6000, r15
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24	18	olivier.gi	`/* SINGLE-OPERAND ARITHMETIC: SXT INSTRUCTION */`
25	2	olivier.gi	`/---------------------------------------------------------------------------/`
26	18	olivier.gi	`/* Test the SXT instruction. */`
27			`/* */`
28			`/* Author(s): */`
29			`/* - Olivier Girard, olgirard@gmail.com */`
30			`/* */`
31			`/---------------------------------------------------------------------------/`
32	19	olivier.gi	`/* $Rev: 111 $ */`
33			`/* $LastChangedBy: olivier.girard $ */`
34			`/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */`
35	2	olivier.gi	`/===========================================================================/`
36
37	111	olivier.gi	`.set DMEM_BASE, (__data_start )`
38			`.set DMEM_200, (__data_start+0x00)`
39			`.set DMEM_202, (__data_start+0x02)`
40			`.set DMEM_204, (__data_start+0x04)`
41			`.set DMEM_206, (__data_start+0x06)`
42			`.set DMEM_208, (__data_start+0x08)`
43			`.set DMEM_209, (__data_start+0x09)`
44			`.set DMEM_20A, (__data_start+0x0A)`
45			`.set DMEM_20B, (__data_start+0x0B)`
46			`.set DMEM_20C, (__data_start+0x0C)`
47			`.set DMEM_20D, (__data_start+0x0D)`
48			`.set DMEM_20E, (__data_start+0x0E)`
49			`.set DMEM_20F, (__data_start+0x0F)`
50			`.set DMEM_210, (__data_start+0x10)`
51			`.set DMEM_212, (__data_start+0x12)`
52			`.set DMEM_214, (__data_start+0x14)`
53			`.set DMEM_216, (__data_start+0x16)`
54			`.set DMEM_218, (__data_start+0x18)`
55			`.set DMEM_219, (__data_start+0x19)`
56			`.set DMEM_21A, (__data_start+0x1A)`
57			`.set DMEM_21B, (__data_start+0x1B)`
58			`.set DMEM_21C, (__data_start+0x1C)`
59			`.set DMEM_21D, (__data_start+0x1D)`
60			`.set DMEM_21E, (__data_start+0x1E)`
61			`.set DMEM_21F, (__data_start+0x1F)`
62			`.set DMEM_220, (__data_start+0x20)`
63			`.set DMEM_222, (__data_start+0x22)`
64			`.set DMEM_224, (__data_start+0x24)`
65	2	olivier.gi
66			`.global main`
67
68			`main:`
69			`/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */`
70
71
72			`# Addressing mode: Rn`
73			`#------------------------`
74
75			`mov #0x0100, r2 ;# Test 1`
76			`mov #0x7524, r4`
77			`sxt r4 ;# SXT (r4=0x7524 => r4=0x0024)`
78			`mov r2, r5`
79
80			`mov #0x0100, r2 ;# Test 2`
81			`mov #0x1cb6, r6`
82			`sxt r6 ;# SXT (r6=0x1cb6 => r6=0xffb6)`
83			`mov r2, r7`
84
85			`mov #0x1000, r15`
86
87
88			`# Addressing mode: @Rn`
89			`#------------------------`
90
91			`mov #0x0100, r2 ;# Test 1`
92	111	olivier.gi	`mov #0x7524, &DMEM_200`
93			`mov #DMEM_200, r4`
94			`mov #0xaaaa, &DMEM_202`
95	2	olivier.gi	`sxt @r4 ;# SXT (mem00=0x7524 => {mem00=0x0024)`
96			`mov r2, r5`
97
98			`mov #0x0100, r2 ;# Test 2`
99	111	olivier.gi	`mov #0x1cb6, &DMEM_202`
100			`mov #DMEM_202, r6`
101			`mov #0xaaaa, &DMEM_204`
102	2	olivier.gi	`sxt @r6 ;# SXT (mem01=0x1cb6 => {mem01=0xffb6)`
103			`mov r2, r7`
104
105			`mov #0x2000, r15`
106
107
108			`# Addressing mode: @Rn+`
109			`#------------------------`
110
111			`mov #0x0100, r2 ;# Test 1`
112	111	olivier.gi	`mov #0x7524, &DMEM_208`
113			`mov #DMEM_208, r4`
114			`mov #0xaaaa, &DMEM_20A`
115	2	olivier.gi	`sxt @r4+ ;# SXT (mem04=0x7524 => {mem04=0x0024)`
116			`mov r2, r5`
117
118			`mov #0x0100, r2 ;# Test 2`
119	111	olivier.gi	`mov #0x1cb6, &DMEM_20A`
120			`mov #DMEM_20A, r6`
121			`mov #0xaaaa, &DMEM_20C`
122	2	olivier.gi	`sxt @r6+ ;# SXT (mem05=0x1cb6 => {mem05=0xffb6)`
123			`mov r2, r7`
124
125			`mov #0x3000, r15`
126
127
128			`# Addressing mode: X(Rn)`
129			`#------------------------`
130
131			`mov #0x0100, r2 ;# Test 1`
132	111	olivier.gi	`mov #0x7524, &DMEM_210`
133			`mov #DMEM_200, r4`
134			`mov #0xaaaa, &DMEM_212`
135	2	olivier.gi	`sxt 16(r4) ;# SXT (mem08=0x7524 => {mem08=0x0024)`
136			`mov r2, r5`
137
138			`mov #0x0100, r2 ;# Test 2`
139	111	olivier.gi	`mov #0x1cb6, &DMEM_212`
140			`mov #DMEM_200, r6`
141			`mov #0xaaaa, &DMEM_214`
142	2	olivier.gi	`sxt 18(r6) ;# SXT (mem09=0x1cb6 => {mem09=0xffb6)`
143			`mov r2, r7`
144
145			`mov #0x4000, r15`
146
147
148			`# Addressing mode: EDE`
149			`#------------------------`
150	111	olivier.gi	`.set EDE_218, DMEM_218`
151			`.set EDE_21A, DMEM_21A`
152			`.set EDE_21C, DMEM_21C`
153			`.set EDE_21E, DMEM_21E`
154	2	olivier.gi
155			`mov #0x0100, r2 ;# Test 1`
156	111	olivier.gi	`mov #0x7524, &DMEM_218`
157			`mov #0xaaaa, &DMEM_21A`
158	2	olivier.gi	`sxt EDE_218 ;# SXT (mem0c=0x7524 => {mem0c=0x0024)`
159			`mov r2, r5`
160
161			`mov #0x0100, r2 ;# Test 2`
162	111	olivier.gi	`mov #0x1cb6, &DMEM_21A`
163			`mov #0xaaaa, &DMEM_21C`
164	2	olivier.gi	`sxt EDE_21A ;# SXT (mem0d=0x1cb6 => {mem0d=0xffb6)`
165			`mov r2, r7`
166
167			`mov #0x5000, r15`
168
169
170			`# Addressing mode: &EDE`
171			`#------------------------`
172	111	olivier.gi	`.set aEDE_220, DMEM_220`
173			`.set aEDE_222, DMEM_222`
174			`.set aEDE_224, DMEM_224`
175			`.set aEDE_226, DMEM_226`
176	2	olivier.gi
177			`mov #0x0100, r2 ;# Test 1`
178	111	olivier.gi	`mov #0x7524, &DMEM_220`
179			`mov #0xaaaa, &DMEM_222`
180	2	olivier.gi	`sxt &aEDE_220 ;# SXT (mem10=0x7524 => {mem10=0x0024)`
181			`mov r2, r5`
182
183			`mov #0x0100, r2 ;# Test 2`
184	111	olivier.gi	`mov #0x1cb6, &DMEM_222`
185			`mov #0xaaaa, &DMEM_224`
186	2	olivier.gi	`sxt &aEDE_222 ;# SXT (mem11=0x1cb6 => {mem11=0xffb6)`
187			`mov r2, r7`
188
189			`mov #0x6000, r15`
190
191
192			`/* ---------------------- END OF TEST --------------- */`
193			`end_of_test:`
194			`nop`
195			`br #0xffff`
196
197
198			`/* ---------------------- INTERRUPT VECTORS --------------- */`
199
200			`.section .vectors, "a"`
201			`.word end_of_test ; Interrupt 0 (lowest priority)`
202			`.word end_of_test ; Interrupt 1`
203			`.word end_of_test ; Interrupt 2`
204			`.word end_of_test ; Interrupt 3`
205			`.word end_of_test ; Interrupt 4`
206			`.word end_of_test ; Interrupt 5`
207			`.word end_of_test ; Interrupt 6`
208			`.word end_of_test ; Interrupt 7`
209			`.word end_of_test ; Interrupt 8`
210			`.word end_of_test ; Interrupt 9`
211			`.word end_of_test ; Interrupt 10 Watchdog timer`
212			`.word end_of_test ; Interrupt 11`
213			`.word end_of_test ; Interrupt 12`
214			`.word end_of_test ; Interrupt 13`
215			`.word end_of_test ; Interrupt 14 NMI`
216			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_sxt.s43] - Blame information for rev 111