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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                 SINGLE-OPERAND ARITHMETIC: SXT  INSTRUCTION              */
/*---------------------------------------------------------------------------*/
/* Test the SXT  instruction.                                               */
/*===========================================================================*/
 
 
.global main
 
main:
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
 
 
        # Addressing mode: Rn
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, r4
        sxt          r4            ;# SXT (r4=0x7524  =>  r4=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, r6
        sxt          r6            ;# SXT (r6=0x1cb6  =>  r6=0xffb6)
        mov          r2, r7
 
        mov     #0x1000, r15
 
 
        # Addressing mode: @Rn
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &0x0200
        mov     #0x0200, r4
        mov     #0xaaaa, &0x0202
        sxt         @r4            ;# SXT (mem00=0x7524  => {mem00=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &0x0202
        mov     #0x0202, r6
        mov     #0xaaaa, &0x0204
        sxt         @r6            ;# SXT (mem01=0x1cb6  => {mem01=0xffb6)
        mov          r2, r7
 
        mov     #0x2000, r15
 
 
        # Addressing mode: @Rn+
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &0x0208
        mov     #0x0208, r4
        mov     #0xaaaa, &0x020A
        sxt        @r4+            ;# SXT (mem04=0x7524  => {mem04=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &0x020A
        mov     #0x020A, r6
        mov     #0xaaaa, &0x020C
        sxt        @r6+            ;# SXT (mem05=0x1cb6  => {mem05=0xffb6)
        mov          r2, r7
 
        mov     #0x3000, r15
 
 
        # Addressing mode: X(Rn)
        #------------------------
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &0x0210
        mov     #0x0200, r4
        mov     #0xaaaa, &0x0212
        sxt       16(r4)            ;# SXT (mem08=0x7524  => {mem08=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &0x0212
        mov     #0x0200, r6
        mov     #0xaaaa, &0x0214
        sxt       18(r6)            ;# SXT (mem09=0x1cb6  => {mem09=0xffb6)
        mov          r2, r7
 
        mov     #0x4000, r15
 
 
        # Addressing mode: EDE
        #------------------------
.set   EDE_218,  (__data_start+0x0018)
.set   EDE_21A,  (__data_start+0x001A)
.set   EDE_21C,  (__data_start+0x001C)
.set   EDE_21E,  (__data_start+0x001E)
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &0x0218
        mov     #0xaaaa, &0x021A
        sxt     EDE_218            ;# SXT (mem0c=0x7524  => {mem0c=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &0x021A
        mov     #0xaaaa, &0x021C
        sxt     EDE_21A            ;# SXT (mem0d=0x1cb6  => {mem0d=0xffb6)
        mov          r2, r7
 
        mov     #0x5000, r15
 
 
        # Addressing mode: &EDE
        #------------------------
.set   aEDE_220,  0x0220
.set   aEDE_222,  0x0222
.set   aEDE_224,  0x0224
.set   aEDE_226,  0x0226
 
        mov     #0x0100, r2        ;# Test 1
        mov     #0x7524, &0x0220
        mov     #0xaaaa, &0x0222
        sxt   &aEDE_220            ;# SXT (mem10=0x7524  => {mem10=0x0024)
        mov          r2, r5
 
        mov     #0x0100, r2        ;# Test 2
        mov     #0x1cb6, &0x0222
        mov     #0xaaaa, &0x0224
        sxt   &aEDE_222            ;# SXT (mem11=0x1cb6  => {mem11=0xffb6)
        mov          r2, r7
 
        mov     #0x6000, r15
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* SINGLE-OPERAND ARITHMETIC: SXT INSTRUCTION */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the SXT instruction. */`
27			`/===========================================================================/`
28
29
30			`.global main`
31
32			`main:`
33			`/* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */`
34
35
36			`# Addressing mode: Rn`
37			`#------------------------`
38
39			`mov #0x0100, r2 ;# Test 1`
40			`mov #0x7524, r4`
41			`sxt r4 ;# SXT (r4=0x7524 => r4=0x0024)`
42			`mov r2, r5`
43
44			`mov #0x0100, r2 ;# Test 2`
45			`mov #0x1cb6, r6`
46			`sxt r6 ;# SXT (r6=0x1cb6 => r6=0xffb6)`
47			`mov r2, r7`
48
49			`mov #0x1000, r15`
50
51
52			`# Addressing mode: @Rn`
53			`#------------------------`
54
55			`mov #0x0100, r2 ;# Test 1`
56			`mov #0x7524, &0x0200`
57			`mov #0x0200, r4`
58			`mov #0xaaaa, &0x0202`
59			`sxt @r4 ;# SXT (mem00=0x7524 => {mem00=0x0024)`
60			`mov r2, r5`
61
62			`mov #0x0100, r2 ;# Test 2`
63			`mov #0x1cb6, &0x0202`
64			`mov #0x0202, r6`
65			`mov #0xaaaa, &0x0204`
66			`sxt @r6 ;# SXT (mem01=0x1cb6 => {mem01=0xffb6)`
67			`mov r2, r7`
68
69			`mov #0x2000, r15`
70
71
72			`# Addressing mode: @Rn+`
73			`#------------------------`
74
75			`mov #0x0100, r2 ;# Test 1`
76			`mov #0x7524, &0x0208`
77			`mov #0x0208, r4`
78			`mov #0xaaaa, &0x020A`
79			`sxt @r4+ ;# SXT (mem04=0x7524 => {mem04=0x0024)`
80			`mov r2, r5`
81
82			`mov #0x0100, r2 ;# Test 2`
83			`mov #0x1cb6, &0x020A`
84			`mov #0x020A, r6`
85			`mov #0xaaaa, &0x020C`
86			`sxt @r6+ ;# SXT (mem05=0x1cb6 => {mem05=0xffb6)`
87			`mov r2, r7`
88
89			`mov #0x3000, r15`
90
91
92			`# Addressing mode: X(Rn)`
93			`#------------------------`
94
95			`mov #0x0100, r2 ;# Test 1`
96			`mov #0x7524, &0x0210`
97			`mov #0x0200, r4`
98			`mov #0xaaaa, &0x0212`
99			`sxt 16(r4) ;# SXT (mem08=0x7524 => {mem08=0x0024)`
100			`mov r2, r5`
101
102			`mov #0x0100, r2 ;# Test 2`
103			`mov #0x1cb6, &0x0212`
104			`mov #0x0200, r6`
105			`mov #0xaaaa, &0x0214`
106			`sxt 18(r6) ;# SXT (mem09=0x1cb6 => {mem09=0xffb6)`
107			`mov r2, r7`
108
109			`mov #0x4000, r15`
110
111
112			`# Addressing mode: EDE`
113			`#------------------------`
114			`.set EDE_218, (__data_start+0x0018)`
115			`.set EDE_21A, (__data_start+0x001A)`
116			`.set EDE_21C, (__data_start+0x001C)`
117			`.set EDE_21E, (__data_start+0x001E)`
118
119			`mov #0x0100, r2 ;# Test 1`
120			`mov #0x7524, &0x0218`
121			`mov #0xaaaa, &0x021A`
122			`sxt EDE_218 ;# SXT (mem0c=0x7524 => {mem0c=0x0024)`
123			`mov r2, r5`
124
125			`mov #0x0100, r2 ;# Test 2`
126			`mov #0x1cb6, &0x021A`
127			`mov #0xaaaa, &0x021C`
128			`sxt EDE_21A ;# SXT (mem0d=0x1cb6 => {mem0d=0xffb6)`
129			`mov r2, r7`
130
131			`mov #0x5000, r15`
132
133
134			`# Addressing mode: &EDE`
135			`#------------------------`
136			`.set aEDE_220, 0x0220`
137			`.set aEDE_222, 0x0222`
138			`.set aEDE_224, 0x0224`
139			`.set aEDE_226, 0x0226`
140
141			`mov #0x0100, r2 ;# Test 1`
142			`mov #0x7524, &0x0220`
143			`mov #0xaaaa, &0x0222`
144			`sxt &aEDE_220 ;# SXT (mem10=0x7524 => {mem10=0x0024)`
145			`mov r2, r5`
146
147			`mov #0x0100, r2 ;# Test 2`
148			`mov #0x1cb6, &0x0222`
149			`mov #0xaaaa, &0x0224`
150			`sxt &aEDE_222 ;# SXT (mem11=0x1cb6 => {mem11=0xffb6)`
151			`mov r2, r7`
152
153			`mov #0x6000, r15`
154
155
156			`/* ---------------------- END OF TEST --------------- */`
157			`end_of_test:`
158			`nop`
159			`br #0xffff`
160
161
162			`/* ---------------------- INTERRUPT VECTORS --------------- */`
163
164			`.section .vectors, "a"`
165			`.word end_of_test ; Interrupt 0 (lowest priority)`
166			`.word end_of_test ; Interrupt 1`
167			`.word end_of_test ; Interrupt 2`
168			`.word end_of_test ; Interrupt 3`
169			`.word end_of_test ; Interrupt 4`
170			`.word end_of_test ; Interrupt 5`
171			`.word end_of_test ; Interrupt 6`
172			`.word end_of_test ; Interrupt 7`
173			`.word end_of_test ; Interrupt 8`
174			`.word end_of_test ; Interrupt 9`
175			`.word end_of_test ; Interrupt 10 Watchdog timer`
176			`.word end_of_test ; Interrupt 11`
177			`.word end_of_test ; Interrupt 12`
178			`.word end_of_test ; Interrupt 13`
179			`.word end_of_test ; Interrupt 14 NMI`
180			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [sing-op_sxt.s43] - Blame information for rev 2