OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [submit.prj] - Blame information for rev 134

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 134 olivier.gi 
 
2 
verilog work ../../../bench/verilog/tb_openMSP430.v
3 
verilog work ../../../bench/verilog/ram.v
4 
verilog work ../../../bench/verilog/msp_debug.v
5 
 
6 
verilog work ../../../rtl/verilog/openMSP430_defines.v
7 
verilog work ../../../rtl/verilog/openMSP430.v
8 
verilog work ../../../rtl/verilog/omsp_frontend.v
9 
verilog work ../../../rtl/verilog/omsp_execution_unit.v
10 
verilog work ../../../rtl/verilog/omsp_register_file.v
11 
verilog work ../../../rtl/verilog/omsp_alu.v
12 
verilog work ../../../rtl/verilog/omsp_sfr.v
13 
verilog work ../../../rtl/verilog/omsp_clock_module.v
14 
verilog work ../../../rtl/verilog/omsp_mem_backbone.v
15 
verilog work ../../../rtl/verilog/omsp_watchdog.v
16 
verilog work ../../../rtl/verilog/omsp_dbg.v
17 
verilog work ../../../rtl/verilog/omsp_dbg_uart.v
18 
verilog work ../../../rtl/verilog/omsp_dbg_hwbrk.v
19 
verilog work ../../../rtl/verilog/omsp_multiplier.v
20 
verilog work ../../../rtl/verilog/omsp_sync_reset.v
21 
verilog work ../../../rtl/verilog/omsp_sync_cell.v
22 
verilog work ../../../rtl/verilog/omsp_scan_mux.v
23 
verilog work ../../../rtl/verilog/omsp_and_gate.v
24 
verilog work ../../../rtl/verilog/omsp_wakeup_cell.v
25 
verilog work ../../../rtl/verilog/omsp_clock_gate.v
26 
verilog work ../../../rtl/verilog/omsp_clock_mux.v
27 
 
28 
verilog work ../../../rtl/verilog/periph/omsp_gpio.v
29 
verilog work ../../../rtl/verilog/periph/omsp_timerA.v
30 
verilog work ../../../rtl/verilog/periph/template_periph_8b.v
31 
verilog work ../../../rtl/verilog/periph/template_periph_16b.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.