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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_clkmux.v] - Blame information for rev 18

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Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                                  TIMER A                                  */
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/*---------------------------------------------------------------------------*/
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/* Test the timer A:                                                         */
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/*                        - Check the timer clock input mux.                 */
28 18 olivier.gi
/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 17 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $          */
36 2 olivier.gi
/*===========================================================================*/
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integer my_counter;
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always @ (negedge mclk)
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  my_counter <=  my_counter+1;
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wire [15:0] tar = timerA_0.tar;
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// Generate TACLK as MCLK/3
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integer taclk_cnt;
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always @ (posedge mclk or posedge puc)
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  if (puc)               taclk_cnt <=  0;
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  else if (taclk_cnt==2) taclk_cnt <=  0;
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  else                   taclk_cnt <=  taclk_cnt+1;
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always @ (taclk_cnt)
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  if (taclk_cnt==2) taclk = 1'b1;
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  else              taclk = 1'b0;
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// Generate INCLK as MCLK/5
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integer inclk_cnt;
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always @ (posedge mclk or posedge puc)
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  if (puc)               inclk_cnt <=  0;
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  else if (inclk_cnt==4) inclk_cnt <=  0;
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  else                   inclk_cnt <=  inclk_cnt+1;
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always @ (inclk_cnt)
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  if (inclk_cnt==4) inclk = 1'b1;
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  else              inclk = 1'b0;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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      // TIMER A TEST:  INPUT MUX - TACLK
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      //--------------------------------------------------------
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//      @(r15 === 16'h0000);
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      @(r15 === 16'h0001);
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      @(tar === 1);
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      my_counter = 0;
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      repeat(300) @(posedge mclk);
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      if (tar !== 16'h0032) tb_error("====== TIMER A TEST:  INPUT MUX - TACLK =====");
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      // TIMER A TEST:  INPUT MUX - ACLK
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      //--------------------------------------------------------
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      @(r15 === 16'h1000);
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      @(r15 === 16'h1001);
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      @(tar === 1);
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      my_counter = 0;
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      repeat(300) @(posedge mclk);
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      if (tar !== 16'h0005) tb_error("====== TIMER A TEST:  INPUT MUX - ACLK =====");
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      // TIMER A TEST:  INPUT MUX - SMCLK
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      //--------------------------------------------------------
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      @(r15 === 16'h2000);
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      @(r15 === 16'h2001);
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      @(tar === 1);
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      my_counter = 0;
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      repeat(300) @(posedge mclk);
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      if (tar !== 16'h0013) tb_error("====== TIMER A TEST:  INPUT MUX - SMCLK =====");
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      // TIMER A TEST:  INPUT MUX - INCLK
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      //--------------------------------------------------------
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      @(r15 === 16'h3000);
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      @(r15 === 16'h3001);
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      @(tar === 1);
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      my_counter = 0;
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      repeat(300) @(posedge mclk);
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      if (tar !== 16'h001E) tb_error("====== TIMER A TEST:  INPUT MUX - INCLK =====");
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      stimulus_done = 1;
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   end
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