OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_compare.v] - Blame information for rev 19

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                                  TIMER A                                  */
25
/*---------------------------------------------------------------------------*/
26
/* Test the timer A:                                                         */
27
/*                        - Check the timer compare features.                */
28 18 olivier.gi
/*                                                                           */
29
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32
/*---------------------------------------------------------------------------*/
33 19 olivier.gi
/* $Rev: 19 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
36 2 olivier.gi
/*===========================================================================*/
37
 
38
integer my_counter;
39
always @ (posedge mclk)
40
  my_counter <=  my_counter+1;
41
 
42
 
43
initial
44
   begin
45
      $display(" ===============================================");
46
      $display("|                 START SIMULATION              |");
47
      $display(" ===============================================");
48
      repeat(5) @(posedge mclk);
49
      stimulus_done = 0;
50
 
51
      // TIMER A TEST:  UP MODE
52
      //--------------------------------------------------------
53
 
54
      @(mem200 === 16'h0001);  // Check Comparator 0
55
      @(posedge ta_out0);
56
      @(negedge mclk);
57
      my_counter = 0;
58
      @(posedge irq_ta1);
59
      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
60
 
61
      @(negedge ta_out0);
62
      @(negedge mclk);
63
      my_counter = 0;
64
      @(posedge irq_ta1);
65
      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
66
      @(posedge ta_out0);
67
      if (my_counter !== 32'h2C) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
68
 
69
      @(posedge irq_ta0);
70
      @(negedge mclk);
71
      my_counter = 0;
72
      @(posedge irq_ta1);
73
      if (my_counter !== 32'h2) tb_error("====== TIMER_A COMPARE 0: UP MODE =====");
74
 
75
 
76
      @(mem200 === 16'h0002);  // Check Comparator 1
77
      @(posedge ta_out1);
78
      @(negedge mclk);
79
      my_counter = 0;
80
      @(posedge ta_out0);
81
      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
82
 
83
      @(negedge ta_out1);
84
      @(negedge mclk);
85
      my_counter = 0;
86
      @(negedge ta_out0);
87
      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
88
 
89
      @(posedge irq_ta1);
90
      @(negedge mclk);
91
      my_counter = 0;
92
      @(posedge ta_out0);
93
      if (my_counter !== 32'h20) tb_error("====== TIMER_A COMPARE 1: UP MODE =====");
94
 
95
 
96
      @(mem200 === 16'h0003);  // Check Comparator 2
97
      @(posedge ta_out2);
98
      @(negedge mclk);
99
      my_counter = 0;
100
      @(posedge ta_out0);
101
      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
102
 
103
      @(negedge ta_out2);
104
      @(negedge mclk);
105
      my_counter = 0;
106
      @(negedge ta_out0);
107
      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
108
 
109
      @(posedge irq_ta1);
110
      @(negedge mclk);
111
      my_counter = 0;
112
      @(posedge ta_out0);
113
      if (my_counter !== 32'h12) tb_error("====== TIMER_A COMPARE 2: UP MODE =====");
114
 
115
 
116
      // TIMER A TEST:  CONTINUOUS MODE
117
      //--------------------------------------------------------
118
 
119
      @(mem200 === 16'h0001);
120
      @(posedge irq_ta1);
121
      @(negedge mclk);
122
      my_counter = 0;
123
      @(negedge irq_ta1);
124
      repeat(10) @(negedge mclk);
125
      if (mem206 !== 16'h000A) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 1 =====");
126
 
127
      @(posedge ta_out0);
128
      if (my_counter !== 32'h60) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 1 =====");
129
 
130
      @(posedge ta_out1);
131
      if (my_counter !== 32'hC0) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
132
      @(negedge irq_ta1);
133
      repeat(10) @(negedge mclk);
134
      if (mem206 !== 16'h0002) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
135
 
136
      @(posedge ta_out2);
137
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
138
      @(negedge irq_ta1);
139
      repeat(10) @(negedge mclk);
140
      if (mem206 !== 16'h0004) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
141
 
142
 
143
      @(mem200 === 16'h0002);
144
      @(posedge irq_ta1);
145
      @(negedge mclk);
146
      my_counter = 0;
147
      @(negedge irq_ta1);
148
      repeat(10) @(negedge mclk);
149
      if (mem206 !== 16'h000A) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 2 =====");
150
 
151
      @(posedge irq_ta0);
152
      if (my_counter !== 32'h60) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 2 =====");
153
 
154
      @(posedge irq_ta1);
155
      if (my_counter !== 32'hC0) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
156
      @(negedge irq_ta1);
157
      repeat(10) @(negedge mclk);
158
      if (mem206 !== 16'h0002) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
159
 
160
      @(posedge irq_ta1);
161
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
162
      @(negedge irq_ta1);
163
      repeat(10) @(negedge mclk);
164
      if (mem206 !== 16'h0004) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
165
 
166
 
167
 
168
      // TIMER A TEST:  UP-DOWN MODE
169
      //--------------------------------------------------------
170
 
171
      @(mem200 === 16'h0001);
172
      @(posedge irq_ta1);
173
      @(negedge mclk);
174
      my_counter = 0;
175
      @(posedge ta_out2);
176
      if (my_counter !== 32'h60)  tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 1 =====");
177
      @(posedge ta_out1);
178
      if (my_counter !== 32'hC0)  tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 1 =====");
179
      @(posedge ta_out0);
180
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 1 =====");
181
 
182
      @(negedge ta_out1);
183
      if (my_counter !== 32'h180) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 2 =====");
184
      @(negedge ta_out2);
185
      if (my_counter !== 32'h1E0) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 2 =====");
186
      @(negedge ta_out0);
187
      if (my_counter !== 32'h360) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 2 =====");
188
 
189
 
190
      @(mem200 === 16'h0002);
191
      @(posedge irq_ta1);
192
      @(negedge mclk);
193
      my_counter = 0;
194
      @(negedge irq_ta1);
195
      repeat(10) @(negedge mclk);
196
      if (mem206 !== 16'h000A)    tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 3 =====");
197
      @(posedge irq_ta1);
198
      if (my_counter !== 32'h60)  tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 3 =====");
199
      @(negedge irq_ta1);
200
      repeat(10) @(negedge mclk);
201
      if (mem206 !== 16'h0004)    tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 3 =====");
202
      @(posedge irq_ta1);
203
      if (my_counter !== 32'hC0)  tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 3 =====");
204
      @(negedge irq_ta1);
205
      repeat(10) @(negedge mclk);
206
      if (mem206 !== 16'h0002)    tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 3 =====");
207
      @(posedge irq_ta0);
208
      if (my_counter !== 32'h120) tb_error("====== TIMER_A COMPARE 0: CONTINUOUS MODE - TEST 3 =====");
209
 
210
      @(posedge irq_ta1);
211
      if (my_counter !== 32'h180) tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 4 =====");
212
      @(negedge irq_ta1);
213
      repeat(10) @(negedge mclk);
214
      if (mem206 !== 16'h0002)    tb_error("====== TIMER_A COMPARE 1: CONTINUOUS MODE - TEST 4 =====");
215
      @(posedge irq_ta1);
216
      if (my_counter !== 32'h1E0) tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 4 =====");
217
      @(negedge irq_ta1);
218
      repeat(10) @(negedge mclk);
219
      if (mem206 !== 16'h0004)    tb_error("====== TIMER_A COMPARE 2: CONTINUOUS MODE - TEST 4 =====");
220
      @(posedge irq_ta1);
221
      if (my_counter !== 32'h240) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
222
      @(negedge irq_ta1);
223
      repeat(10) @(negedge mclk);
224
      if (mem206 !== 16'h000A)    tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
225
      @(posedge irq_ta0);
226
      if (my_counter !== 32'h360) tb_error("====== TIMER_A COMPARE: CONTINUOUS MODE - TEST 4 =====");
227
 
228
 
229
      // TIMER A TEST:  CCI INPUT LATCHING (SCCI)
230
      //--------------------------------------------------------
231
 
232
      @(r15 === 16'h4000);
233
      if (mem202 !== 16'h3088) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
234
      if (mem204 !== 16'h3489) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
235
      if (mem206 !== 16'h2480) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
236
      if (mem208 !== 16'h2081) tb_error("====== TIMER_A COMPARE 0: CCI INPUT LATCHING (SCCI) =====");
237
 
238
      if (mem212 !== 16'h3088) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
239
      if (mem214 !== 16'h3489) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
240
      if (mem216 !== 16'h2480) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
241
      if (mem218 !== 16'h2081) tb_error("====== TIMER_A COMPARE 1: CCI INPUT LATCHING (SCCI) =====");
242
 
243
      if (mem222 !== 16'h3088) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
244
      if (mem224 !== 16'h3489) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
245
      if (mem226 !== 16'h2480) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
246
      if (mem228 !== 16'h2081) tb_error("====== TIMER_A COMPARE 2: CCI INPUT LATCHING (SCCI) =====");
247
 
248
      stimulus_done = 1;
249
   end
250
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.