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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_modes.v] - Blame information for rev 219

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Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
23
/*===========================================================================*/
24
/*                                  TIMER A                                  */
25
/*---------------------------------------------------------------------------*/
26
/* Test the timer A:                                                         */
27
/*                        - Check RD/WR register access.                     */
28
/*                        - Check the clock divider.                         */
29
/*                        - Check the timer modes.                           */
30 18 olivier.gi
/*                                                                           */
31
/* Author(s):                                                                */
32
/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
34
/*---------------------------------------------------------------------------*/
35 19 olivier.gi
/* $Rev: 202 $                                                                */
36
/* $LastChangedBy: olivier.girard $                                          */
37
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
38 2 olivier.gi
/*===========================================================================*/
39
 
40 111 olivier.gi
 
41
integer test_step;
42 2 olivier.gi
integer my_counter;
43
always @ (posedge mclk)
44
  my_counter <=  my_counter+1;
45
 
46
initial
47
   begin
48
      $display(" ===============================================");
49
      $display("|                 START SIMULATION              |");
50
      $display(" ===============================================");
51
      repeat(5) @(posedge mclk);
52
      stimulus_done = 0;
53 111 olivier.gi
      test_step     = 0;
54 202 olivier.gi
 
55 180 olivier.gi
`ifdef ASIC_CLOCKING
56 202 olivier.gi
      tb_skip_finish("|   (this test is not supported in ASIC mode)   |");
57 134 olivier.gi
`else
58
 
59 2 olivier.gi
      // TIMER A TEST:  RD/WR ACCESS
60
      //--------------------------------------------------------
61
 
62
      @(r15===16'h1000);
63
      if (mem200 !== 16'h02a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
64
      if (mem202 !== 16'h0151) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
65
      if (mem204 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
66
      if (mem206 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
67
 
68
      if (mem208 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
69
      if (mem20A !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
70
      if (mem20C !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
71
 
72
      if (mem210 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
73
      if (mem212 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
74
      if (mem214 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
75
 
76
      if (mem216 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
77
      if (mem218 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
78
      if (mem21A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
79
 
80
      if (mem220 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
81
      if (mem222 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
82
      if (mem224 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
83
 
84
      if (mem226 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
85
      if (mem228 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
86
      if (mem22A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
87
 
88
      if (mem230 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
89
      if (mem232 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
90
      if (mem234 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
91
 
92
      if (mem236 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
93
      if (mem238 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
94
      if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
95
 
96
      if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
97
      if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
98
      if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
99 111 olivier.gi
      test_step = 1;
100 202 olivier.gi
 
101 2 olivier.gi
      // TIMER A TEST:  INPUT DIVIDER
102
      //--------------------------------------------------------
103
 
104
      @(mem200 === 16'h0001);  // Check /1 divider
105
      @(posedge irq_ta1)
106
      @(negedge mclk)
107
        my_counter = 0;
108
      @(posedge irq_ta1)
109
        if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
110 111 olivier.gi
      test_step = 2;
111 2 olivier.gi
 
112
      @(mem200 === 16'h0002);  // Check /2 divider
113
      @(posedge irq_ta1)
114
      @(negedge mclk)
115
        my_counter = 0;
116
      @(posedge irq_ta1)
117
        if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
118 111 olivier.gi
      test_step = 3;
119 2 olivier.gi
 
120
      @(mem200 === 16'h0003);  // Check /4 divider
121
      @(posedge irq_ta1)
122
      @(negedge mclk)
123
        my_counter = 0;
124
      @(posedge irq_ta1)
125
        if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
126 111 olivier.gi
      test_step = 4;
127 2 olivier.gi
 
128
      @(mem200 === 16'h0004);  // Check /8 divider
129
      @(posedge irq_ta1)
130
      @(negedge mclk)
131
        my_counter = 0;
132
      @(posedge irq_ta1)
133
        if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
134 111 olivier.gi
      test_step = 5;
135 2 olivier.gi
 
136
      @(r15===16'h2000);
137 111 olivier.gi
      test_step = 6;
138 2 olivier.gi
 
139 202 olivier.gi
 
140 2 olivier.gi
      // TIMER A TEST:  UP MODE
141
      //--------------------------------------------------------
142
 
143
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
144
      @(posedge irq_ta1)
145
      @(negedge mclk)
146
        my_counter = 0;
147
      @(posedge irq_ta1)
148
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
149 111 olivier.gi
      test_step = 7;
150 2 olivier.gi
 
151
      @(mem200 === 16'h0002);  // Check timing 2 - TAIFG interrupt
152
      @(posedge irq_ta1)
153
      @(negedge mclk)
154
        my_counter = 0;
155
      @(posedge irq_ta1)
156
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
157 111 olivier.gi
      test_step = 8;
158 202 olivier.gi
 
159 2 olivier.gi
      @(mem200 === 16'h0003);  // Check timing 1 - TACCR0 interrupt
160
      @(posedge irq_ta0)
161
      @(negedge mclk)
162
        my_counter = 0;
163
      @(posedge irq_ta0)
164
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
165 111 olivier.gi
      test_step = 8;
166 2 olivier.gi
 
167
      @(mem200 === 16'h0004);  // Check timing 2 - TACCR0 interrupt
168
      @(posedge irq_ta0)
169
      @(negedge mclk)
170
        my_counter = 0;
171
      @(posedge irq_ta0)
172
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
173 111 olivier.gi
      test_step = 9;
174 202 olivier.gi
 
175 2 olivier.gi
      @(r15===16'h3000);
176
      if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
177
      if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
178 111 olivier.gi
      test_step = 10;
179 2 olivier.gi
 
180 202 olivier.gi
 
181 2 olivier.gi
      // TIMER A TEST:  CONTINUOUS MODE
182
      //--------------------------------------------------------
183
 
184
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
185
      @(negedge mclk)
186
      my_counter = 0;
187
      @(posedge irq_ta1)
188
        if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
189 111 olivier.gi
      test_step = 11;
190 2 olivier.gi
 
191 202 olivier.gi
 
192 2 olivier.gi
      // TIMER A TEST:  UP-DOWN MODE
193
      //--------------------------------------------------------
194
 
195
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
196
      @(posedge irq_ta0)
197
      @(negedge mclk)
198
      my_counter = 0;
199
      @(posedge irq_ta0)
200
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
201 111 olivier.gi
      test_step = 12;
202 2 olivier.gi
 
203
      @(posedge irq_ta1)       // Check timing 1 - TACCR0 interrupt
204
      @(negedge mclk)
205
      my_counter = 0;
206
      @(posedge irq_ta1)
207
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
208 111 olivier.gi
      test_step = 13;
209 2 olivier.gi
 
210
      @(posedge irq_ta0)       // Check timing 1 - TAIFG->TACCR0 interrupt
211
      @(negedge mclk)
212
      my_counter = 0;
213
      @(posedge irq_ta1)
214
        if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
215 111 olivier.gi
      test_step = 14;
216 2 olivier.gi
 
217
      @(mem200===16'h0002);
218
      if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
219
      if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
220 111 olivier.gi
      test_step = 15;
221 2 olivier.gi
 
222 134 olivier.gi
`endif
223 2 olivier.gi
 
224
      stimulus_done = 1;
225
   end

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