OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [tA_modes.v] - Blame information for rev 53

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                                  TIMER A                                  */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the timer A:                                                         */
27 
/*                        - Check RD/WR register access.                     */
28 
/*                        - Check the clock divider.                         */
29 
/*                        - Check the timer modes.                           */
30 18 olivier.gi 
/*                                                                           */
31 
/* Author(s):                                                                */
32 
/*             - Olivier Girard,    olgirard@gmail.com                       */
33 
/*                                                                           */
34 
/*---------------------------------------------------------------------------*/
35 19 olivier.gi 
/* $Rev: 19 $                                                                */
36 
/* $LastChangedBy: olivier.girard $                                          */
37 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
38 2 olivier.gi 
/*===========================================================================*/
39 
 
40 
integer my_counter;
41 
always @ (posedge mclk)
42 
  my_counter <=  my_counter+1;
43 
 
44 
initial
45 
   begin
46 
      $display(" ===============================================");
47 
      $display("|                 START SIMULATION              |");
48 
      $display(" ===============================================");
49 
      repeat(5) @(posedge mclk);
50 
      stimulus_done = 0;
51 
 
52 
      // TIMER A TEST:  RD/WR ACCESS
53 
      //--------------------------------------------------------
54 
 
55 
      @(r15===16'h1000);
56 
      if (mem200 !== 16'h02a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
57 
      if (mem202 !== 16'h0151) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
58 
      if (mem204 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
59 
      if (mem206 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACTL   ERROR =====");
60 
 
61 
      if (mem208 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
62 
      if (mem20A !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
63 
      if (mem20C !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAR     ERROR =====");
64 
 
65 
      if (mem210 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
66 
      if (mem212 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
67 
      if (mem214 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL0 ERROR =====");
68 
 
69 
      if (mem216 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
70 
      if (mem218 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
71 
      if (mem21A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR0  ERROR =====");
72 
 
73 
      if (mem220 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
74 
      if (mem222 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
75 
      if (mem224 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL1 ERROR =====");
76 
 
77 
      if (mem226 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
78 
      if (mem228 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
79 
      if (mem22A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR1  ERROR =====");
80 
 
81 
      if (mem230 !== 16'ha8a2) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
82 
      if (mem232 !== 16'h5155) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
83 
      if (mem234 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCTL2 ERROR =====");
84 
 
85 
      if (mem236 !== 16'haaaa) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
86 
      if (mem238 !== 16'h5555) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
87 
      if (mem23A !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TACCR2  ERROR =====");
88 
 
89 
      if (mem240 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
90 
      if (mem242 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
91 
      if (mem244 !== 16'h0000) tb_error("====== TIMER_A RD/WR REGISTERS: TAIV    ERROR =====");
92 
 
93 
 
94 
      // TIMER A TEST:  INPUT DIVIDER
95 
      //--------------------------------------------------------
96 
 
97 
      @(mem200 === 16'h0001);  // Check /1 divider
98 
      @(posedge irq_ta1)
99 
      @(negedge mclk)
100 
        my_counter = 0;
101 
      @(posedge irq_ta1)
102 
        if (my_counter !== 32'h21) tb_error("====== TIMER_A INPUT DIVIDER: /1 ERROR =====");
103 
 
104 
      @(mem200 === 16'h0002);  // Check /2 divider
105 
      @(posedge irq_ta1)
106 
      @(negedge mclk)
107 
        my_counter = 0;
108 
      @(posedge irq_ta1)
109 
        if (my_counter !== 32'h22) tb_error("====== TIMER_A INPUT DIVIDER: /2 ERROR =====");
110 
 
111 
      @(mem200 === 16'h0003);  // Check /4 divider
112 
      @(posedge irq_ta1)
113 
      @(negedge mclk)
114 
        my_counter = 0;
115 
      @(posedge irq_ta1)
116 
        if (my_counter !== 32'h24) tb_error("====== TIMER_A INPUT DIVIDER: /4 ERROR =====");
117 
 
118 
      @(mem200 === 16'h0004);  // Check /8 divider
119 
      @(posedge irq_ta1)
120 
      @(negedge mclk)
121 
        my_counter = 0;
122 
      @(posedge irq_ta1)
123 
        if (my_counter !== 32'h28) tb_error("====== TIMER_A INPUT DIVIDER: /8 ERROR =====");
124 
 
125 
      @(r15===16'h2000);
126 
 
127 
 
128 
      // TIMER A TEST:  UP MODE
129 
      //--------------------------------------------------------
130 
 
131 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
132 
      @(posedge irq_ta1)
133 
      @(negedge mclk)
134 
        my_counter = 0;
135 
      @(posedge irq_ta1)
136 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TAIFG interrupt =====");
137 
 
138 
      @(mem200 === 16'h0002);  // Check timing 2 - TAIFG interrupt
139 
      @(posedge irq_ta1)
140 
      @(negedge mclk)
141 
        my_counter = 0;
142 
      @(posedge irq_ta1)
143 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TAIFG interrupt =====");
144 
 
145 
      @(mem200 === 16'h0003);  // Check timing 1 - TACCR0 interrupt
146 
      @(posedge irq_ta0)
147 
      @(negedge mclk)
148 
        my_counter = 0;
149 
      @(posedge irq_ta0)
150 
        if (my_counter !== 32'h26) tb_error("====== TIMER_A UP MODE: TIMING 1 - TACCR0 interrupt =====");
151 
 
152 
      @(mem200 === 16'h0004);  // Check timing 2 - TACCR0 interrupt
153 
      @(posedge irq_ta0)
154 
      @(negedge mclk)
155 
        my_counter = 0;
156 
      @(posedge irq_ta0)
157 
        if (my_counter !== 32'h3E) tb_error("====== TIMER_A UP MODE: TIMING 2 - TACCR0 interrupt =====");
158 
 
159 
      @(r15===16'h3000);
160 
      if (mem202 !== 16'h0004) tb_error("====== TIMER_A UP MODE: TAIFG LATENCY ERROR =====");
161 
      if (mem204 !== 16'h0003) tb_error("====== TIMER_A UP MODE: TACCR0 LATENCY ERROR =====");
162 
 
163 
 
164 
      // TIMER A TEST:  CONTINUOUS MODE
165 
      //--------------------------------------------------------
166 
 
167 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
168 
      @(negedge mclk)
169 
      my_counter = 0;
170 
      @(posedge irq_ta1)
171 
        if (my_counter !== 32'h1C) tb_error("====== TIMER_A CONTINUOUS MODE: TIMING 1 - TAIFG interrupt =====");
172 
 
173 
 
174 
      // TIMER A TEST:  UP-DOWN MODE
175 
      //--------------------------------------------------------
176 
 
177 
      @(mem200 === 16'h0001);  // Check timing 1 - TAIFG interrupt
178 
      @(posedge irq_ta0)
179 
      @(negedge mclk)
180 
      my_counter = 0;
181 
      @(posedge irq_ta0)
182 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG interrupt =====");
183 
 
184 
      @(posedge irq_ta1)       // Check timing 1 - TACCR0 interrupt
185 
      @(negedge mclk)
186 
      my_counter = 0;
187 
      @(posedge irq_ta1)
188 
        if (my_counter !== 32'h62) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TACCR0 interrupt =====");
189 
 
190 
      @(posedge irq_ta0)       // Check timing 1 - TAIFG->TACCR0 interrupt
191 
      @(negedge mclk)
192 
      my_counter = 0;
193 
      @(posedge irq_ta1)
194 
        if (my_counter !== 32'h31) tb_error("====== TIMER_A UP-DOWN MODE: TIMING 1 - TAIFG->TACCR0 interrupt =====");
195 
 
196 
      @(mem200===16'h0002);
197 
      if (mem202 !== 16'h0008) tb_error("====== TIMER_A UP-DOWN MODE: TAIFG LATENCY ERROR =====");
198 
      if (mem204 !== 16'h0028) tb_error("====== TIMER_A UP-DOWN MODE: TACCR0 LATENCY ERROR =====");
199 
 
200 
 
201 
      stimulus_done = 1;
202 
   end
203 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.