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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [template_periph_16b.s43] - Blame information for rev 111

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                    16 BIT PERIPHERAL TEMPLATE                             */
/*---------------------------------------------------------------------------*/
/* Test the 16 bit peripheral template:                                      */
/*                                     - Read/Write register access.         */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/*===========================================================================*/
 
.global main
 
.set   DMEM_BASE, (__data_start     )
.set   DMEM_200,  (__data_start+0x00)
.set   DMEM_202,  (__data_start+0x02)
.set   DMEM_204,  (__data_start+0x04)
.set   DMEM_206,  (__data_start+0x06)
.set   DMEM_208,  (__data_start+0x08)
.set   DMEM_20A,  (__data_start+0x0A)
.set   DMEM_20C,  (__data_start+0x0C)
.set   DMEM_20E,  (__data_start+0x0E)
.set   DMEM_210,  (__data_start+0x10)
.set   DMEM_212,  (__data_start+0x12)
.set   DMEM_214,  (__data_start+0x14)
.set   DMEM_216,  (__data_start+0x16)
 
.set   UNUSED_0,  (DMEM_BASE-0x0070-0x0002)
.set   CNTRL1,    (DMEM_BASE-0x0070+0x0000)
.set   CNTRL2,    (DMEM_BASE-0x0070+0x0002)
.set   CNTRL3,    (DMEM_BASE-0x0070+0x0004)
.set   CNTRL4,    (DMEM_BASE-0x0070+0x0006)
.set   UNUSED_1,  (DMEM_BASE-0x0070-0x0008)
 
main:
        /* --------------     TEST RD/WR REGISTER ACCESS     --------------- */
 
        mov   #0x1234,  &UNUSED_0       ; UNUSED 0
        mov &UNUSED_0,  &DMEM_200
        mov   #0x5678,  &UNUSED_0
        mov &UNUSED_0,  &DMEM_202
 
        mov   #0x5555,  &CNTRL1         ; CNTRL1
        mov   &CNTRL1,  &DMEM_204
        mov   #0xaaaa,  &CNTRL1
        mov   &CNTRL1,  &DMEM_206
 
        mov   #0xaaaa,  &CNTRL2         ; CNTRL2
        mov   &CNTRL2,  &DMEM_208
        mov   #0x5555,  &CNTRL2
        mov   &CNTRL2,  &DMEM_20A
 
        mov   #0x55aa,  &CNTRL3         ; CNTRL3
        mov   &CNTRL3,  &DMEM_20C
        mov   #0xaa55,  &CNTRL3
        mov   &CNTRL3,  &DMEM_20E
 
        mov   #0xaa55,  &CNTRL4         ; CNTRL4
        mov   &CNTRL4,  &DMEM_210
        mov   #0x55aa,  &CNTRL4
        mov   &CNTRL4,  &DMEM_212
 
        mov   #0x8765,  &UNUSED_1       ; UNUSED 1
        mov &UNUSED_1,  &DMEM_214
        mov   #0x4321,  &UNUSED_1
        mov &UNUSED_1,  &DMEM_216
 
        mov   #0x0001, r15
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word end_of_test  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* 16 BIT PERIPHERAL TEMPLATE */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the 16 bit peripheral template: */`
27			`/* - Read/Write register access. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33	19	olivier.gi	`/* $Rev: 111 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38			`.global main`
39
40	111	olivier.gi	`.set DMEM_BASE, (__data_start )`
41			`.set DMEM_200, (__data_start+0x00)`
42			`.set DMEM_202, (__data_start+0x02)`
43			`.set DMEM_204, (__data_start+0x04)`
44			`.set DMEM_206, (__data_start+0x06)`
45			`.set DMEM_208, (__data_start+0x08)`
46			`.set DMEM_20A, (__data_start+0x0A)`
47			`.set DMEM_20C, (__data_start+0x0C)`
48			`.set DMEM_20E, (__data_start+0x0E)`
49			`.set DMEM_210, (__data_start+0x10)`
50			`.set DMEM_212, (__data_start+0x12)`
51			`.set DMEM_214, (__data_start+0x14)`
52			`.set DMEM_216, (__data_start+0x16)`
53	2	olivier.gi
54	111	olivier.gi	`.set UNUSED_0, (DMEM_BASE-0x0070-0x0002)`
55			`.set CNTRL1, (DMEM_BASE-0x0070+0x0000)`
56			`.set CNTRL2, (DMEM_BASE-0x0070+0x0002)`
57			`.set CNTRL3, (DMEM_BASE-0x0070+0x0004)`
58			`.set CNTRL4, (DMEM_BASE-0x0070+0x0006)`
59			`.set UNUSED_1, (DMEM_BASE-0x0070-0x0008)`
60
61	2	olivier.gi	`main:`
62			`/* -------------- TEST RD/WR REGISTER ACCESS --------------- */`
63
64	111	olivier.gi	`mov #0x1234, &UNUSED_0 ; UNUSED 0`
65			`mov &UNUSED_0, &DMEM_200`
66			`mov #0x5678, &UNUSED_0`
67			`mov &UNUSED_0, &DMEM_202`
68
69	2	olivier.gi	`mov #0x5555, &CNTRL1 ; CNTRL1`
70	111	olivier.gi	`mov &CNTRL1, &DMEM_204`
71	2	olivier.gi	`mov #0xaaaa, &CNTRL1`
72	111	olivier.gi	`mov &CNTRL1, &DMEM_206`
73	2	olivier.gi
74			`mov #0xaaaa, &CNTRL2 ; CNTRL2`
75	111	olivier.gi	`mov &CNTRL2, &DMEM_208`
76	2	olivier.gi	`mov #0x5555, &CNTRL2`
77	111	olivier.gi	`mov &CNTRL2, &DMEM_20A`
78	2	olivier.gi
79			`mov #0x55aa, &CNTRL3 ; CNTRL3`
80	111	olivier.gi	`mov &CNTRL3, &DMEM_20C`
81	2	olivier.gi	`mov #0xaa55, &CNTRL3`
82	111	olivier.gi	`mov &CNTRL3, &DMEM_20E`
83	2	olivier.gi
84			`mov #0xaa55, &CNTRL4 ; CNTRL4`
85	111	olivier.gi	`mov &CNTRL4, &DMEM_210`
86	2	olivier.gi	`mov #0x55aa, &CNTRL4`
87	111	olivier.gi	`mov &CNTRL4, &DMEM_212`
88	2	olivier.gi
89	111	olivier.gi	`mov #0x8765, &UNUSED_1 ; UNUSED 1`
90			`mov &UNUSED_1, &DMEM_214`
91			`mov #0x4321, &UNUSED_1`
92			`mov &UNUSED_1, &DMEM_216`
93	2	olivier.gi
94			`mov #0x0001, r15`
95
96
97
98			`/* ---------------------- END OF TEST --------------- */`
99			`end_of_test:`
100			`nop`
101			`br #0xffff`
102
103
104			`/* ---------------------- INTERRUPT VECTORS --------------- */`
105
106			`.section .vectors, "a"`
107			`.word end_of_test ; Interrupt 0 (lowest priority)`
108			`.word end_of_test ; Interrupt 1`
109			`.word end_of_test ; Interrupt 2`
110			`.word end_of_test ; Interrupt 3`
111			`.word end_of_test ; Interrupt 4`
112			`.word end_of_test ; Interrupt 5`
113			`.word end_of_test ; Interrupt 6`
114			`.word end_of_test ; Interrupt 7`
115			`.word end_of_test ; Interrupt 8`
116			`.word end_of_test ; Interrupt 9`
117			`.word end_of_test ; Interrupt 10 Watchdog timer`
118			`.word end_of_test ; Interrupt 11`
119			`.word end_of_test ; Interrupt 12`
120			`.word end_of_test ; Interrupt 13`
121			`.word end_of_test ; Interrupt 14 NMI`
122			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [template_periph_16b.s43] - Blame information for rev 111