OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [template_periph_8b.s43] - Blame information for rev 111

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                     8 BIT PERIPHERAL TEMPLATE                             */
25
/*---------------------------------------------------------------------------*/
26
/* Test the 8 bit peripheral template:                                       */
27
/*                                     - Read/Write register access.         */
28 18 olivier.gi
/*                                                                           */
29
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32
/*---------------------------------------------------------------------------*/
33 19 olivier.gi
/* $Rev: 111 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
36 2 olivier.gi
/*===========================================================================*/
37
 
38
.global main
39
 
40 111 olivier.gi
.set   DMEM_BASE, (__data_start     )
41
.set   DMEM_200,  (__data_start+0x00)
42
.set   DMEM_201,  (__data_start+0x01)
43
.set   DMEM_202,  (__data_start+0x02)
44
.set   DMEM_203,  (__data_start+0x03)
45
.set   DMEM_204,  (__data_start+0x04)
46
.set   DMEM_205,  (__data_start+0x05)
47
.set   DMEM_206,  (__data_start+0x06)
48
.set   DMEM_207,  (__data_start+0x07)
49
 
50 2 olivier.gi
.set   CNTRL1, 0x0090
51
.set   CNTRL2, 0x0091
52
.set   CNTRL3, 0x0092
53
.set   CNTRL4, 0x0093
54
 
55
main:
56
        /* --------------     TEST RD/WR REGISTER ACCESS     --------------- */
57
 
58
        mov.b #0x11,   &CNTRL1         ; CNTRL1
59 111 olivier.gi
        mov.b &CNTRL1, &DMEM_200
60 2 olivier.gi
        mov.b #0xee,   &CNTRL1
61 111 olivier.gi
        mov.b &CNTRL1, &DMEM_201
62 2 olivier.gi
 
63
        mov.b #0xaa,   &CNTRL2         ; CNTRL2
64 111 olivier.gi
        mov.b &CNTRL2, &DMEM_202
65 2 olivier.gi
        mov.b #0x55,   &CNTRL2
66 111 olivier.gi
        mov.b &CNTRL2, &DMEM_203
67 2 olivier.gi
 
68
        mov.b #0x5a,   &CNTRL3         ; CNTRL3
69 111 olivier.gi
        mov.b &CNTRL3, &DMEM_204
70 2 olivier.gi
        mov.b #0xa5,   &CNTRL3
71 111 olivier.gi
        mov.b &CNTRL3, &DMEM_205
72 2 olivier.gi
 
73
        mov.b #0x55,   &CNTRL4         ; CNTRL4
74 111 olivier.gi
        mov.b &CNTRL4, &DMEM_206
75 2 olivier.gi
        mov.b #0xaa,   &CNTRL4
76 111 olivier.gi
        mov.b &CNTRL4, &DMEM_207
77 2 olivier.gi
 
78
 
79
        mov   #0x0001, r15
80
 
81
 
82
 
83
        /* ----------------------         END OF TEST        --------------- */
84
end_of_test:
85
        nop
86
        br #0xffff
87
 
88
 
89
        /* ----------------------         INTERRUPT VECTORS  --------------- */
90
 
91
.section .vectors, "a"
92
.word end_of_test  ; Interrupt  0 (lowest priority)    
93
.word end_of_test  ; Interrupt  1                      
94
.word end_of_test  ; Interrupt  2                      
95
.word end_of_test  ; Interrupt  3                      
96
.word end_of_test  ; Interrupt  4                      
97
.word end_of_test  ; Interrupt  5                      
98
.word end_of_test  ; Interrupt  6                      
99
.word end_of_test  ; Interrupt  7                      
100
.word end_of_test  ; Interrupt  8                      
101
.word end_of_test  ; Interrupt  9                      
102
.word end_of_test  ; Interrupt 10                      Watchdog timer
103
.word end_of_test  ; Interrupt 11                      
104
.word end_of_test  ; Interrupt 12                      
105
.word end_of_test  ; Interrupt 13                      
106
.word end_of_test  ; Interrupt 14                      NMI
107
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.