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olivier.gi |
/*===========================================================================*/
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/* Copyright (C) 2001 Authors */
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/* */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer. */
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/* */
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/* This source file is free software; you can redistribute it and/or modify */
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/* it under the terms of the GNU Lesser General Public License as published */
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/* by the Free Software Foundation; either version 2.1 of the License, or */
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/* (at your option) any later version. */
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/* */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
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/* License for more details. */
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/* */
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/* You should have received a copy of the GNU Lesser General Public License */
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/* along with this source; if not, write to the Free Software Foundation, */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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/* */
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/*===========================================================================*/
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/* 8 BIT PERIPHERAL TEMPLATE */
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/*---------------------------------------------------------------------------*/
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/* Test the 8 bit peripheral template: */
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/* - Read/Write register access. */
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olivier.gi |
/* */
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/* Author(s): */
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/* - Olivier Girard, olgirard@gmail.com */
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/* */
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/*---------------------------------------------------------------------------*/
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olivier.gi |
/* $Rev: 19 $ */
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/* $LastChangedBy: olivier.girard $ */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
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olivier.gi |
/*===========================================================================*/
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initial
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begin
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$display(" ===============================================");
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$display("| START SIMULATION |");
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$display(" ===============================================");
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repeat(5) @(posedge mclk);
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stimulus_done = 0;
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// TEST RD/WR REGISTER ACCESS
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//--------------------------------------------------------
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@(r15==16'h0001);
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if (mem200 !== 16'hee11) tb_error("====== CNTRL1: @0x200 != 0xee11 =====");
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if (mem202 !== 16'h55aa) tb_error("====== CNTRL2: @0x202 != 0x55aa =====");
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if (mem204 !== 16'ha55a) tb_error("====== CNTRL3: @0x204 != 0xa55a =====");
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if (mem206 !== 16'haa55) tb_error("====== CNTRL4: @0x206 != 0xaa55 =====");
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stimulus_done = 1;
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end
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