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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_add.v] - Blame information for rev 219

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Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 TWO-OPERAND ARITHMETIC: ADD INSTRUCTION                   */
25
/*---------------------------------------------------------------------------*/
26
/* Test the ADD instruction with all addressing modes                        */
27 18 olivier.gi
/*                                                                           */
28
/* Author(s):                                                                */
29
/*             - Olivier Girard,    olgirard@gmail.com                       */
30
/*                                                                           */
31
/*---------------------------------------------------------------------------*/
32 19 olivier.gi
/* $Rev: 134 $                                                                */
33
/* $LastChangedBy: olivier.girard $                                          */
34
/* $LastChangedDate: 2012-03-22 21:31:06 +0100 (Thu, 22 Mar 2012) $          */
35 2 olivier.gi
/*===========================================================================*/
36
 
37
initial
38
   begin
39
      $display(" ===============================================");
40
      $display("|                 START SIMULATION              |");
41
      $display(" ===============================================");
42
      repeat(5) @(posedge mclk);
43
      stimulus_done = 0;
44
 
45
      // Check reset values
46
      //--------------------------------------------------------
47
      if (r2 !==16'h0000) tb_error("R2  reset value");
48
      if (r3 !==16'h0000) tb_error("R3  reset value");
49
      if (r4 !==16'h0000) tb_error("R4  reset value");
50
      if (r5 !==16'h0000) tb_error("R5  reset value");
51
      if (r6 !==16'h0000) tb_error("R6  reset value");
52
      if (r7 !==16'h0000) tb_error("R7  reset value");
53
      if (r8 !==16'h0000) tb_error("R8  reset value");
54
      if (r9 !==16'h0000) tb_error("R9  reset value");
55
      if (r10!==16'h0000) tb_error("R10 reset value");
56
      if (r11!==16'h0000) tb_error("R11 reset value");
57
      if (r12!==16'h0000) tb_error("R12 reset value");
58
      if (r13!==16'h0000) tb_error("R13 reset value");
59
      if (r14!==16'h0000) tb_error("R14 reset value");
60
      if (r15!==16'h0000) tb_error("R15 reset value");
61
 
62
 
63
      // Make sure initialization worked fine
64
      //--------------------------------------------------------
65
      @(r15==16'h1000);
66
 
67 134 olivier.gi
      if (r2 !==16'h0002) tb_error("R2  initialization");
68 2 olivier.gi
      if (r3 !==16'h3333) tb_error("R3  initialization");
69
      if (r4 !==16'h4444) tb_error("R4  initialization");
70
      if (r5 !==16'h5555) tb_error("R5  initialization");
71
      if (r6 !==16'h6666) tb_error("R6  initialization");
72
      if (r7 !==16'h7777) tb_error("R7  initialization");
73
      if (r8 !==16'h8888) tb_error("R8  initialization");
74
      if (r9 !==16'h9999) tb_error("R9  initialization");
75
      if (r10!==16'haaaa) tb_error("R10 initialization");
76
      if (r11!==16'hbbbb) tb_error("R11 initialization");
77
      if (r12!==16'hcccc) tb_error("R12 initialization");
78
      if (r13!==16'hdddd) tb_error("R13 initialization");
79
      if (r14!==16'heeee) tb_error("R14 initialization");
80
 
81
 
82
      // ADD: Check when source is Rn
83
      //--------------------------------------------------------
84
      @(r15==16'h2000);
85
 
86
      if (r5     !==16'h9999) tb_error("====== ADD Rn Rm    =====");
87
      if (r4     ===16'h1234) tb_error("====== ADD Rn PC    =====");
88
      if (mem210 !==16'h5555) tb_error("====== ADD Rn x(Rm) =====");
89
      if (mem212 !==16'h9abc) tb_error("====== ADD Rn EDE   =====");
90
      if (mem214 !==16'h6789) tb_error("====== ADD Rn &EDE  =====");
91
 
92
 
93
      // ADD: Check when source is @Rn
94
      //--------------------------------------------------------
95
      @(r15==16'h3000);
96
 
97
      if (r5     !==16'h7777) tb_error("====== ADD @Rn Rm    =====");
98
      if (r4     ===16'h0000) tb_error("====== ADD @Rn PC    =====");
99
      if (mem210 !==16'h6666) tb_error("====== ADD @Rn x(Rm) =====");
100
      if (mem212 !==16'hed2e) tb_error("====== ADD @Rn EDE   =====");
101
      if (mem214 !==16'h4653) tb_error("====== ADD @Rn &EDE  =====");
102
 
103
 
104
      // ADD: Check when source is @Rn+
105
      //--------------------------------------------------------
106
      @(r15==16'h4000);
107
 
108 111 olivier.gi
      if (r4     !==(`PER_SIZE+16'h0002)) tb_error("====== ADD @Rn+ Rm    =====");
109
      if (r5     !==16'haaaa)             tb_error("====== ADD @Rn+ Rm    =====");
110 2 olivier.gi
 
111 111 olivier.gi
      if (r6     !==(`PER_SIZE+16'h0006)) tb_error("====== ADD @Rn+ PC    =====");
112 2 olivier.gi
 
113 111 olivier.gi
      if (r7     !==(`PER_SIZE+16'h0010)) tb_error("====== ADD @Rn+ x(Rm) =====");
114
      if (mem210 !==16'h6666)             tb_error("====== ADD @Rn+ x(Rm) =====");
115 2 olivier.gi
 
116 111 olivier.gi
      if (r8     !==(`PER_SIZE+16'h0008)) tb_error("====== ADD @Rn+ EDE =====");
117
      if (mem212 !==16'hed2e)             tb_error("====== ADD @Rn+ EDE   =====");
118 2 olivier.gi
 
119 111 olivier.gi
      if (r9     !==(`PER_SIZE+16'h0004)) tb_error("====== ADD @Rn+ &EDE =====");
120
      if (mem214 !==16'h4653)             tb_error("====== ADD @Rn+ &EDE  =====");
121 2 olivier.gi
 
122
      // ADD: Check when source is #N
123
      //--------------------------------------------------------
124
      @(r15==16'h5000);
125
 
126
      if (r4     !==16'h4444) tb_error("====== ADD #N  Rm    =====");
127
      if (r5     !==16'h0000) tb_error("====== ADD #N  PC    =====");
128
      if (mem230 !==16'hae8c) tb_error("====== ADD #N  x(Rm) =====");
129
      if (mem210 !==16'h5d50) tb_error("====== ADD #N  EDE   =====");
130
      if (mem206 !==16'h6ea1) tb_error("====== ADD #N  &EDE  =====");
131
 
132
 
133
      // ADD: Check when source is x(Rn)
134
      //--------------------------------------------------------
135
      @(r15==16'h6000);
136
 
137
      if (r5     !==16'h957b) tb_error("====== ADD x(Rn) Rm    =====");
138
      if (r6     ===16'h0000) tb_error("====== ADD x(Rn) PC    =====");
139
      if (mem214 !==16'h5776) tb_error("====== ADD x(Rn) x(Rm) =====");
140
      if (mem220 !==16'h937b) tb_error("====== ADD x(Rn) EDE   =====");
141
      if (mem208 !==16'hace4) tb_error("====== ADD x(Rn) &EDE  =====");
142
 
143
 
144
      // ADD: Check when source is EDE
145
      //--------------------------------------------------------
146
      @(r15==16'h7000);
147
 
148
      if (r4     !==16'h06f7) tb_error("====== ADD EDE Rm    =====");
149
      if (r6     ===16'h0000) tb_error("====== ADD EDE PC    =====");
150
      if (mem214 !==16'h0946) tb_error("====== ADD EDE x(Rm) =====");
151
      if (mem216 !==16'hb933) tb_error("====== ADD EDE EDE   =====");
152
      if (mem212 !==16'h2ab2) tb_error("====== ADD EDE &EDE  =====");
153
 
154
 
155
      // ADD: Check when source is &EDE
156
      //--------------------------------------------------------
157
      @(r15==16'h8000);
158
 
159
      if (r4     !==16'h66f5) tb_error("====== ADD &EDE Rm    =====");
160
      if (r6     ===16'h0000) tb_error("====== ADD &EDE PC    =====");
161
      if (mem214 !==16'h82d1) tb_error("====== ADD &EDE x(Rm) =====");
162
      if (mem218 !==16'hca4e) tb_error("====== ADD &EDE EDE   =====");
163
      if (mem202 !==16'h1338) tb_error("====== ADD &EDE &EDE  =====");
164
 
165
 
166
      // ADD: Check when source is CONST
167
      //--------------------------------------------------------
168
      @(r15==16'h9000);
169
 
170
      if (r4     !==16'h4444) tb_error("====== ADD #+0 Rm    =====");
171
      if (r5     !==16'h5556) tb_error("====== ADD #+1 Rm    =====");
172
      if (r6     !==16'h6668) tb_error("====== ADD #+2 Rm    =====");
173
      if (r7     !==16'h777b) tb_error("====== ADD #+4 Rm    =====");
174
      if (r8     !==16'h8890) tb_error("====== ADD #+8 Rm    =====");
175
      if (r9     !==16'h9998) tb_error("====== ADD #-1 Rm    =====");
176
 
177
      if (r11    !==16'h1234) tb_error("====== ADD #+4 PC    =====");
178
 
179
      if (mem210 !==16'h4444) tb_error("====== ADD #+0 x(Rm) =====");
180
      if (mem212 !==16'h5556) tb_error("====== ADD #+1 x(Rm) =====");
181
      if (mem214 !==16'h6668) tb_error("====== ADD #+2 x(Rm) =====");
182
      if (mem216 !==16'h777b) tb_error("====== ADD #+4 x(Rm) =====");
183
      if (mem218 !==16'h8890) tb_error("====== ADD #+8 x(Rm) =====");
184
      if (mem21A !==16'h9998) tb_error("====== ADD #-1 x(Rm) =====");
185
 
186
      if (mem220 !==16'h4444) tb_error("====== ADD #+0 EDE   =====");
187
      if (mem222 !==16'h5556) tb_error("====== ADD #+1 EDE   =====");
188
      if (mem224 !==16'h6668) tb_error("====== ADD #+2 EDE   =====");
189
      if (mem226 !==16'h777b) tb_error("====== ADD #+4 EDE   =====");
190
      if (mem228 !==16'h8890) tb_error("====== ADD #+8 EDE   =====");
191
      if (mem22A !==16'h9998) tb_error("====== ADD #-1 EDE   =====");
192
 
193
      if (mem230 !==16'h4444) tb_error("====== ADD #+0 &EDE  =====");
194
      if (mem232 !==16'h5556) tb_error("====== ADD #+1 &EDE  =====");
195
      if (mem234 !==16'h6668) tb_error("====== ADD #+2 &EDE  =====");
196
      if (mem236 !==16'h777b) tb_error("====== ADD #+4 &EDE  =====");
197
      if (mem238 !==16'h8890) tb_error("====== ADD #+8 &EDE  =====");
198
      if (mem23A !==16'h9998) tb_error("====== ADD #-1 &EDE  =====");
199
 
200
 
201
      // ADD: Check Flags
202
      //--------------------------------------------------------
203
 
204
      @(r15==16'hA000);
205
      if (r2    !==16'h0000) tb_error("====== ADD FLAG: Flag   check error: V=0, N=0, Z=0, C=0 =====");
206
      if (r5    !==16'h0999) tb_error("====== ADD FLAG: Result check error: V=0, N=0, Z=0, C=0 =====");
207
 
208
      @(r15==16'hA001);
209
      if (r2    !==16'h0001) tb_error("====== ADD FLAG: Flag   check error: V=0, N=0, Z=0, C=1 =====");
210
      if (r5    !==16'h0001) tb_error("====== ADD FLAG: Result check error: V=0, N=0, Z=0, C=1 =====");
211
 
212
      @(r15==16'hA002);
213
      if (r2    !==16'h0002) tb_error("====== ADD FLAG: Flag   check error: V=0, N=0, Z=1, C=0 =====");
214
      if (r5    !==16'h0000) tb_error("====== ADD FLAG: Result check error: V=0, N=0, Z=1, C=0 =====");
215
 
216
      @(r15==16'hA003);
217
      if (r2    !==16'h0004) tb_error("====== ADD FLAG: Flag   check error: V=0, N=1, Z=0, C=0 =====");
218
      if (r5    !==16'hff10) tb_error("====== ADD FLAG: Result check error: V=0, N=1, Z=0, C=0 =====");
219
 
220
      @(r15==16'hA004);
221
      if (r2    !==16'h0104) tb_error("====== ADD FLAG: Flag   check error: V=1, N=1, Z=0, C=0 =====");
222
      if (r5    !==16'h800f) tb_error("====== ADD FLAG: Result check error: V=1, N=1, Z=0, C=0 =====");
223
 
224
      @(r15==16'hA005);
225
      if (r2    !==16'h0101) tb_error("====== ADD FLAG: Flag   check error: V=1, N=0, Z=0, C=1 =====");
226
      if (r5    !==16'h7f00) tb_error("====== ADD FLAG: Result check error: V=1, N=0, Z=0, C=1 =====");
227
 
228
//    ---------------- TEST WHEN SOURCE IS CONSTANT IN BYTE MODE ------ */
229
//    #
230
//    # NOTE: The following section would not fit in the smallest ROM
231
//    #       configuration for the "two-op_add-b.v" pattern.
232
//    #       It is therefore executed here.
233
//    #
234
      @(r15==16'hB000);
235
 
236
 
237
      if (mem250 !==16'haa44) tb_error("====== ADD.B #+0 &EDE =====");
238
      if (mem252 !==16'haa56) tb_error("====== ADD.B #+1 &EDE =====");
239
      if (mem254 !==16'haa68) tb_error("====== ADD.B #+2 &EDE =====");
240
      if (mem256 !==16'haa7b) tb_error("====== ADD.B #+4 &EDE =====");
241
      if (mem258 !==16'haa3d) tb_error("====== ADD.B #+8 &EDE =====");
242
      if (mem25A !==16'haa98) tb_error("====== ADD.B #-1 &EDE =====");
243
      if (mem25C !==16'haa55) tb_error("====== ADD.B #+0 &EDE =====");
244
      if (mem25E !==16'hbc55) tb_error("====== ADD.B #+1 &EDE =====");
245
      if (mem260 !==16'hce55) tb_error("====== ADD.B #+2 &EDE =====");
246
      if (mem262 !==16'he155) tb_error("====== ADD.B #+4 &EDE =====");
247
      if (mem264 !==16'hf655) tb_error("====== ADD.B #+8 &EDE =====");
248
      if (mem266 !==16'h3255) tb_error("====== ADD.B #-1 &EDE =====");
249
 
250
 
251
      // ADD.B: Check Flags
252
      //--------------------------------------------------------
253
 
254
      @(r15==16'hC000);
255
      if (r2    !==16'h0000) tb_error("====== ADD.B FLAG: Flag   check error: V=0, N=0, Z=0, C=0 =====");
256
      if (r5    !==16'h0009) tb_error("====== ADD.B FLAG: Result check error: V=0, N=0, Z=0, C=0 =====");
257
 
258
      @(r15==16'hC001);
259
      if (r2    !==16'h0001) tb_error("====== ADD.B FLAG: Flag   check error: V=0, N=0, Z=0, C=1 =====");
260
      if (r5    !==16'h0001) tb_error("====== ADD.B FLAG: Result check error: V=0, N=0, Z=0, C=1 =====");
261
 
262
      @(r15==16'hC002);
263
      if (r2    !==16'h0002) tb_error("====== ADD.B FLAG: Flag   check error: V=0, N=0, Z=1, C=0 =====");
264
      if (r5    !==16'h0000) tb_error("====== ADD.B FLAG: Result check error: V=0, N=0, Z=1, C=0 =====");
265
 
266
      @(r15==16'hC003);
267
      if (r2    !==16'h0004) tb_error("====== ADD.B FLAG: Flag   check error: V=0, N=1, Z=0, C=0 =====");
268
      if (r5    !==16'h00f3) tb_error("====== ADD.B FLAG: Result check error: V=0, N=1, Z=0, C=0 =====");
269
 
270
      @(r15==16'hC004);
271
      if (r2    !==16'h0104) tb_error("====== ADD.B FLAG: Flag   check error: V=1, N=1, Z=0, C=0 =====");
272
      if (r5    !==16'h008f) tb_error("====== ADD.B FLAG: Result check error: V=1, N=1, Z=0, C=0 =====");
273
 
274
      @(r15==16'hC005);
275
      if (r2    !==16'h0101) tb_error("====== ADD.B FLAG: Flag   check error: V=1, N=0, Z=0, C=1 =====");
276
      if (r5    !==16'h007f) tb_error("====== ADD.B FLAG: Result check error: V=1, N=0, Z=0, C=1 =====");
277
 
278
      stimulus_done = 1;
279
   end
280
 

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