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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_addc.s43] - Blame information for rev 19

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1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                 TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION              */
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/*---------------------------------------------------------------------------*/
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/* Test the ADDC[.B] instruction.                                            */
27 18 olivier.gi
/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
32 19 olivier.gi
/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
35 2 olivier.gi
/*===========================================================================*/
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.global main
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main:
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        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
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        # Test standard ADD without Carry bit set
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        mov     #0x0000, r2
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        mov     #0x4444, r4
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        mov     #0x5555, r5
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        add          r4, r5        ;# Add r4+r5 (0x4444+0x5555=0x9999)
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        # Test standard ADD withCarry bit set
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        mov     #0x0001, r2
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        mov     #0x6666, r4
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        mov     #0x7777, r6
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        add          r4, r6        ;# Add r4+r6 (0x6666+0x7777=0xdddd)
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        # Test standard ADDC without Carry bit set
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        mov     #0x0000, r2
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        mov     #0x8888, r4
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        mov     #0x9999, r7
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        addc         r4, r7        ;# Add r4+r7+c (0x8888+0x9999=0x2221)
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        # Test standard ADDC with Carry bit set
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        mov     #0x0001, r2
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        mov     #0xaaaa, r4
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        mov     #0xbbbb, r8
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        addc         r4, r8        ;# Add r4+r8+C (0xaaaa+0xbbbb=0x6666)
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        mov     #0x1000, r15
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        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
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        # Test standard ADD with and without Carry bit set
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        mov     #0x0000, r2
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        mov     #0x4444, r4
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        mov     #0x5555, r5
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        add.b        r4, r5        ;# Add r4+r5 (0x0044+0x0055=0x0099)
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        # Test standard ADD with and with Carry bit set
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        mov     #0x0001, r2
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        mov     #0x6666, r4
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        mov     #0x6677, r6
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        add.b        r4, r6        ;# Add r4+r6 (0x0066+0x0077=0x00dd)
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        # Test standard ADDC with and without Carry bit set
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        mov     #0x0000, r2
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        mov     #0x8888, r4
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        mov     #0x9999, r7
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        addc.b       r4, r7        ;# Add r4+r5+c (0x0088+0x0099=0x0021)
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        # Test standard ADDC with and with Carry bit set
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        mov     #0x0001, r2
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        mov     #0xaaaa, r4
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        mov     #0xbbbb, r8
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        addc.b       r4, r8        ;# Add r4+r6+C (0x00aa+0x00bb=0x0066)
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        mov     #0x2000, r15
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        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
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        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=0
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        mov     #0x0444, r4        ;#
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        mov     #0x0555, r5        ;#
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        addc         r4, r5        ;# Add r4+r5 (0x0444+0x0555=0x0999)
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        mov     #0x3000, r15
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        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=1
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        mov     #0x0011, r4        ;#
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        mov     #0xfff0, r5        ;#
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        addc         r4, r5        ;# Add r4+r5 (0xfff0+0x0011=0x0001)
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        mov     #0x3001, r15
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        mov     #0x0000, r2        ;# V=0, N=0, Z=1, C=0
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        mov     #0x0000, r4        ;#
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        mov     #0x0000, r5        ;#
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        addc         r4, r5        ;# Add r4+r5 (0x0000+0x0000=0x0000)
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        mov     #0x3002, r15
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        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=0
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        mov     #0xff00, r4        ;#
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        mov     #0x0010, r5        ;#
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        addc         r4, r5        ;# Add r4+r5 (0xff00+0x0010=0xff10)
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        mov     #0x3003, r15
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        mov     #0x0000, r2        ;# V=1, N=1, Z=0, C=0
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        mov     #0x7fff, r4        ;#
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        mov     #0x0010, r5        ;#
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        addc         r4, r5        ;# Add r4+r5 (0x7fff+0x0010=0x800f)
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        mov     #0x3004, r15
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        mov     #0x0000, r2        ;# V=1, N=0, Z=0, C=1
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        mov     #0xff00, r4        ;#
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        mov     #0x8000, r5        ;#
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        addc         r4, r5        ;# Add r4+r5 (0xff00+0x8000=0x7f00)
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        mov     #0x3005, r15
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        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
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        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=0
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        mov     #0xaa04, r4        ;#
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        mov     #0x6605, r5        ;#
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        addc.b       r4, r5        ;# Add r4+r5 (0xaa04+0x6605=0x0009)
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        mov     #0x4000, r15
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        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=1
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        mov     #0xaa11, r4        ;#
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        mov     #0x66f0, r5        ;#
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        addc.b       r4, r5        ;# Add r4+r5 (0x0011+0x00f0=0x0001)
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        mov     #0x4001, r15
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        mov     #0x0000, r2        ;# V=0, N=0, Z=1, C=0
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        mov     #0xaa00, r4        ;#
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        mov     #0x6600, r5        ;#
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        addc.b       r4, r5        ;# Add r4+r5 (0x0000+0x0000=0x0000)
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        mov     #0x4002, r15
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        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=0
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        mov     #0xaaf0, r4        ;#
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        mov     #0x6603, r5        ;#
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        addc.b       r4, r5        ;# Add r4+r5 (0x00f0+0x0003=0x00f3)
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        mov     #0x4003, r15
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        mov     #0x0000, r2        ;# V=1, N=1, Z=0, C=0
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        mov     #0x007f, r4        ;#
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        mov     #0x0010, r5        ;#
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        addc.b       r4, r5        ;# Add r4+r5 (0x007f+0x0010=0x008f)
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        mov     #0x4004, r15
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        mov     #0x0000, r2        ;# V=1, N=0, Z=0, C=1
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        mov     #0x00ff, r4        ;#
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        mov     #0x0080, r5        ;#
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        addc.b       r4, r5        ;# Add r4+r5 (0x00ff+0x0080=0x007f)
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        mov     #0x4005, r15
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        /* ----------------------         END OF TEST        --------------- */
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        mov     #0x5000, r15
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end_of_test:
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        nop
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        br #0xffff
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        /* ----------------------         INTERRUPT VECTORS  --------------- */
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.section .vectors, "a"
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.word end_of_test  ; Interrupt  0 (lowest priority)    
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.word end_of_test  ; Interrupt  1                      
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.word end_of_test  ; Interrupt  2                      
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.word end_of_test  ; Interrupt  3                      
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.word end_of_test  ; Interrupt  4                      
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.word end_of_test  ; Interrupt  5                      
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.word end_of_test  ; Interrupt  6                      
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.word end_of_test  ; Interrupt  7                      
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.word end_of_test  ; Interrupt  8                      
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.word end_of_test  ; Interrupt  9                      
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.word end_of_test  ; Interrupt 10                      Watchdog timer
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.word end_of_test  ; Interrupt 11                      
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.word end_of_test  ; Interrupt 12                      
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.word end_of_test  ; Interrupt 13                      
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.word end_of_test  ; Interrupt 14                      NMI
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.word main         ; Interrupt 15 (highest priority)   RESET

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