OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_addc.s43] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION              */
25
/*---------------------------------------------------------------------------*/
26
/* Test the ADDC[.B] instruction.                                            */
27 18 olivier.gi
/*                                                                           */
28
/* Author(s):                                                                */
29
/*             - Olivier Girard,    olgirard@gmail.com                       */
30
/*                                                                           */
31
/*---------------------------------------------------------------------------*/
32 19 olivier.gi
/* $Rev: 19 $                                                                */
33
/* $LastChangedBy: olivier.girard $                                          */
34
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
35 2 olivier.gi
/*===========================================================================*/
36
 
37
 
38
.global main
39
 
40
main:
41
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
42
 
43
        # Test standard ADD without Carry bit set
44
        mov     #0x0000, r2
45
        mov     #0x4444, r4
46
        mov     #0x5555, r5
47
        add          r4, r5        ;# Add r4+r5 (0x4444+0x5555=0x9999)
48
 
49
        # Test standard ADD withCarry bit set
50
        mov     #0x0001, r2
51
        mov     #0x6666, r4
52
        mov     #0x7777, r6
53
        add          r4, r6        ;# Add r4+r6 (0x6666+0x7777=0xdddd)
54
 
55
 
56
        # Test standard ADDC without Carry bit set
57
        mov     #0x0000, r2
58
        mov     #0x8888, r4
59
        mov     #0x9999, r7
60
        addc         r4, r7        ;# Add r4+r7+c (0x8888+0x9999=0x2221)
61
 
62
        # Test standard ADDC with Carry bit set
63
        mov     #0x0001, r2
64
        mov     #0xaaaa, r4
65
        mov     #0xbbbb, r8
66
        addc         r4, r8        ;# Add r4+r8+C (0xaaaa+0xbbbb=0x6666)
67
 
68
 
69
        mov     #0x1000, r15
70
 
71
 
72
        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
73
 
74
        # Test standard ADD with and without Carry bit set
75
        mov     #0x0000, r2
76
        mov     #0x4444, r4
77
        mov     #0x5555, r5
78
        add.b        r4, r5        ;# Add r4+r5 (0x0044+0x0055=0x0099)
79
 
80
        # Test standard ADD with and with Carry bit set
81
        mov     #0x0001, r2
82
        mov     #0x6666, r4
83
        mov     #0x6677, r6
84
        add.b        r4, r6        ;# Add r4+r6 (0x0066+0x0077=0x00dd)
85
 
86
 
87
        # Test standard ADDC with and without Carry bit set
88
        mov     #0x0000, r2
89
        mov     #0x8888, r4
90
        mov     #0x9999, r7
91
        addc.b       r4, r7        ;# Add r4+r5+c (0x0088+0x0099=0x0021)
92
 
93
        # Test standard ADDC with and with Carry bit set
94
        mov     #0x0001, r2
95
        mov     #0xaaaa, r4
96
        mov     #0xbbbb, r8
97
        addc.b       r4, r8        ;# Add r4+r6+C (0x00aa+0x00bb=0x0066)
98
 
99
 
100
        mov     #0x2000, r15
101
 
102
 
103
        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
104
 
105
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=0
106
        mov     #0x0444, r4        ;#
107
        mov     #0x0555, r5        ;#
108
        addc         r4, r5        ;# Add r4+r5 (0x0444+0x0555=0x0999)
109
        mov     #0x3000, r15
110
 
111
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=1
112
        mov     #0x0011, r4        ;#
113
        mov     #0xfff0, r5        ;#
114
        addc         r4, r5        ;# Add r4+r5 (0xfff0+0x0011=0x0001)
115
        mov     #0x3001, r15
116
 
117
        mov     #0x0000, r2        ;# V=0, N=0, Z=1, C=0
118
        mov     #0x0000, r4        ;#
119
        mov     #0x0000, r5        ;#
120
        addc         r4, r5        ;# Add r4+r5 (0x0000+0x0000=0x0000)
121
        mov     #0x3002, r15
122
 
123
        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=0
124
        mov     #0xff00, r4        ;#
125
        mov     #0x0010, r5        ;#
126
        addc         r4, r5        ;# Add r4+r5 (0xff00+0x0010=0xff10)
127
        mov     #0x3003, r15
128
 
129
        mov     #0x0000, r2        ;# V=1, N=1, Z=0, C=0
130
        mov     #0x7fff, r4        ;#
131
        mov     #0x0010, r5        ;#
132
        addc         r4, r5        ;# Add r4+r5 (0x7fff+0x0010=0x800f)
133
        mov     #0x3004, r15
134
 
135
        mov     #0x0000, r2        ;# V=1, N=0, Z=0, C=1
136
        mov     #0xff00, r4        ;#
137
        mov     #0x8000, r5        ;#
138
        addc         r4, r5        ;# Add r4+r5 (0xff00+0x8000=0x7f00)
139
        mov     #0x3005, r15
140
 
141
 
142
        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
143
 
144
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=0
145
        mov     #0xaa04, r4        ;#
146
        mov     #0x6605, r5        ;#
147
        addc.b       r4, r5        ;# Add r4+r5 (0xaa04+0x6605=0x0009)
148
        mov     #0x4000, r15
149
 
150
        mov     #0x0000, r2        ;# V=0, N=0, Z=0, C=1
151
        mov     #0xaa11, r4        ;#
152
        mov     #0x66f0, r5        ;#
153
        addc.b       r4, r5        ;# Add r4+r5 (0x0011+0x00f0=0x0001)
154
        mov     #0x4001, r15
155
 
156
        mov     #0x0000, r2        ;# V=0, N=0, Z=1, C=0
157
        mov     #0xaa00, r4        ;#
158
        mov     #0x6600, r5        ;#
159
        addc.b       r4, r5        ;# Add r4+r5 (0x0000+0x0000=0x0000)
160
        mov     #0x4002, r15
161
 
162
        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=0
163
        mov     #0xaaf0, r4        ;#
164
        mov     #0x6603, r5        ;#
165
        addc.b       r4, r5        ;# Add r4+r5 (0x00f0+0x0003=0x00f3)
166
        mov     #0x4003, r15
167
 
168
        mov     #0x0000, r2        ;# V=1, N=1, Z=0, C=0
169
        mov     #0x007f, r4        ;#
170
        mov     #0x0010, r5        ;#
171
        addc.b       r4, r5        ;# Add r4+r5 (0x007f+0x0010=0x008f)
172
        mov     #0x4004, r15
173
 
174
        mov     #0x0000, r2        ;# V=1, N=0, Z=0, C=1
175
        mov     #0x00ff, r4        ;#
176
        mov     #0x0080, r5        ;#
177
        addc.b       r4, r5        ;# Add r4+r5 (0x00ff+0x0080=0x007f)
178
        mov     #0x4005, r15
179
 
180
 
181
        /* ----------------------         END OF TEST        --------------- */
182
        mov     #0x5000, r15
183
end_of_test:
184
        nop
185
        br #0xffff
186
 
187
 
188
 
189
        /* ----------------------         INTERRUPT VECTORS  --------------- */
190
 
191
.section .vectors, "a"
192
.word end_of_test  ; Interrupt  0 (lowest priority)    
193
.word end_of_test  ; Interrupt  1                      
194
.word end_of_test  ; Interrupt  2                      
195
.word end_of_test  ; Interrupt  3                      
196
.word end_of_test  ; Interrupt  4                      
197
.word end_of_test  ; Interrupt  5                      
198
.word end_of_test  ; Interrupt  6                      
199
.word end_of_test  ; Interrupt  7                      
200
.word end_of_test  ; Interrupt  8                      
201
.word end_of_test  ; Interrupt  9                      
202
.word end_of_test  ; Interrupt 10                      Watchdog timer
203
.word end_of_test  ; Interrupt 11                      
204
.word end_of_test  ; Interrupt 12                      
205
.word end_of_test  ; Interrupt 13                      
206
.word end_of_test  ; Interrupt 14                      NMI
207
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.