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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_addc.v] - Blame information for rev 83

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Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                 TWO-OPERAND ARITHMETIC: ADDC[.B] INSTRUCTION              */
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/*---------------------------------------------------------------------------*/
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/* Test the ADDC[.B] instruction.                                            */
27 18 olivier.gi 
/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
32 19 olivier.gi 
/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
35 2 olivier.gi 
/*===========================================================================*/
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37 
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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      // ADDC (WORD MODE)
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      //--------------------------------------------------------
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      @(r15==16'h1000);
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      if (r5    !==16'h9999) tb_error("====== ADD without Carry =====");
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      if (r6    !==16'hdddd) tb_error("====== ADD with Carry =====");
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      if (r7    !==16'h2221) tb_error("====== ADDC without Carry =====");
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      if (r8    !==16'h6666) tb_error("====== ADDC with Carry =====");
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54 
 
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      // ADDC.B (BYTE MODE)
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      //--------------------------------------------------------
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      @(r15==16'h2000);
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      if (r5    !==16'h0099) tb_error("====== ADD.B  without Carry =====");
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      if (r6    !==16'h00dd) tb_error("====== ADD.B  with Carry =====");
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      if (r7    !==16'h0021) tb_error("====== ADDC.B without Carry =====");
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      if (r8    !==16'h0066) tb_error("====== ADDC.B with Carry =====");
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64 
 
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      // ADDC (WORD MODE): Check Flags
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      //--------------------------------------------------------
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      @(r15==16'h3000);
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      if (r2    !==16'h0000) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=0, Z=0, C=0 =====");
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      if (r5    !==16'h0999) tb_error("====== ADDC FLAG: Result check error: V=0, N=0, Z=0, C=0 =====");
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      @(r15==16'h3001);
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      if (r2    !==16'h0001) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=0, Z=0, C=1 =====");
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      if (r5    !==16'h0001) tb_error("====== ADDC FLAG: Result check error: V=0, N=0, Z=0, C=1 =====");
75 
 
76 
      @(r15==16'h3002);
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      if (r2    !==16'h0002) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=0, Z=1, C=0 =====");
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      if (r5    !==16'h0000) tb_error("====== ADDC FLAG: Result check error: V=0, N=0, Z=1, C=0 =====");
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80 
      @(r15==16'h3003);
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      if (r2    !==16'h0004) tb_error("====== ADDC FLAG: Flag   check error: V=0, N=1, Z=0, C=0 =====");
82 
      if (r5    !==16'hff10) tb_error("====== ADDC FLAG: Result check error: V=0, N=1, Z=0, C=0 =====");
83 
 
84 
      @(r15==16'h3004);
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      if (r2    !==16'h0104) tb_error("====== ADDC FLAG: Flag   check error: V=1, N=1, Z=0, C=0 =====");
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      if (r5    !==16'h800f) tb_error("====== ADDC FLAG: Result check error: V=1, N=1, Z=0, C=0 =====");
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88 
      @(r15==16'h3005);
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      if (r2    !==16'h0101) tb_error("====== ADDC FLAG: Flag   check error: V=1, N=0, Z=0, C=1 =====");
90 
      if (r5    !==16'h7f00) tb_error("====== ADDC FLAG: Result check error: V=1, N=0, Z=0, C=1 =====");
91 
 
92 
 
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      // ADDC.B (BYTE MODE): Check Flags
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      //--------------------------------------------------------
95 
 
96 
      @(r15==16'h4000);
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      if (r2    !==16'h0000) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=0, Z=0, C=0 =====");
98 
      if (r5    !==16'h0009) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=0, Z=0, C=0 =====");
99 
 
100 
      @(r15==16'h4001);
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      if (r2    !==16'h0001) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=0, Z=0, C=1 =====");
102 
      if (r5    !==16'h0001) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=0, Z=0, C=1 =====");
103 
 
104 
      @(r15==16'h4002);
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      if (r2    !==16'h0002) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=0, Z=1, C=0 =====");
106 
      if (r5    !==16'h0000) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=0, Z=1, C=0 =====");
107 
 
108 
      @(r15==16'h4003);
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      if (r2    !==16'h0004) tb_error("====== ADDC.B FLAG: Flag   check error: V=0, N=1, Z=0, C=0 =====");
110 
      if (r5    !==16'h00f3) tb_error("====== ADDC.B FLAG: Result check error: V=0, N=1, Z=0, C=0 =====");
111 
 
112 
      @(r15==16'h4004);
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      if (r2    !==16'h0104) tb_error("====== ADDC.B FLAG: Flag   check error: V=1, N=1, Z=0, C=0 =====");
114 
      if (r5    !==16'h008f) tb_error("====== ADDC.B FLAG: Result check error: V=1, N=1, Z=0, C=0 =====");
115 
 
116 
      @(r15==16'h4005);
117 
      if (r2    !==16'h0101) tb_error("====== ADDC.B FLAG: Flag   check error: V=1, N=0, Z=0, C=1 =====");
118 
      if (r5    !==16'h007f) tb_error("====== ADDC.B FLAG: Result check error: V=1, N=0, Z=0, C=1 =====");
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120 
 
121 
      stimulus_done = 1;
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   end
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