OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_bis.s43] - Blame information for rev 175

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                 TWO-OPERAND ARITHMETIC: BIS[.B] INSTRUCTION               */
25
/*---------------------------------------------------------------------------*/
26
/* Test the BIS[.B] instruction.                                             */
27 18 olivier.gi
/*                                                                           */
28
/* Author(s):                                                                */
29
/*             - Olivier Girard,    olgirard@gmail.com                       */
30
/*                                                                           */
31
/*---------------------------------------------------------------------------*/
32 19 olivier.gi
/* $Rev: 19 $                                                                */
33
/* $LastChangedBy: olivier.girard $                                          */
34
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
35 2 olivier.gi
/*===========================================================================*/
36
 
37
 
38
.global main
39
 
40
main:
41
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
42
 
43
        mov     #0x0000, r2
44
        mov     #0xaaaa, r4
45
        mov     #0x3333, r5
46
        bis          r4, r5        ;# Set bits r4 | r5 (0xaaaa | 0x3333=0xbbbb)
47
 
48
        mov     #0x0001, r2
49
        mov     #0x5555, r4
50
        mov     #0xcccc, r6
51
        bis          r4, r6        ;# Set bits r4 | r6 (0x5555 | 0xcccc=0xdddd)
52
 
53
        mov     #0x1000, r15
54
 
55
 
56
        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
57
 
58
        mov     #0x0000, r2
59
        mov     #0x4444, r4
60
        mov     #0x1111, r5
61
        bis.b        r4, r5        ;# Set bits r4 | r5 (0x4444 | 0x1111=0x0055)
62
 
63
        mov     #0x0001, r2
64
        mov     #0x8888, r4
65
        mov     #0x2222, r6
66
        bis.b        r4, r6        ;# Set bits r4 | r6 (0x8888 | 0x2222=0x00aa)
67
 
68
        mov     #0x2000, r15
69
 
70
 
71
        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
72
        #
73
        # Make sure Flags are unaffected by instruction
74
        #
75
 
76
        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
77
        mov     #0x0aaa, r4        ;#
78
        mov     #0x0666, r5        ;#
79
        bis          r4, r5        ;# Set bits r4 | r5 (0x0aaa | 0x0666=0x0eee)
80
        mov     #0x3000, r15
81
 
82
        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
83
        mov     #0x0aaa, r4        ;#
84
        mov     #0x0666, r5        ;#
85
        bis          r4, r5        ;# Set bits r4 | r5 (0x0aaa | 0x0666=0x0eee)
86
        mov     #0x3001, r15
87
 
88
 
89
        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
90
        #
91
        # Make sure Flags are unaffected by instruction
92
        #
93
 
94
        mov     #0x0005, r2        ;# V=0, N=1, Z=0, C=1
95
        mov     #0x550a, r4        ;#
96
        mov     #0x6606, r5        ;#
97
        bis.b        r4, r5        ;# Set bits r4 | r5 (0x000a | 0x0006=0x000e)
98
        mov     #0x4000, r15
99
 
100
        mov     #0x0102, r2        ;# V=1, N=0, Z=1, C=0
101
        mov     #0x330a, r4        ;#
102
        mov     #0x9906, r5        ;#
103
        bis.b        r4, r5        ;# Set bits r4 | r5 (0x000a | 0x0006=0x000e)
104
        mov     #0x4001, r15
105
 
106
 
107
 
108
        /* ----------------------         END OF TEST        --------------- */
109
        mov      #0x5000, r15
110
end_of_test:
111
        nop
112
        br #0xffff
113
 
114
 
115
        /* ----------------------         INTERRUPT VECTORS  --------------- */
116
 
117
.section .vectors, "a"
118
.word end_of_test  ; Interrupt  0 (lowest priority)    
119
.word end_of_test  ; Interrupt  1                      
120
.word end_of_test  ; Interrupt  2                      
121
.word end_of_test  ; Interrupt  3                      
122
.word end_of_test  ; Interrupt  4                      
123
.word end_of_test  ; Interrupt  5                      
124
.word end_of_test  ; Interrupt  6                      
125
.word end_of_test  ; Interrupt  7                      
126
.word end_of_test  ; Interrupt  8                      
127
.word end_of_test  ; Interrupt  9                      
128
.word end_of_test  ; Interrupt 10                      Watchdog timer
129
.word end_of_test  ; Interrupt 11                      
130
.word end_of_test  ; Interrupt 12                      
131
.word end_of_test  ; Interrupt 13                      
132
.word end_of_test  ; Interrupt 14                      NMI
133
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.