OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [two-op_bit.s43] - Blame information for rev 200

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                 TWO-OPERAND ARITHMETIC: BIT[.B] INSTRUCTION               */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the BIT[.B] instruction.                                             */
27 18 olivier.gi 
/*                                                                           */
28 
/* Author(s):                                                                */
29 
/*             - Olivier Girard,    olgirard@gmail.com                       */
30 
/*                                                                           */
31 
/*---------------------------------------------------------------------------*/
32 19 olivier.gi 
/* $Rev: 19 $                                                                */
33 
/* $LastChangedBy: olivier.girard $                                          */
34 
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
35 2 olivier.gi 
/*===========================================================================*/
36 
 
37 
 
38 
.global main
39 
 
40 
main:
41 
        /* -------------- TEST INSTRUCTION IN WORD MODE ------------------- */
42 
 
43 
        mov     #0x0000, r2
44 
        mov     #0x3333, r4
45 
        mov     #0x8888, r5
46 
        bit          r4, r5        ;# Test bits r5 & r4 (0x8888 & 0x3333)
47 
 
48 
        mov     #0x0001, r2
49 
        mov     #0x5555, r4
50 
        mov     #0x9999, r6
51 
        bit          r4, r6        ;# Test bits r6 & r4 (0x9999 & 0x5555)
52 
 
53 
        mov     #0x1000, r15
54 
 
55 
 
56 
        /* -------------- TEST INSTRUCTION IN BYTE MODE ------------------- */
57 
 
58 
        mov     #0x0000, r2
59 
        mov     #0x3333, r4
60 
        mov     #0x8888, r5
61 
        bit.b        r4, r5        ;# Test bits r5 & r4 (0x0088 & 0x0033)
62 
 
63 
        mov     #0x0001, r2
64 
        mov     #0x5555, r4
65 
        mov     #0x9999, r6
66 
        bit.b        r4, r6        ;# Test bits r6 & r4 (0x0099 & 0x0055)
67 
 
68 
        mov     #0x2000, r15
69 
 
70 
 
71 
        /* ------------------ TEST FLAGS IN WORD MODE ---------------------- */
72 
 
73 
        mov     #0x0100, r2        ;# V=0, N=0, Z=0, C=1
74 
        mov     #0x0aaa, r4        ;#
75 
        mov     #0x0666, r5        ;#
76 
        bit          r4, r5        ;# Test bits r5 & r4 (0x0666 & 0x0aaa)
77 
        mov     #0x3000, r15
78 
 
79 
        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=1
80 
        mov     #0x8444, r4        ;#
81 
        mov     #0x8555, r5        ;#
82 
        bit          r4, r5        ;# Test bits r5 & r4 (0x8555 & 0x8444)
83 
        mov     #0x3001, r15
84 
 
85 
        mov     #0x0100, r2        ;# V=0, N=0, Z=1, C=0
86 
        mov     #0x0aaa, r4        ;#
87 
        mov     #0x0555, r5        ;#
88 
        bit          r4, r5        ;# Test bits r5 & r4 (0x0555 & 0x0aaa)
89 
        mov     #0x3002, r15
90 
 
91 
 
92 
        /* ------------------ TEST FLAGS IN BYTE MODE --------------------- */
93 
 
94 
        mov     #0x0100, r2        ;# V=0, N=0, Z=0, C=1
95 
        mov     #0x800a, r4        ;#
96 
        mov     #0x8006, r5        ;#
97 
        bit.b        r4, r5        ;# Test bits r5 & r4 (0x0006 & 0x000a)
98 
        mov     #0x4000, r15
99 
 
100 
        mov     #0x0000, r2        ;# V=0, N=1, Z=0, C=1
101 
        mov     #0x0084, r4        ;#
102 
        mov     #0x0085, r5        ;#
103 
        bit.b        r4, r5        ;# Test bits r5 & r4 (0x0004 & 0x0005)
104 
        mov     #0x4001, r15
105 
 
106 
        mov     #0x0100, r2        ;# V=0, N=0, Z=1, C=0
107 
        mov     #0x4455, r4        ;#
108 
        mov     #0x77aa, r5        ;#
109 
        bit.b        r4, r5        ;# Test bits r5 & r4 (0x0055 & 0x00aa)
110 
        mov     #0x4002, r15
111 
 
112 
 
113 
        /* ----------------------         END OF TEST        --------------- */
114 
        mov      #0x5000, r15
115 
end_of_test:
116 
        nop
117 
        br #0xffff
118 
 
119 
 
120 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
121 
 
122 
.section .vectors, "a"
123 
.word end_of_test  ; Interrupt  0 (lowest priority)
124 
.word end_of_test  ; Interrupt  1
125 
.word end_of_test  ; Interrupt  2
126 
.word end_of_test  ; Interrupt  3
127 
.word end_of_test  ; Interrupt  4
128 
.word end_of_test  ; Interrupt  5
129 
.word end_of_test  ; Interrupt  6
130 
.word end_of_test  ; Interrupt  7
131 
.word end_of_test  ; Interrupt  8
132 
.word end_of_test  ; Interrupt  9
133 
.word end_of_test  ; Interrupt 10                      Watchdog timer
134 
.word end_of_test  ; Interrupt 11
135 
.word end_of_test  ; Interrupt 12
136 
.word end_of_test  ; Interrupt 13
137 
.word end_of_test  ; Interrupt 14                      NMI
138 
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.