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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.s43] - Blame information for rev 18

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Clock source selection.                          */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   BCSCTL1, 0x0057
.set   BCSCTL2, 0x0058
 
.set   IE1,    0x0000
.set   IFG1,   0x0002
.set   WDTCTL, 0x0120
 
WAIT_FUNC:
        dec r14
        jnz WAIT_FUNC
        ret
 
main:
 
        /* -------   WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2      ------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b   #0x01,   &IE1
 
        mov.b   #0x02, &BCSCTL2	  ;# SMCLK = MCLK/2
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
        mov   #0x0001, r15
 
        mov   #0x0170, r14
        call  #WAIT_FUNC
 
        mov   #0x1000, r15
 
 
        /* -------   WATCHDOG TEST INTERVAL MODE /64 - ACLK        ------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b   #0x01,   &IE1
 
        mov.b   #0x00, &BCSCTL1	  ;# ACLK = LFXTCLK/1
        mov   #0x5a1f, &WDTCTL	  ;# Enable interval mode /64 & clear counter
        mov   #0x1001, r15
 
        mov   #0x1000, r14
        call  #WAIT_FUNC
 
        mov   #0x2000, r15
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
WDOG_VECTOR:
        xor  #0x0001, r5        ; # Toggle r5[0] for testbench stimulus check
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Clock source selection. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 17 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38			`.global main`
39
40			`.set BCSCTL1, 0x0057`
41			`.set BCSCTL2, 0x0058`
42
43			`.set IE1, 0x0000`
44			`.set IFG1, 0x0002`
45			`.set WDTCTL, 0x0120`
46
47			`WAIT_FUNC:`
48			`dec r14`
49			`jnz WAIT_FUNC`
50			`ret`
51
52			`main:`
53
54			`/* ------- WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2 ------ */`
55
56			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
57			`eint`
58			`bis.b #0x01, &IE1`
59
60			`mov.b #0x02, &BCSCTL2 ;# SMCLK = MCLK/2`
61			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
62			`mov #0x0001, r15`
63
64			`mov #0x0170, r14`
65			`call #WAIT_FUNC`
66
67			`mov #0x1000, r15`
68
69
70			`/* ------- WATCHDOG TEST INTERVAL MODE /64 - ACLK ------ */`
71
72			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
73			`eint`
74			`bis.b #0x01, &IE1`
75
76			`mov.b #0x00, &BCSCTL1 ;# ACLK = LFXTCLK/1`
77			`mov #0x5a1f, &WDTCTL ;# Enable interval mode /64 & clear counter`
78			`mov #0x1001, r15`
79
80			`mov #0x1000, r14`
81			`call #WAIT_FUNC`
82
83			`mov #0x2000, r15`
84
85
86
87			`/* ---------------------- END OF TEST --------------- */`
88			`end_of_test:`
89			`nop`
90			`br #0xffff`
91
92
93			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
94
95			`WDOG_VECTOR:`
96			`xor #0x0001, r5 ; # Toggle r5[0] for testbench stimulus check`
97			`reti`
98
99
100			`/* ---------------------- INTERRUPT VECTORS --------------- */`
101
102			`.section .vectors, "a"`
103			`.word end_of_test ; Interrupt 0 (lowest priority)`
104			`.word end_of_test ; Interrupt 1`
105			`.word end_of_test ; Interrupt 2`
106			`.word end_of_test ; Interrupt 3`
107			`.word end_of_test ; Interrupt 4`
108			`.word end_of_test ; Interrupt 5`
109			`.word end_of_test ; Interrupt 6`
110			`.word end_of_test ; Interrupt 7`
111			`.word end_of_test ; Interrupt 8`
112			`.word end_of_test ; Interrupt 9`
113			`.word WDOG_VECTOR ; Interrupt 10 Watchdog timer`
114			`.word end_of_test ; Interrupt 11`
115			`.word end_of_test ; Interrupt 12`
116			`.word end_of_test ; Interrupt 13`
117			`.word end_of_test ; Interrupt 14 NMI`
118			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.s43] - Blame information for rev 18