OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.s43] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            WATCHDOG TIMER                                 */
25
/*---------------------------------------------------------------------------*/
26
/* Test the Watdog timer:                                                    */
27
/*                        - Clock source selection.                          */
28 18 olivier.gi
/*                                                                           */
29
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32
/*---------------------------------------------------------------------------*/
33 19 olivier.gi
/* $Rev: 141 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
36 2 olivier.gi
/*===========================================================================*/
37
 
38 141 olivier.gi
.include "pmem_defs.asm"
39
 
40 2 olivier.gi
.global main
41
 
42
WAIT_FUNC:
43
        dec r14
44
        jnz WAIT_FUNC
45
        ret
46
 
47
main:
48
 
49
        /* -------   WATCHDOG TEST INTERVAL MODE /64 - SMCLK /2      ------ */
50
 
51 111 olivier.gi
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
52 2 olivier.gi
        eint
53
        bis.b   #0x01,   &IE1
54
 
55
        mov.b   #0x02, &BCSCTL2	  ;# SMCLK = MCLK/2
56
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
57
        mov   #0x0001, r15
58
 
59 134 olivier.gi
        mov   #0x0470, r14
60 2 olivier.gi
        call  #WAIT_FUNC
61
 
62
        mov   #0x1000, r15
63 134 olivier.gi
        mov.b   #0x00, &BCSCTL2	  ;# SMCLK = MCLK
64 2 olivier.gi
 
65
 
66
        /* -------   WATCHDOG TEST INTERVAL MODE /64 - ACLK        ------ */
67
 
68 111 olivier.gi
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
69 2 olivier.gi
        eint
70
        bis.b   #0x01,   &IE1
71
 
72
        mov.b   #0x00, &BCSCTL1	  ;# ACLK = LFXTCLK/1
73
        mov   #0x5a1f, &WDTCTL	  ;# Enable interval mode /64 & clear counter
74
        mov   #0x1001, r15
75
 
76
        mov   #0x1000, r14
77
        call  #WAIT_FUNC
78
 
79
        mov   #0x2000, r15
80
 
81
 
82
 
83
        /* ----------------------         END OF TEST        --------------- */
84
end_of_test:
85
        nop
86
        br #0xffff
87
 
88
 
89
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
90
 
91
WDOG_VECTOR:
92
        xor  #0x0001, r5        ; # Toggle r5[0] for testbench stimulus check
93
        reti
94
 
95
 
96
        /* ----------------------         INTERRUPT VECTORS  --------------- */
97
 
98
.section .vectors, "a"
99
.word end_of_test  ; Interrupt  0 (lowest priority)    
100
.word end_of_test  ; Interrupt  1                      
101
.word end_of_test  ; Interrupt  2                      
102
.word end_of_test  ; Interrupt  3                      
103
.word end_of_test  ; Interrupt  4                      
104
.word end_of_test  ; Interrupt  5                      
105
.word end_of_test  ; Interrupt  6                      
106
.word end_of_test  ; Interrupt  7                      
107
.word end_of_test  ; Interrupt  8                      
108
.word end_of_test  ; Interrupt  9                      
109
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
110
.word end_of_test  ; Interrupt 11                      
111
.word end_of_test  ; Interrupt 12                      
112
.word end_of_test  ; Interrupt 13                      
113
.word end_of_test  ; Interrupt 14                      NMI
114
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.