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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.v] - Blame information for rev 200

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Clock source selection.                          */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 180 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $          */
/*===========================================================================*/
 
`define LONG_TIMEOUT
 
integer mclk_counter;
always @ (posedge mclk)
  mclk_counter <=  mclk_counter+1;
 
integer r5_counter;
always @ (posedge r5[0] or negedge r5[0])
  r5_counter <=  r5_counter+1;
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
 
`ifdef WATCHDOG
 
      // WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2
      //--------------------------------------------------------
 
      @(r15 === 16'h0001);
      @(posedge r5[0]);
      @(negedge mclk);
      mclk_counter = 0;
      r5_counter   = 0;
      repeat(1024) @(negedge mclk);
      if (mclk_counter !== 1024)        tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");
   `ifdef ASIC_CLOCKING
     `ifdef WATCHDOG_MUX
        `ifdef SMCLK_DIVIDER
            if (r5_counter   !== 7)     tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");
        `else
            if (r5_counter   !== 14)    tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");
        `endif
     `else
        `ifdef WATCHDOG_NOMUX_ACLK
           `ifdef LFXT_DOMAIN
               if (r5_counter   !== 0)  tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 4 =====");
           `else
               if (r5_counter   !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 5 =====");
           `endif
        `else
           `ifdef SMCLK_DIVIDER
               if (r5_counter   !== 7)  tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 6 =====");
           `else
               if (r5_counter   !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 7 =====");
           `endif
        `endif
     `endif
   `else
      if (r5_counter   !== 8)           tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 8 =====");
   `endif
 
 
      // WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1
      //--------------------------------------------------------
 
      @(r15 === 16'h1001);
      @(negedge r5[0]);
      @(negedge mclk);
      mclk_counter = 0;
      r5_counter   = 0;
      repeat(7815) @(negedge mclk);
      if (mclk_counter !== 7815)         tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");
   `ifdef ASIC_CLOCKING
     `ifdef WATCHDOG_MUX
            if (r5_counter      !== 4)   tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");
     `else
        `ifdef WATCHDOG_NOMUX_ACLK
           `ifdef LFXT_DOMAIN
               if (r5_counter   !== 4)   tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 3 =====");
           `else
               if (r5_counter   !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 4 =====");
           `endif
        `else
             if (r5_counter     !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 5 =====");
        `endif
     `endif
   `else
      if (r5_counter   !== 4)            tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 6 =====");
   `endif
 
`else
      $display(" ===============================================");
      $display("|               SIMULATION SKIPPED              |");
      $display("|         (the Watchdog is not included)        |");
      $display(" ===============================================");
      $finish;
`endif
 
      stimulus_done = 1;
   end
 

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Clock source selection. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33	19	olivier.gi	`/* $Rev: 180 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2013-02-25 22:23:18 +0100 (Mon, 25 Feb 2013) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38			`define LONG_TIMEOUT
39
40			`integer mclk_counter;`
41			`always @ (posedge mclk)`
42			`mclk_counter <= mclk_counter+1;`
43
44			`integer r5_counter;`
45			`always @ (posedge r5[0] or negedge r5[0])`
46			`r5_counter <= r5_counter+1;`
47
48			`initial`
49			`begin`
50			`$display(" ===============================================");`
51			`$display("\| START SIMULATION \|");`
52			`$display(" ===============================================");`
53			`repeat(5) @(posedge mclk);`
54			`stimulus_done = 0;`
55
56	134	olivier.gi	`ifdef WATCHDOG
57	2	olivier.gi
58			`// WATCHDOG TEST INTERVAL MODE /64 - SMCLK == MCLK/2`
59			`//--------------------------------------------------------`
60
61			`@(r15 === 16'h0001);`
62			`@(posedge r5[0]);`
63			`@(negedge mclk);`
64			`mclk_counter = 0;`
65			`r5_counter = 0;`
66			`repeat(1024) @(negedge mclk);`
67	134	olivier.gi	`if (mclk_counter !== 1024) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 1 =====");`
68	180	olivier.gi	`ifdef ASIC_CLOCKING
69	134	olivier.gi	`ifdef WATCHDOG_MUX
70			`ifdef SMCLK_DIVIDER
71			`if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 2 =====");`
72			`else
73			`if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 3 =====");`
74			`endif
75			`else
76			`ifdef WATCHDOG_NOMUX_ACLK
77			`ifdef LFXT_DOMAIN
78			`if (r5_counter !== 0) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 4 =====");`
79			`else
80			`if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 5 =====");`
81			`endif
82			`else
83			`ifdef SMCLK_DIVIDER
84			`if (r5_counter !== 7) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 6 =====");`
85			`else
86			`if (r5_counter !== 14) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 7 =====");`
87			`endif
88			`endif
89			`endif
90			`else
91			`if (r5_counter !== 8) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - SMCLK - TEST 8 =====");`
92			`endif
93	2	olivier.gi
94	134	olivier.gi
95	2	olivier.gi	`// WATCHDOG TEST INTERVAL MODE /64 - ACLK == LFXTCLK/1`
96			`//--------------------------------------------------------`
97
98			`@(r15 === 16'h1001);`
99			`@(negedge r5[0]);`
100			`@(negedge mclk);`
101			`mclk_counter = 0;`
102			`r5_counter = 0;`
103	85	olivier.gi	`repeat(7815) @(negedge mclk);`
104	134	olivier.gi	`if (mclk_counter !== 7815) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 1 =====");`
105	180	olivier.gi	`ifdef ASIC_CLOCKING
106	134	olivier.gi	`ifdef WATCHDOG_MUX
107			`if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 2 =====");`
108			`else
109			`ifdef WATCHDOG_NOMUX_ACLK
110			`ifdef LFXT_DOMAIN
111			`if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 3 =====");`
112			`else
113			`if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 4 =====");`
114			`endif
115			`else
116			`if (r5_counter !== 122) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 5 =====");`
117			`endif
118			`endif
119			`else
120			`if (r5_counter !== 4) tb_error("====== WATCHDOG TEST INTERVAL MODE /64 - ACLK - TEST 6 =====");`
121			`endif
122	2	olivier.gi
123	134	olivier.gi	`else
124			`$display(" ===============================================");`
125			`$display("\| SIMULATION SKIPPED \|");`
126			`$display("\| (the Watchdog is not included) \|");`
127			`$display(" ===============================================");`
128			`$finish;`
129			`endif
130	2	olivier.gi
131			`stimulus_done = 1;`
132			`end`
133

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_clkmux.v] - Blame information for rev 200