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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Blame information for rev 111

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Interval timer mode.                             */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 111 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $          */
/*===========================================================================*/
 
.global main
 
.set   DMEM_BASE, (__data_start     )
.set   DMEM_200,  (__data_start+0x00)
.set   DMEM_250,  (__data_start+0x50)
 
.set   IE1,    0x0000
.set   IFG1,   0x0002
.set   WDTCTL, 0x0120
 
 
main:
 
        /* --------------   WATCHDOG TEST:  RD/WR ACCESS    --------------- */
 
        mov  &WDTCTL, r4
        mov  #0x5aff, &WDTCTL
        mov  &WDTCTL, r5
        mov  #0x5a55, &WDTCTL
        mov  &WDTCTL, r6
        mov  #0x5aaa, &WDTCTL
        mov  &WDTCTL, r7
        mov  #0x5a00, &WDTCTL
        mov  &WDTCTL, r8
 
        mov  #0x1000, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /64  ------------ */
 
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0001, r5
wait_loop_64:
        inc   r4
        cmp   #0x3401, r5
        jne   wait_loop_64
 
        mov   #0x2000, r15
 
 
 
        bic.b #0x01,   &IE1	  ;# Disable watchdog interrupt
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
 
        mov   #0x0010, r4
        mov   #0x0002, r5
wait_loop_64_no_irq:
        dec   r4
        cmp   #0x0000, r4
        jne   wait_loop_64_no_irq
 
        mov    &IFG1, r6
        mov       r4, r7
        bic.b #0x01,   &IFG1	  ;# Clear flag
        mov    &IFG1, r8
 
        mov   #0x2001, r15
 
 
 
        mov   #0x5a9b, &WDTCTL	  ;# Enable interval mode /64 & clear counter & enable hold
 
        mov   #0x0020, r4
        mov   #0x0022, r5
wait_loop_64_no_irq_hold:
        dec   r4
        cmp   #0x0000, r4
        jne   wait_loop_64_no_irq_hold
 
        mov    &IFG1, r6
        mov       r4, r7
 
        mov   #0x2002, r15
 
 
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter / Check counter clear
        mov   #0x0033, r4
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear1:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear1
 
        mov   #0x5a1b, &WDTCTL	  ;# Clear counter
        mov    &IFG1, r6
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear2:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear2
 
        mov    &IFG1, r7	  ;# Don't Clear counter
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear3:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear3
 
        mov    &IFG1,   r8
        bic.b  #0x01,   &IFG1	  ;# Clear flag
 
 
        mov   #0x2003, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /512  ------------ */
 
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a1a, &WDTCTL	  ;# Enable interval mode /512 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0003, r5
wait_loop_512:
        inc   r4
        cmp   #0x3403, r5
        jne   wait_loop_512
 
        mov   #0x3000, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /8192  ------------ */
 
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a19, &WDTCTL	  ;# Enable interval mode /8192 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0004, r5
wait_loop_8192:
        inc   r4
        cmp   #0x3404, r5
        jne   wait_loop_8192
 
        mov   #0x4000, r15
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /32768  ------------ */
 
        mov   #DMEM_250, r1       ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a18, &WDTCTL	  ;# Enable interval mode /32768 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0005, r5
wait_loop_32768:
        inc   r4
        cmp   #0x3405, r5
        jne   wait_loop_32768
 
        mov   #0x5000, r15
 
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
WDOG_VECTOR:
        bis  #0x3400, r5
        mov    &IFG1, r6
        mov       r4, r7
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Blame information for rev 111

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Interval timer mode. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33	19	olivier.gi	`/* $Rev: 111 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2011-05-20 22:39:02 +0200 (Fri, 20 May 2011) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38			`.global main`
39
40	111	olivier.gi	`.set DMEM_BASE, (__data_start )`
41			`.set DMEM_200, (__data_start+0x00)`
42			`.set DMEM_250, (__data_start+0x50)`
43
44	2	olivier.gi	`.set IE1, 0x0000`
45			`.set IFG1, 0x0002`
46			`.set WDTCTL, 0x0120`
47
48
49			`main:`
50
51			`/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */`
52
53			`mov &WDTCTL, r4`
54			`mov #0x5aff, &WDTCTL`
55			`mov &WDTCTL, r5`
56			`mov #0x5a55, &WDTCTL`
57			`mov &WDTCTL, r6`
58			`mov #0x5aaa, &WDTCTL`
59			`mov &WDTCTL, r7`
60			`mov #0x5a00, &WDTCTL`
61			`mov &WDTCTL, r8`
62
63			`mov #0x1000, r15`
64
65
66			`/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */`
67
68	111	olivier.gi	`mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts`
69	2	olivier.gi	`eint`
70			`bis.b #0x01, &IE1`
71
72			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
73
74			`mov #0x0000, r4`
75			`mov #0x0001, r5`
76			`wait_loop_64:`
77			`inc r4`
78			`cmp #0x3401, r5`
79			`jne wait_loop_64`
80
81			`mov #0x2000, r15`
82
83
84
85			`bic.b #0x01, &IE1 ;# Disable watchdog interrupt`
86
87			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
88
89			`mov #0x0010, r4`
90			`mov #0x0002, r5`
91			`wait_loop_64_no_irq:`
92			`dec r4`
93			`cmp #0x0000, r4`
94			`jne wait_loop_64_no_irq`
95
96			`mov &IFG1, r6`
97			`mov r4, r7`
98			`bic.b #0x01, &IFG1 ;# Clear flag`
99			`mov &IFG1, r8`
100
101			`mov #0x2001, r15`
102
103
104
105			`mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold`
106
107			`mov #0x0020, r4`
108			`mov #0x0022, r5`
109			`wait_loop_64_no_irq_hold:`
110			`dec r4`
111			`cmp #0x0000, r4`
112			`jne wait_loop_64_no_irq_hold`
113
114			`mov &IFG1, r6`
115			`mov r4, r7`
116
117			`mov #0x2002, r15`
118
119
120
121			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter / Check counter clear`
122			`mov #0x0033, r4`
123
124			`mov #0x000C, r5`
125			`wait_loop_64_no_irq_clear1:`
126			`dec r5`
127			`cmp #0x0000, r5`
128			`jne wait_loop_64_no_irq_clear1`
129
130			`mov #0x5a1b, &WDTCTL ;# Clear counter`
131			`mov &IFG1, r6`
132
133			`mov #0x000C, r5`
134			`wait_loop_64_no_irq_clear2:`
135			`dec r5`
136			`cmp #0x0000, r5`
137			`jne wait_loop_64_no_irq_clear2`
138
139			`mov &IFG1, r7 ;# Don't Clear counter`
140
141			`mov #0x000C, r5`
142			`wait_loop_64_no_irq_clear3:`
143			`dec r5`
144			`cmp #0x0000, r5`
145			`jne wait_loop_64_no_irq_clear3`
146
147			`mov &IFG1, r8`
148			`bic.b #0x01, &IFG1 ;# Clear flag`
149
150
151			`mov #0x2003, r15`
152
153
154			`/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */`
155
156	111	olivier.gi	`mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts`
157	2	olivier.gi	`eint`
158			`bis.b #0x01, &IE1`
159
160			`mov #0x5a1a, &WDTCTL ;# Enable interval mode /512 & clear counter`
161
162			`mov #0x0000, r4`
163			`mov #0x0003, r5`
164			`wait_loop_512:`
165			`inc r4`
166			`cmp #0x3403, r5`
167			`jne wait_loop_512`
168
169			`mov #0x3000, r15`
170
171
172			`/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */`
173
174	111	olivier.gi	`mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts`
175	2	olivier.gi	`eint`
176			`bis.b #0x01, &IE1`
177
178			`mov #0x5a19, &WDTCTL ;# Enable interval mode /8192 & clear counter`
179
180			`mov #0x0000, r4`
181			`mov #0x0004, r5`
182			`wait_loop_8192:`
183			`inc r4`
184			`cmp #0x3404, r5`
185			`jne wait_loop_8192`
186
187			`mov #0x4000, r15`
188
189
190
191			`/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */`
192
193	111	olivier.gi	`mov #DMEM_250, r1 ;# Initialize stack & Enable interrupts`
194	2	olivier.gi	`eint`
195			`bis.b #0x01, &IE1`
196
197			`mov #0x5a18, &WDTCTL ;# Enable interval mode /32768 & clear counter`
198
199			`mov #0x0000, r4`
200			`mov #0x0005, r5`
201			`wait_loop_32768:`
202			`inc r4`
203			`cmp #0x3405, r5`
204			`jne wait_loop_32768`
205
206			`mov #0x5000, r15`
207
208
209
210
211			`/* ---------------------- END OF TEST --------------- */`
212			`end_of_test:`
213			`nop`
214			`br #0xffff`
215
216
217			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
218
219			`WDOG_VECTOR:`
220			`bis #0x3400, r5`
221			`mov &IFG1, r6`
222			`mov r4, r7`
223			`reti`
224
225
226			`/* ---------------------- INTERRUPT VECTORS --------------- */`
227
228			`.section .vectors, "a"`
229			`.word end_of_test ; Interrupt 0 (lowest priority)`
230			`.word end_of_test ; Interrupt 1`
231			`.word end_of_test ; Interrupt 2`
232			`.word end_of_test ; Interrupt 3`
233			`.word end_of_test ; Interrupt 4`
234			`.word end_of_test ; Interrupt 5`
235			`.word end_of_test ; Interrupt 6`
236			`.word end_of_test ; Interrupt 7`
237			`.word end_of_test ; Interrupt 8`
238			`.word end_of_test ; Interrupt 9`
239			`.word WDOG_VECTOR ; Interrupt 10 Watchdog timer`
240			`.word end_of_test ; Interrupt 11`
241			`.word end_of_test ; Interrupt 12`
242			`.word end_of_test ; Interrupt 13`
243			`.word end_of_test ; Interrupt 14 NMI`
244			`.word main ; Interrupt 15 (highest priority) RESET`