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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Blame information for rev 18

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Interval timer mode.                             */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 17 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   IE1,    0x0000
.set   IFG1,   0x0002
.set   WDTCTL, 0x0120
 
 
main:
 
        /* --------------   WATCHDOG TEST:  RD/WR ACCESS    --------------- */
 
        mov  &WDTCTL, r4
        mov  #0x5aff, &WDTCTL
        mov  &WDTCTL, r5
        mov  #0x5a55, &WDTCTL
        mov  &WDTCTL, r6
        mov  #0x5aaa, &WDTCTL
        mov  &WDTCTL, r7
        mov  #0x5a00, &WDTCTL
        mov  &WDTCTL, r8
 
        mov  #0x1000, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /64  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0001, r5
wait_loop_64:
        inc   r4
        cmp   #0x3401, r5
        jne   wait_loop_64
 
        mov   #0x2000, r15
 
 
 
        bic.b #0x01,   &IE1	  ;# Disable watchdog interrupt
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter
 
        mov   #0x0010, r4
        mov   #0x0002, r5
wait_loop_64_no_irq:
        dec   r4
        cmp   #0x0000, r4
        jne   wait_loop_64_no_irq
 
        mov    &IFG1, r6
        mov       r4, r7
        bic.b #0x01,   &IFG1	  ;# Clear flag
        mov    &IFG1, r8
 
        mov   #0x2001, r15
 
 
 
        mov   #0x5a9b, &WDTCTL	  ;# Enable interval mode /64 & clear counter & enable hold
 
        mov   #0x0020, r4
        mov   #0x0022, r5
wait_loop_64_no_irq_hold:
        dec   r4
        cmp   #0x0000, r4
        jne   wait_loop_64_no_irq_hold
 
        mov    &IFG1, r6
        mov       r4, r7
 
        mov   #0x2002, r15
 
 
 
        mov   #0x5a1b, &WDTCTL	  ;# Enable interval mode /64 & clear counter / Check counter clear
        mov   #0x0033, r4
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear1:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear1
 
        mov   #0x5a1b, &WDTCTL	  ;# Clear counter
        mov    &IFG1, r6
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear2:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear2
 
        mov    &IFG1, r7	  ;# Don't Clear counter
 
        mov   #0x000C, r5
wait_loop_64_no_irq_clear3:
        dec   r5
        cmp   #0x0000, r5
        jne   wait_loop_64_no_irq_clear3
 
        mov    &IFG1,   r8
        bic.b  #0x01,   &IFG1	  ;# Clear flag
 
 
        mov   #0x2003, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /512  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a1a, &WDTCTL	  ;# Enable interval mode /512 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0003, r5
wait_loop_512:
        inc   r4
        cmp   #0x3403, r5
        jne   wait_loop_512
 
        mov   #0x3000, r15
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /8192  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a19, &WDTCTL	  ;# Enable interval mode /8192 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0004, r5
wait_loop_8192:
        inc   r4
        cmp   #0x3404, r5
        jne   wait_loop_8192
 
        mov   #0x4000, r15
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /32768  ------------ */
 
        mov   #0x0250, r1         ;# Initialize stack & Enable interrupts
        eint
        bis.b #0x01,   &IE1
 
        mov   #0x5a18, &WDTCTL	  ;# Enable interval mode /32768 & clear counter
 
        mov   #0x0000, r4
        mov   #0x0005, r5
wait_loop_32768:
        inc   r4
        cmp   #0x3405, r5
        jne   wait_loop_32768
 
        mov   #0x5000, r15
 
 
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
WDOG_VECTOR:
        bis  #0x3400, r5
        mov    &IFG1, r6
        mov       r4, r7
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.s43] - Blame information for rev 18

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Interval timer mode. */`
28	18	olivier.gi	`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 17 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38			`.global main`
39
40			`.set IE1, 0x0000`
41			`.set IFG1, 0x0002`
42			`.set WDTCTL, 0x0120`
43
44
45			`main:`
46
47			`/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */`
48
49			`mov &WDTCTL, r4`
50			`mov #0x5aff, &WDTCTL`
51			`mov &WDTCTL, r5`
52			`mov #0x5a55, &WDTCTL`
53			`mov &WDTCTL, r6`
54			`mov #0x5aaa, &WDTCTL`
55			`mov &WDTCTL, r7`
56			`mov #0x5a00, &WDTCTL`
57			`mov &WDTCTL, r8`
58
59			`mov #0x1000, r15`
60
61
62			`/* -------------- WATCHDOG TEST: INTERVAL MODE /64 ------------ */`
63
64			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
65			`eint`
66			`bis.b #0x01, &IE1`
67
68			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
69
70			`mov #0x0000, r4`
71			`mov #0x0001, r5`
72			`wait_loop_64:`
73			`inc r4`
74			`cmp #0x3401, r5`
75			`jne wait_loop_64`
76
77			`mov #0x2000, r15`
78
79
80
81			`bic.b #0x01, &IE1 ;# Disable watchdog interrupt`
82
83			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter`
84
85			`mov #0x0010, r4`
86			`mov #0x0002, r5`
87			`wait_loop_64_no_irq:`
88			`dec r4`
89			`cmp #0x0000, r4`
90			`jne wait_loop_64_no_irq`
91
92			`mov &IFG1, r6`
93			`mov r4, r7`
94			`bic.b #0x01, &IFG1 ;# Clear flag`
95			`mov &IFG1, r8`
96
97			`mov #0x2001, r15`
98
99
100
101			`mov #0x5a9b, &WDTCTL ;# Enable interval mode /64 & clear counter & enable hold`
102
103			`mov #0x0020, r4`
104			`mov #0x0022, r5`
105			`wait_loop_64_no_irq_hold:`
106			`dec r4`
107			`cmp #0x0000, r4`
108			`jne wait_loop_64_no_irq_hold`
109
110			`mov &IFG1, r6`
111			`mov r4, r7`
112
113			`mov #0x2002, r15`
114
115
116
117			`mov #0x5a1b, &WDTCTL ;# Enable interval mode /64 & clear counter / Check counter clear`
118			`mov #0x0033, r4`
119
120			`mov #0x000C, r5`
121			`wait_loop_64_no_irq_clear1:`
122			`dec r5`
123			`cmp #0x0000, r5`
124			`jne wait_loop_64_no_irq_clear1`
125
126			`mov #0x5a1b, &WDTCTL ;# Clear counter`
127			`mov &IFG1, r6`
128
129			`mov #0x000C, r5`
130			`wait_loop_64_no_irq_clear2:`
131			`dec r5`
132			`cmp #0x0000, r5`
133			`jne wait_loop_64_no_irq_clear2`
134
135			`mov &IFG1, r7 ;# Don't Clear counter`
136
137			`mov #0x000C, r5`
138			`wait_loop_64_no_irq_clear3:`
139			`dec r5`
140			`cmp #0x0000, r5`
141			`jne wait_loop_64_no_irq_clear3`
142
143			`mov &IFG1, r8`
144			`bic.b #0x01, &IFG1 ;# Clear flag`
145
146
147			`mov #0x2003, r15`
148
149
150			`/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */`
151
152			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
153			`eint`
154			`bis.b #0x01, &IE1`
155
156			`mov #0x5a1a, &WDTCTL ;# Enable interval mode /512 & clear counter`
157
158			`mov #0x0000, r4`
159			`mov #0x0003, r5`
160			`wait_loop_512:`
161			`inc r4`
162			`cmp #0x3403, r5`
163			`jne wait_loop_512`
164
165			`mov #0x3000, r15`
166
167
168			`/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */`
169
170			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
171			`eint`
172			`bis.b #0x01, &IE1`
173
174			`mov #0x5a19, &WDTCTL ;# Enable interval mode /8192 & clear counter`
175
176			`mov #0x0000, r4`
177			`mov #0x0004, r5`
178			`wait_loop_8192:`
179			`inc r4`
180			`cmp #0x3404, r5`
181			`jne wait_loop_8192`
182
183			`mov #0x4000, r15`
184
185
186
187			`/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */`
188
189			`mov #0x0250, r1 ;# Initialize stack & Enable interrupts`
190			`eint`
191			`bis.b #0x01, &IE1`
192
193			`mov #0x5a18, &WDTCTL ;# Enable interval mode /32768 & clear counter`
194
195			`mov #0x0000, r4`
196			`mov #0x0005, r5`
197			`wait_loop_32768:`
198			`inc r4`
199			`cmp #0x3405, r5`
200			`jne wait_loop_32768`
201
202			`mov #0x5000, r15`
203
204
205
206
207			`/* ---------------------- END OF TEST --------------- */`
208			`end_of_test:`
209			`nop`
210			`br #0xffff`
211
212
213			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
214
215			`WDOG_VECTOR:`
216			`bis #0x3400, r5`
217			`mov &IFG1, r6`
218			`mov r4, r7`
219			`reti`
220
221
222			`/* ---------------------- INTERRUPT VECTORS --------------- */`
223
224			`.section .vectors, "a"`
225			`.word end_of_test ; Interrupt 0 (lowest priority)`
226			`.word end_of_test ; Interrupt 1`
227			`.word end_of_test ; Interrupt 2`
228			`.word end_of_test ; Interrupt 3`
229			`.word end_of_test ; Interrupt 4`
230			`.word end_of_test ; Interrupt 5`
231			`.word end_of_test ; Interrupt 6`
232			`.word end_of_test ; Interrupt 7`
233			`.word end_of_test ; Interrupt 8`
234			`.word end_of_test ; Interrupt 9`
235			`.word WDOG_VECTOR ; Interrupt 10 Watchdog timer`
236			`.word end_of_test ; Interrupt 11`
237			`.word end_of_test ; Interrupt 12`
238			`.word end_of_test ; Interrupt 13`
239			`.word end_of_test ; Interrupt 14 NMI`
240			`.word main ; Interrupt 15 (highest priority) RESET`