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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_interval.v] - Blame information for rev 202

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Line No. Rev Author Line
1 2 olivier.gi 
/*===========================================================================*/
2 
/* Copyright (C) 2001 Authors                                                */
3 
/*                                                                           */
4 
/* This source file may be used and distributed without restriction provided */
5 
/* that this copyright statement is not removed from the file and that any   */
6 
/* derivative work contains the original copyright notice and the associated */
7 
/* disclaimer.                                                               */
8 
/*                                                                           */
9 
/* This source file is free software; you can redistribute it and/or modify  */
10 
/* it under the terms of the GNU Lesser General Public License as published  */
11 
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12 
/* (at your option) any later version.                                       */
13 
/*                                                                           */
14 
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15 
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16 
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17 
/* License for more details.                                                 */
18 
/*                                                                           */
19 
/* You should have received a copy of the GNU Lesser General Public License  */
20 
/* along with this source; if not, write to the Free Software Foundation,    */
21 
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22 
/*                                                                           */
23 
/*===========================================================================*/
24 
/*                            WATCHDOG TIMER                                 */
25 
/*---------------------------------------------------------------------------*/
26 
/* Test the Watdog timer:                                                    */
27 
/*                        - Interval timer mode.                             */
28 18 olivier.gi 
/*                                                                           */
29 
/* Author(s):                                                                */
30 
/*             - Olivier Girard,    olgirard@gmail.com                       */
31 
/*                                                                           */
32 
/*---------------------------------------------------------------------------*/
33 19 olivier.gi 
/* $Rev: 202 $                                                                */
34 
/* $LastChangedBy: olivier.girard $                                          */
35 
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
36 2 olivier.gi 
/*===========================================================================*/
37 202 olivier.gi 
 
38 2 olivier.gi 
`define LONG_TIMEOUT
39 
 
40 
initial
41 
   begin
42 
      $display(" ===============================================");
43 
      $display("|                 START SIMULATION              |");
44 
      $display(" ===============================================");
45 
      repeat(5) @(posedge mclk);
46 
      stimulus_done = 0;
47 
 
48 134 olivier.gi 
`ifdef WATCHDOG
49 2 olivier.gi 
 
50 
      // WATCHDOG TEST:  RD/WR ACCESS
51 
      //--------------------------------------------------------
52 
 
53 
      @(r15==16'h1000);
54 134 olivier.gi 
`ifdef NMI
55 
  `ifdef WATCHDOG_MUX
56 
      if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
57 
      if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 1) =====");
58 
      if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 1) =====");
59 
      if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 1) =====");
60 
      if (r8 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
61 
  `else
62 
    `ifdef WATCHDOG_NOMUX_ACLK
63 
      if (r4 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
64 
      if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 2) =====");
65 
      if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 2) =====");
66 
      if (r7 !== 16'h69a6) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a6 (CONFIG 2) =====");
67 
      if (r8 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
68 
    `else
69 
      if (r4 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
70 180 olivier.gi 
      `ifdef ASIC_CLOCKING
71 134 olivier.gi 
      if (r5 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) =====");
72 
      if (r6 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) =====");
73 
      if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) =====");
74 
      `else
75 
      if (r5 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 3) =====");
76 
      if (r6 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 3) =====");
77 
      if (r7 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3) =====");
78 
      `endif
79 
      if (r8 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
80 
    `endif
81 
  `endif
82 
`else
83 
  `ifdef WATCHDOG_MUX
84 
      if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
85 
      if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 4) =====");
86 
      if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 4) =====");
87 
      if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 4) =====");
88 
      if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
89 
  `else
90 
    `ifdef WATCHDOG_NOMUX_ACLK
91 
      if (r4 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
92 
      if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 5) =====");
93 
      if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 5) =====");
94 
      if (r7 !== 16'h6986) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6986 (CONFIG 5) =====");
95 
      if (r8 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
96 
    `else
97 
      if (r4 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
98 180 olivier.gi 
      `ifdef ASIC_CLOCKING
99 134 olivier.gi 
      if (r5 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) =====");
100 
      if (r6 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) =====");
101 
      if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) =====");
102 
      `else
103 
      if (r5 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 6) =====");
104 
      if (r6 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 6) =====");
105 
      if (r7 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6) =====");
106 
      `endif
107 
      if (r8 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
108 
    `endif
109 
  `endif
110 
`endif
111 
`ifdef NMI
112 
      if (r9 !== 16'h0010) tb_error("====== WATCHDOG RD/WR ACCESS: IFG1   != 0x10 =====");
113 
`else
114 
      if (r9 !== 16'h0000) tb_error("====== WATCHDOG RD/WR ACCESS: IFG1   != 0x00 =====");
115 
`endif
116 2 olivier.gi 
 
117 202 olivier.gi 
 
118 2 olivier.gi 
      // WATCHDOG TEST:  INTERVAL MODE /64
119 
      //--------------------------------------------------------
120 
 
121 
      @(r15==16'h2000);
122 
      if (r5 !== 16'h3401) tb_error("====== WATCHDOG INTERVAL MODE /64: R5 != 0x3401 =====");
123 
      if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64: R6 != 0x0000 =====");
124 180 olivier.gi 
`ifdef ASIC_CLOCKING
125 134 olivier.gi 
  `ifdef WATCHDOG_MUX
126 
      if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) =====");
127 
  `else
128 
    `ifdef WATCHDOG_NOMUX_ACLK
129 
      `ifdef ACLK_DIVIDER
130 
      if (r7 !== 16'h019F) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x019F (CONFIG 1) =====");
131 
      `else
132 
      if (r7 !== 16'h0199) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x0199 (CONFIG 1) =====");
133 
      `endif
134 
    `else
135 
      if (r7 !== 16'h000E) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000E (CONFIG 1) =====");
136 
    `endif
137 
  `endif
138 
`else
139 
      if (r7 !== 16'h000D) tb_error("====== WATCHDOG INTERVAL MODE /64: R7 != 0x000D (CONFIG 1) =====");
140 
`endif
141 202 olivier.gi 
 
142 2 olivier.gi 
      @(r15==16'h2001);
143 
      if (r5 !== 16'h0002) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R5 != 0x0002 =====");
144 
      if (r6 !== 16'h0001) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R6 != 0x0001 =====");
145 
      if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R7 != 0x0000 =====");
146 
      if (r8 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ: R8 != 0x0000 =====");
147 202 olivier.gi 
 
148 180 olivier.gi 
`ifdef ASIC_CLOCKING
149 134 olivier.gi 
  `ifdef WATCHDOG_MUX
150 
  `else
151 
    `ifdef WATCHDOG_NOMUX_ACLK
152 
      // From there, force the watchdog clock to DCO_CLK to speedup simulation
153 202 olivier.gi 
      force lfxt_clk = dco_clk;
154 134 olivier.gi 
    `endif
155 
  `endif
156 
`endif
157 2 olivier.gi 
 
158 
      @(r15==16'h2002);
159 
      if (r5 !== 16'h0022) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R5 != 0x0022 =====");
160 
      if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R6 != 0x0000 =====");
161 
      if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ HOLD: R7 != 0x0000 =====");
162 
 
163 
      @(r15==16'h2003);
164 
      if (r4 !== 16'h0033) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ CNT CLEAR: R4 != 0x0033 =====");
165 
      if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ CNT CLEAR: R6 != 0x0000 =====");
166 
      if (r7 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ CNT CLEAR: R7 != 0x0000 =====");
167 
      if (r8 !== 16'h0001) tb_error("====== WATCHDOG INTERVAL MODE /64 NO IRQ CNT CLEAR: R8 != 0x0001 =====");
168 
 
169 
      $display("Interval mode /64 mode test completed...");
170 202 olivier.gi 
 
171 
 
172 2 olivier.gi 
      // WATCHDOG TEST:  INTERVAL MODE /512
173 
      //--------------------------------------------------------
174 
 
175 
      @(r15==16'h3000);
176 
      if (r5 !== 16'h3403) tb_error("====== WATCHDOG INTERVAL MODE /512: R5 != 0x3403 =====");
177 
      if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /512: R6 != 0x0000 =====");
178 180 olivier.gi 
`ifdef ASIC_CLOCKING
179 134 olivier.gi 
      if (r7 !== 16'h0068) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0068 =====");
180 
`else
181 
      if (r7 !== 16'h0066) tb_error("====== WATCHDOG INTERVAL MODE /512: R7 != 0x0066 =====");
182 
`endif
183 2 olivier.gi 
 
184 
      $display("Interval mode /512 mode test completed...");
185 
 
186 202 olivier.gi 
 
187 2 olivier.gi 
      // WATCHDOG TEST:  INTERVAL MODE /8192
188 
      //--------------------------------------------------------
189 
 
190 
      @(r15==16'h4000);
191 
      if (r5 !== 16'h3404) tb_error("====== WATCHDOG INTERVAL MODE /8192: R5 != 0x3404 =====");
192 
      if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /8192: R6 != 0x0000 =====");
193 180 olivier.gi 
`ifdef ASIC_CLOCKING
194 134 olivier.gi 
      if (r7 !== 16'h0668) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0668 =====");
195 
`else
196 2 olivier.gi 
      if (r7 !== 16'h0667) tb_error("====== WATCHDOG INTERVAL MODE /8192: R7 != 0x0667 =====");
197 134 olivier.gi 
`endif
198 2 olivier.gi 
 
199 
      $display("Interval mode /8192 mode test completed...");
200 
 
201 202 olivier.gi 
 
202 2 olivier.gi 
      // WATCHDOG TEST:  INTERVAL MODE /32768
203 
      //--------------------------------------------------------
204 
 
205 
      @(r15==16'h5000);
206 
      if (r5 !== 16'h3405) tb_error("====== WATCHDOG INTERVAL MODE /32768: R5 != 0x3405 =====");
207 
      if (r6 !== 16'h0000) tb_error("====== WATCHDOG INTERVAL MODE /32768: R6 != 0x0000 =====");
208 180 olivier.gi 
`ifdef ASIC_CLOCKING
209 134 olivier.gi 
      if (r7 !== 16'h199B) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199B =====");
210 
`else
211 
      if (r7 !== 16'h199A) tb_error("====== WATCHDOG INTERVAL MODE /32768: R7 != 0x199A =====");
212 
`endif
213 2 olivier.gi 
 
214 
      $display("Interval mode /32768 mode test completed...");
215 
 
216 134 olivier.gi 
`else
217 202 olivier.gi 
      tb_skip_finish("|         (the Watchdog is not included)        |");
218 134 olivier.gi 
`endif
219 2 olivier.gi 
 
220 
      stimulus_done = 1;
221 
   end

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