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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.s43] - Blame information for rev 18

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Watchdog mode.                                   */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 18 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
.global main
 
.set   IE1,    0x0000
.set   IFG1,   0x0002
.set   WDTCTL, 0x0120
 
 
main:
 
        /* --------------   WATCHDOG TEST:  STARTUP SEQUENCE  --------------- */
 
        mov   &IFG1, r4       	;# Check if we come out of a watchdog reset
        cmp #0x0000, r4
        jeq   RD_WR_ACCESS
 
        mov &0x0250, r15        ;# If yes, check RAM variable to see where to go next
 
        cmp #0x0000, r15
        jeq   RESET_64
        cmp #0x1000, r15
        jeq   RESET_512
        cmp #0x2000, r15
        jeq   RESET_8192
        cmp #0x3000, r15
        jeq   RESET_32768
        cmp #0x4000, r15
        jeq   CHECK_32768
 
        jmp  end_of_test
 
 
        /* --------------   WATCHDOG TEST:  RD/WR ACCESS    --------------- */
RD_WR_ACCESS:
        mov  #0x0000, &0x0250
 
        mov  &WDTCTL, &0x0200
        mov  #0x5aff, &WDTCTL
        mov  &WDTCTL, &0x0202
        mov  #0x5a55, &WDTCTL
        mov  &WDTCTL, &0x0204
        mov  #0x5aaa, &WDTCTL
        mov  &WDTCTL, &0x0206
        mov  #0x5a00, &WDTCTL
        mov  &WDTCTL, &0x0208
 
        mov  #0xDEAD, &WDTCTL	 ;# Generate reset through wrong password
 
        jmp  end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  WATCHODG MODE /64  ------------ */
RESET_64:
        bic.b #0x01,   &IFG1
        mov   #0x1000, &0x0250
 
        mov   #0x5a0b, &WDTCTL	 ;# Enable watchdog mode /64 & clear counter
 
        mov   #0x0000, &0x0200
wait_loop_64:
        inc   &0x0200
        jmp   wait_loop_64
 
        jmp   end_of_test        ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /512  ------------ */
RESET_512:
        bic.b #0x01,   &IFG1
        mov   #0x2000, &0x0250
 
        mov   #0x5a0a, &WDTCTL	  ;# Enable watchdog mode /512 & clear counter
 
        mov   #0x0000, &0x0202
wait_loop_512:
        inc   &0x0202
        jmp   wait_loop_512
 
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /8192  ------------ */
RESET_8192:
        bic.b #0x01,   &IFG1
        mov   #0x3000, &0x0250
 
        mov   #0x5a09, &WDTCTL	  ;# Enable watchdog mode /8192 & clear counter
 
        mov   #0x0000, &0x0204
wait_loop_8192:
        inc   &0x0204
        jmp   wait_loop_8192
 
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
 
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /32768  ------------ */
RESET_32768:
        bic.b #0x01,   &IFG1
        mov   #0x4000, &0x0250
 
        mov   #0x5a08, &WDTCTL	  ;# Enable interval mode /32768 & clear counter
 
        mov   #0x0000, &0x0206
wait_loop_32768:
        inc   &0x0206
        jmp   wait_loop_32768
 
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
 
 
CHECK_32768:
        bic.b #0x01,   &IFG1
        mov   #0x5000, &0x0250
 
 
        /* ----------------------         END OF TEST        --------------- */
end_of_test:
        nop
        br #0xffff
 
 
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
 
WDOG_VECTOR:
        bis  #0x3400, r5
        mov    &IFG1, r6
        mov       r4, r7
        reti
 
 
        /* ----------------------         INTERRUPT VECTORS  --------------- */
 
.section .vectors, "a"
.word end_of_test  ; Interrupt  0 (lowest priority)    
.word end_of_test  ; Interrupt  1                      
.word end_of_test  ; Interrupt  2                      
.word end_of_test  ; Interrupt  3                      
.word end_of_test  ; Interrupt  4                      
.word end_of_test  ; Interrupt  5                      
.word end_of_test  ; Interrupt  6                      
.word end_of_test  ; Interrupt  7                      
.word end_of_test  ; Interrupt  8                      
.word end_of_test  ; Interrupt  9                      
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
.word end_of_test  ; Interrupt 11                      
.word end_of_test  ; Interrupt 12                      
.word end_of_test  ; Interrupt 13                      
.word end_of_test  ; Interrupt 14                      NMI
.word main         ; Interrupt 15 (highest priority)   RESET

Line No.	Rev	Author	Line
1	2	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Watchdog mode. */`
28	17	olivier.gi	`/* */`
29	18	olivier.gi	`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32	17	olivier.gi	`/---------------------------------------------------------------------------/`
33			`/* $Rev: 18 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:44:12 +0200 (Tue, 04 Aug 2009) $ */`
36	2	olivier.gi	`/===========================================================================/`
37
38			`.global main`
39
40			`.set IE1, 0x0000`
41			`.set IFG1, 0x0002`
42			`.set WDTCTL, 0x0120`
43
44
45			`main:`
46
47			`/* -------------- WATCHDOG TEST: STARTUP SEQUENCE --------------- */`
48
49			`mov &IFG1, r4 ;# Check if we come out of a watchdog reset`
50			`cmp #0x0000, r4`
51			`jeq RD_WR_ACCESS`
52
53			`mov &0x0250, r15 ;# If yes, check RAM variable to see where to go next`
54
55			`cmp #0x0000, r15`
56			`jeq RESET_64`
57			`cmp #0x1000, r15`
58			`jeq RESET_512`
59			`cmp #0x2000, r15`
60			`jeq RESET_8192`
61			`cmp #0x3000, r15`
62			`jeq RESET_32768`
63			`cmp #0x4000, r15`
64			`jeq CHECK_32768`
65
66			`jmp end_of_test`
67
68
69			`/* -------------- WATCHDOG TEST: RD/WR ACCESS --------------- */`
70			`RD_WR_ACCESS:`
71			`mov #0x0000, &0x0250`
72
73			`mov &WDTCTL, &0x0200`
74			`mov #0x5aff, &WDTCTL`
75			`mov &WDTCTL, &0x0202`
76			`mov #0x5a55, &WDTCTL`
77			`mov &WDTCTL, &0x0204`
78			`mov #0x5aaa, &WDTCTL`
79			`mov &WDTCTL, &0x0206`
80			`mov #0x5a00, &WDTCTL`
81			`mov &WDTCTL, &0x0208`
82
83			`mov #0xDEAD, &WDTCTL ;# Generate reset through wrong password`
84
85			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
86
87
88
89			`/* -------------- WATCHDOG TEST: WATCHODG MODE /64 ------------ */`
90			`RESET_64:`
91			`bic.b #0x01, &IFG1`
92			`mov #0x1000, &0x0250`
93
94			`mov #0x5a0b, &WDTCTL ;# Enable watchdog mode /64 & clear counter`
95
96			`mov #0x0000, &0x0200`
97			`wait_loop_64:`
98			`inc &0x0200`
99			`jmp wait_loop_64`
100
101			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
102
103
104
105			`/* -------------- WATCHDOG TEST: INTERVAL MODE /512 ------------ */`
106			`RESET_512:`
107			`bic.b #0x01, &IFG1`
108			`mov #0x2000, &0x0250`
109
110			`mov #0x5a0a, &WDTCTL ;# Enable watchdog mode /512 & clear counter`
111
112			`mov #0x0000, &0x0202`
113			`wait_loop_512:`
114			`inc &0x0202`
115			`jmp wait_loop_512`
116
117			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
118
119
120
121			`/* -------------- WATCHDOG TEST: INTERVAL MODE /8192 ------------ */`
122			`RESET_8192:`
123			`bic.b #0x01, &IFG1`
124			`mov #0x3000, &0x0250`
125
126			`mov #0x5a09, &WDTCTL ;# Enable watchdog mode /8192 & clear counter`
127
128			`mov #0x0000, &0x0204`
129			`wait_loop_8192:`
130			`inc &0x0204`
131			`jmp wait_loop_8192`
132
133			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
134
135
136
137			`/* -------------- WATCHDOG TEST: INTERVAL MODE /32768 ------------ */`
138			`RESET_32768:`
139			`bic.b #0x01, &IFG1`
140			`mov #0x4000, &0x0250`
141
142			`mov #0x5a08, &WDTCTL ;# Enable interval mode /32768 & clear counter`
143
144			`mov #0x0000, &0x0206`
145			`wait_loop_32768:`
146			`inc &0x0206`
147			`jmp wait_loop_32768`
148
149			`jmp end_of_test ;# Force end of test if watchdog reset don't happen`
150
151
152			`CHECK_32768:`
153			`bic.b #0x01, &IFG1`
154			`mov #0x5000, &0x0250`
155
156
157			`/* ---------------------- END OF TEST --------------- */`
158			`end_of_test:`
159			`nop`
160			`br #0xffff`
161
162
163			`/* ---------------------- INTERRUPT ROUTINES --------------- */`
164
165			`WDOG_VECTOR:`
166			`bis #0x3400, r5`
167			`mov &IFG1, r6`
168			`mov r4, r7`
169			`reti`
170
171
172			`/* ---------------------- INTERRUPT VECTORS --------------- */`
173
174			`.section .vectors, "a"`
175			`.word end_of_test ; Interrupt 0 (lowest priority)`
176			`.word end_of_test ; Interrupt 1`
177			`.word end_of_test ; Interrupt 2`
178			`.word end_of_test ; Interrupt 3`
179			`.word end_of_test ; Interrupt 4`
180			`.word end_of_test ; Interrupt 5`
181			`.word end_of_test ; Interrupt 6`
182			`.word end_of_test ; Interrupt 7`
183			`.word end_of_test ; Interrupt 8`
184			`.word end_of_test ; Interrupt 9`
185			`.word WDOG_VECTOR ; Interrupt 10 Watchdog timer`
186			`.word end_of_test ; Interrupt 11`
187			`.word end_of_test ; Interrupt 12`
188			`.word end_of_test ; Interrupt 13`
189			`.word end_of_test ; Interrupt 14 NMI`
190			`.word main ; Interrupt 15 (highest priority) RESET`

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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.s43] - Blame information for rev 18