OpenCores
URL https://opencores.org/ocsvn/openmsp430/openmsp430/trunk

Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.s43] - Blame information for rev 219

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
3
/*                                                                           */
4
/* This source file may be used and distributed without restriction provided */
5
/* that this copyright statement is not removed from the file and that any   */
6
/* derivative work contains the original copyright notice and the associated */
7
/* disclaimer.                                                               */
8
/*                                                                           */
9
/* This source file is free software; you can redistribute it and/or modify  */
10
/* it under the terms of the GNU Lesser General Public License as published  */
11
/* by the Free Software Foundation; either version 2.1 of the License, or    */
12
/* (at your option) any later version.                                       */
13
/*                                                                           */
14
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
15
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
16
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
17
/* License for more details.                                                 */
18
/*                                                                           */
19
/* You should have received a copy of the GNU Lesser General Public License  */
20
/* along with this source; if not, write to the Free Software Foundation,    */
21
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
22
/*                                                                           */
23
/*===========================================================================*/
24
/*                            WATCHDOG TIMER                                 */
25
/*---------------------------------------------------------------------------*/
26
/* Test the Watdog timer:                                                    */
27
/*                        - Watchdog mode.                                   */
28 17 olivier.gi
/*                                                                           */
29 18 olivier.gi
/* Author(s):                                                                */
30
/*             - Olivier Girard,    olgirard@gmail.com                       */
31
/*                                                                           */
32 17 olivier.gi
/*---------------------------------------------------------------------------*/
33
/* $Rev: 141 $                                                                */
34
/* $LastChangedBy: olivier.girard $                                          */
35
/* $LastChangedDate: 2012-05-05 23:22:06 +0200 (Sat, 05 May 2012) $          */
36 2 olivier.gi
/*===========================================================================*/
37
 
38 141 olivier.gi
.include "pmem_defs.asm"
39
 
40 2 olivier.gi
.global main
41
 
42
main:
43
 
44
        /* --------------   WATCHDOG TEST:  STARTUP SEQUENCE  --------------- */
45
 
46
        mov   &IFG1, r4       	;# Check if we come out of a watchdog reset
47
        cmp #0x0000, r4
48
        jeq   RD_WR_ACCESS
49
 
50 111 olivier.gi
        mov &DMEM_250, r15        ;# If yes, check RAM variable to see where to go next
51 2 olivier.gi
 
52
        cmp #0x0000, r15
53
        jeq   RESET_64
54
        cmp #0x1000, r15
55
        jeq   RESET_512
56
        cmp #0x2000, r15
57
        jeq   RESET_8192
58
        cmp #0x3000, r15
59
        jeq   RESET_32768
60
        cmp #0x4000, r15
61
        jeq   CHECK_32768
62
 
63
        jmp  end_of_test
64
 
65
 
66
        /* --------------   WATCHDOG TEST:  RD/WR ACCESS    --------------- */
67
RD_WR_ACCESS:
68 111 olivier.gi
        mov  #0x0000, &DMEM_250
69 2 olivier.gi
 
70 111 olivier.gi
        mov  &WDTCTL, &DMEM_200
71 2 olivier.gi
        mov  #0x5aff, &WDTCTL
72 111 olivier.gi
        mov  &WDTCTL, &DMEM_202
73 2 olivier.gi
        mov  #0x5a55, &WDTCTL
74 111 olivier.gi
        mov  &WDTCTL, &DMEM_204
75 2 olivier.gi
        mov  #0x5aaa, &WDTCTL
76 111 olivier.gi
        mov  &WDTCTL, &DMEM_206
77 2 olivier.gi
        mov  #0x5a00, &WDTCTL
78 111 olivier.gi
        mov  &WDTCTL, &DMEM_208
79 2 olivier.gi
 
80
        mov  #0xDEAD, &WDTCTL	 ;# Generate reset through wrong password
81
 
82
        jmp  end_of_test         ;# Force end of test if watchdog reset don't happen
83
 
84
 
85
 
86
        /* --------------   WATCHDOG TEST:  WATCHODG MODE /64  ------------ */
87
RESET_64:
88
        bic.b #0x01,   &IFG1
89 111 olivier.gi
        mov   #0x1000, &DMEM_250
90 2 olivier.gi
 
91
        mov   #0x5a0b, &WDTCTL	 ;# Enable watchdog mode /64 & clear counter
92
 
93 111 olivier.gi
        mov   #0x0000, &DMEM_200
94 2 olivier.gi
wait_loop_64:
95 111 olivier.gi
        inc   &DMEM_200
96 2 olivier.gi
        jmp   wait_loop_64
97
 
98
        jmp   end_of_test        ;# Force end of test if watchdog reset don't happen
99
 
100
 
101
 
102
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /512  ------------ */
103
RESET_512:
104
        bic.b #0x01,   &IFG1
105 111 olivier.gi
        mov   #0x2000, &DMEM_250
106 2 olivier.gi
 
107
        mov   #0x5a0a, &WDTCTL	  ;# Enable watchdog mode /512 & clear counter
108
 
109 111 olivier.gi
        mov   #0x0000, &DMEM_202
110 2 olivier.gi
wait_loop_512:
111 111 olivier.gi
        inc   &DMEM_202
112 2 olivier.gi
        jmp   wait_loop_512
113
 
114
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
115
 
116
 
117
 
118
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /8192  ------------ */
119
RESET_8192:
120
        bic.b #0x01,   &IFG1
121 111 olivier.gi
        mov   #0x3000, &DMEM_250
122 2 olivier.gi
 
123
        mov   #0x5a09, &WDTCTL	  ;# Enable watchdog mode /8192 & clear counter
124
 
125 111 olivier.gi
        mov   #0x0000, &DMEM_204
126 2 olivier.gi
wait_loop_8192:
127 111 olivier.gi
        inc   &DMEM_204
128 2 olivier.gi
        jmp   wait_loop_8192
129
 
130
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
131
 
132
 
133
 
134
        /* --------------   WATCHDOG TEST:  INTERVAL MODE /32768  ------------ */
135
RESET_32768:
136
        bic.b #0x01,   &IFG1
137 111 olivier.gi
        mov   #0x4000, &DMEM_250
138 2 olivier.gi
 
139
        mov   #0x5a08, &WDTCTL	  ;# Enable interval mode /32768 & clear counter
140
 
141 111 olivier.gi
        mov   #0x0000, &DMEM_206
142 2 olivier.gi
wait_loop_32768:
143 111 olivier.gi
        inc   &DMEM_206
144 2 olivier.gi
        jmp   wait_loop_32768
145
 
146
        jmp   end_of_test         ;# Force end of test if watchdog reset don't happen
147
 
148
 
149
CHECK_32768:
150
        bic.b #0x01,   &IFG1
151 111 olivier.gi
        mov   #0x5000, &DMEM_250
152 2 olivier.gi
 
153
 
154
        /* ----------------------         END OF TEST        --------------- */
155
end_of_test:
156
        nop
157
        br #0xffff
158
 
159
 
160
        /* ----------------------      INTERRUPT ROUTINES    --------------- */
161
 
162
WDOG_VECTOR:
163
        bis  #0x3400, r5
164
        mov    &IFG1, r6
165
        mov       r4, r7
166
        reti
167
 
168
 
169
        /* ----------------------         INTERRUPT VECTORS  --------------- */
170
 
171
.section .vectors, "a"
172
.word end_of_test  ; Interrupt  0 (lowest priority)    
173
.word end_of_test  ; Interrupt  1                      
174
.word end_of_test  ; Interrupt  2                      
175
.word end_of_test  ; Interrupt  3                      
176
.word end_of_test  ; Interrupt  4                      
177
.word end_of_test  ; Interrupt  5                      
178
.word end_of_test  ; Interrupt  6                      
179
.word end_of_test  ; Interrupt  7                      
180
.word end_of_test  ; Interrupt  8                      
181
.word end_of_test  ; Interrupt  9                      
182
.word WDOG_VECTOR  ; Interrupt 10                      Watchdog timer
183
.word end_of_test  ; Interrupt 11                      
184
.word end_of_test  ; Interrupt 12                      
185
.word end_of_test  ; Interrupt 13                      
186
.word end_of_test  ; Interrupt 14                      NMI
187
.word main         ; Interrupt 15 (highest priority)   RESET

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.