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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_watchdog.v] - Blame information for rev 222

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Line No. Rev Author Line
1 2 olivier.gi
/*===========================================================================*/
2
/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            WATCHDOG TIMER                                 */
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer:                                                    */
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/*                        - Watchdog mode.                                   */
28 17 olivier.gi
/*                                                                           */
29 18 olivier.gi
/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
32 17 olivier.gi
/*---------------------------------------------------------------------------*/
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/* $Rev: 202 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $          */
36 2 olivier.gi
/*===========================================================================*/
37 202 olivier.gi
 
38 2 olivier.gi
`define LONG_TIMEOUT
39
 
40
initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
47
 
48 134 olivier.gi
`ifdef WATCHDOG
49 2 olivier.gi
 
50
      // WATCHDOG TEST:  RD/WR ACCESS
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      //--------------------------------------------------------
52
 
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      @(mem250===16'h1000);
54 134 olivier.gi
`ifdef NMI
55
  `ifdef WATCHDOG_MUX
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      if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
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      if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 1) =====");
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      if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 1) =====");
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      if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 1) =====");
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      if (mem208 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
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  `else
62
    `ifdef WATCHDOG_NOMUX_ACLK
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      if (mem200 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
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      if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 2) =====");
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      if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 2) =====");
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      if (mem206 !== 16'h69a6) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a6 (CONFIG 2) =====");
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      if (mem208 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
68
    `else
69
      if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
70 180 olivier.gi
      `ifdef ASIC_CLOCKING
71 134 olivier.gi
      if (mem202 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) =====");
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      if (mem204 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) =====");
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      if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) =====");
74
      `else
75
      if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 3) =====");
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      if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 3) =====");
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      if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3) =====");
78
      `endif
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      if (mem208 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
80
    `endif
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  `endif
82
`else
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  `ifdef WATCHDOG_MUX
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      if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
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      if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 4) =====");
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      if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 4) =====");
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      if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 4) =====");
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      if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
89
  `else
90
    `ifdef WATCHDOG_NOMUX_ACLK
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      if (mem200 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
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      if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 5) =====");
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      if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 5) =====");
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      if (mem206 !== 16'h6986) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6986 (CONFIG 5) =====");
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      if (mem208 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
96
    `else
97
      if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
98 180 olivier.gi
      `ifdef ASIC_CLOCKING
99 134 olivier.gi
      if (mem202 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) =====");
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      if (mem204 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) =====");
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      if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) =====");
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      `else
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      if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 6) =====");
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      if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 6) =====");
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      if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6) =====");
106
      `endif
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      if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
108
    `endif
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  `endif
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`endif
111 202 olivier.gi
 
112 180 olivier.gi
`ifdef ASIC_CLOCKING
113 134 olivier.gi
  `ifdef WATCHDOG_MUX
114
  `else
115
    `ifdef WATCHDOG_NOMUX_ACLK
116
      // From there, force the watchdog clock to DCO_CLK to speedup simulation
117 202 olivier.gi
      force lfxt_clk = dco_clk;
118 134 olivier.gi
    `endif
119
  `endif
120
`endif
121 2 olivier.gi
 
122
      // WATCHDOG TEST:  WATCHDOG MODE /64
123
      //--------------------------------------------------------
124
 
125
      @(mem250===16'h2000);
126 180 olivier.gi
`ifdef ASIC_CLOCKING
127 134 olivier.gi
      if (mem200 !== 16'h000B) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000B =====");
128
`else
129 2 olivier.gi
      if (mem200 !== 16'h000A) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000A =====");
130 134 olivier.gi
`endif
131 202 olivier.gi
 
132 2 olivier.gi
      $display("Watchdog mode /64 mode test completed...");
133
 
134 202 olivier.gi
 
135 2 olivier.gi
      // WATCHDOG TEST:  INTERVAL MODE /512
136
      //--------------------------------------------------------
137
 
138
      @(mem250===16'h3000);
139 180 olivier.gi
`ifdef ASIC_CLOCKING
140 134 olivier.gi
      if (mem202 !== 16'h0056) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0056 =====");
141
`else
142 2 olivier.gi
      if (mem202 !== 16'h0055) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0055 =====");
143 134 olivier.gi
`endif
144 2 olivier.gi
 
145
      $display("Watchdog mode /512 mode test completed...");
146
 
147 202 olivier.gi
 
148 2 olivier.gi
      // WATCHDOG TEST:  INTERVAL MODE /8192
149
      //--------------------------------------------------------
150
 
151
      @(mem250===16'h4000);
152 180 olivier.gi
`ifdef ASIC_CLOCKING
153 134 olivier.gi
      if (mem204 !== 16'h0556) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0556 =====");
154
`else
155 2 olivier.gi
      if (mem204 !== 16'h0555) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0555 =====");
156 134 olivier.gi
`endif
157 2 olivier.gi
 
158
      $display("Watchdog mode /8192 mode test completed...");
159
 
160 202 olivier.gi
 
161 2 olivier.gi
      // WATCHDOG TEST:  INTERVAL MODE /32768
162
      //--------------------------------------------------------
163
 
164
      @(mem250===16'h5000);
165 180 olivier.gi
`ifdef ASIC_CLOCKING
166 134 olivier.gi
      if (mem206 !== 16'h1556) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1556 =====");
167
`else
168 2 olivier.gi
      if (mem206 !== 16'h1555) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1555 =====");
169 134 olivier.gi
`endif
170 2 olivier.gi
 
171
      $display("Watchdog mode /32768 mode test completed...");
172
 
173 134 olivier.gi
`else
174 202 olivier.gi
      tb_skip_finish("|         (the Watchdog is not included)        |");
175 134 olivier.gi
`endif
176 2 olivier.gi
 
177
      stimulus_done = 1;
178
   end

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