1 |
2 |
olivier.gi |
/*===========================================================================*/
|
2 |
|
|
/* Copyright (C) 2001 Authors */
|
3 |
|
|
/* */
|
4 |
|
|
/* This source file may be used and distributed without restriction provided */
|
5 |
|
|
/* that this copyright statement is not removed from the file and that any */
|
6 |
|
|
/* derivative work contains the original copyright notice and the associated */
|
7 |
|
|
/* disclaimer. */
|
8 |
|
|
/* */
|
9 |
|
|
/* This source file is free software; you can redistribute it and/or modify */
|
10 |
|
|
/* it under the terms of the GNU Lesser General Public License as published */
|
11 |
|
|
/* by the Free Software Foundation; either version 2.1 of the License, or */
|
12 |
|
|
/* (at your option) any later version. */
|
13 |
|
|
/* */
|
14 |
|
|
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
|
15 |
|
|
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
|
16 |
|
|
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
|
17 |
|
|
/* License for more details. */
|
18 |
|
|
/* */
|
19 |
|
|
/* You should have received a copy of the GNU Lesser General Public License */
|
20 |
|
|
/* along with this source; if not, write to the Free Software Foundation, */
|
21 |
|
|
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
|
22 |
|
|
/* */
|
23 |
|
|
/*===========================================================================*/
|
24 |
|
|
/* WATCHDOG TIMER */
|
25 |
|
|
/*---------------------------------------------------------------------------*/
|
26 |
|
|
/* Test the Watdog timer: */
|
27 |
|
|
/* - Watchdog mode. */
|
28 |
17 |
olivier.gi |
/* */
|
29 |
18 |
olivier.gi |
/* Author(s): */
|
30 |
|
|
/* - Olivier Girard, olgirard@gmail.com */
|
31 |
|
|
/* */
|
32 |
17 |
olivier.gi |
/*---------------------------------------------------------------------------*/
|
33 |
|
|
/* $Rev: 202 $ */
|
34 |
|
|
/* $LastChangedBy: olivier.girard $ */
|
35 |
|
|
/* $LastChangedDate: 2015-07-01 23:13:32 +0200 (Wed, 01 Jul 2015) $ */
|
36 |
2 |
olivier.gi |
/*===========================================================================*/
|
37 |
202 |
olivier.gi |
|
38 |
2 |
olivier.gi |
`define LONG_TIMEOUT
|
39 |
|
|
|
40 |
|
|
initial
|
41 |
|
|
begin
|
42 |
|
|
$display(" ===============================================");
|
43 |
|
|
$display("| START SIMULATION |");
|
44 |
|
|
$display(" ===============================================");
|
45 |
|
|
repeat(5) @(posedge mclk);
|
46 |
|
|
stimulus_done = 0;
|
47 |
|
|
|
48 |
134 |
olivier.gi |
`ifdef WATCHDOG
|
49 |
2 |
olivier.gi |
|
50 |
|
|
// WATCHDOG TEST: RD/WR ACCESS
|
51 |
|
|
//--------------------------------------------------------
|
52 |
|
|
|
53 |
|
|
@(mem250===16'h1000);
|
54 |
134 |
olivier.gi |
`ifdef NMI
|
55 |
|
|
`ifdef WATCHDOG_MUX
|
56 |
|
|
if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
|
57 |
|
|
if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 1) =====");
|
58 |
|
|
if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 1) =====");
|
59 |
|
|
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 1) =====");
|
60 |
|
|
if (mem208 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 1) =====");
|
61 |
|
|
`else
|
62 |
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
63 |
|
|
if (mem200 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
|
64 |
|
|
if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 2) =====");
|
65 |
|
|
if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 2) =====");
|
66 |
|
|
if (mem206 !== 16'h69a6) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a6 (CONFIG 2) =====");
|
67 |
|
|
if (mem208 !== 16'h6924) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6924 (CONFIG 2) =====");
|
68 |
|
|
`else
|
69 |
|
|
if (mem200 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
|
70 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
71 |
134 |
olivier.gi |
if (mem202 !== 16'h69f3) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f3 (CONFIG 3-ASIC) =====");
|
72 |
|
|
if (mem204 !== 16'h6971) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6971 (CONFIG 3-ASIC) =====");
|
73 |
|
|
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3-ASIC) =====");
|
74 |
|
|
`else
|
75 |
|
|
if (mem202 !== 16'h69f7) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69f7 (CONFIG 3) =====");
|
76 |
|
|
if (mem204 !== 16'h6975) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6975 (CONFIG 3) =====");
|
77 |
|
|
if (mem206 !== 16'h69a2) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x69a2 (CONFIG 3) =====");
|
78 |
|
|
`endif
|
79 |
|
|
if (mem208 !== 16'h6920) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6920 (CONFIG 3) =====");
|
80 |
|
|
`endif
|
81 |
|
|
`endif
|
82 |
|
|
`else
|
83 |
|
|
`ifdef WATCHDOG_MUX
|
84 |
|
|
if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
|
85 |
|
|
if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 4) =====");
|
86 |
|
|
if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 4) =====");
|
87 |
|
|
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 4) =====");
|
88 |
|
|
if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 4) =====");
|
89 |
|
|
`else
|
90 |
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
91 |
|
|
if (mem200 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
|
92 |
|
|
if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 5) =====");
|
93 |
|
|
if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 5) =====");
|
94 |
|
|
if (mem206 !== 16'h6986) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6986 (CONFIG 5) =====");
|
95 |
|
|
if (mem208 !== 16'h6904) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6904 (CONFIG 5) =====");
|
96 |
|
|
`else
|
97 |
|
|
if (mem200 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
|
98 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
99 |
134 |
olivier.gi |
if (mem202 !== 16'h6993) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6993 (CONFIG 6-ASIC) =====");
|
100 |
|
|
if (mem204 !== 16'h6911) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6911 (CONFIG 6-ASIC) =====");
|
101 |
|
|
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6-ASIC) =====");
|
102 |
|
|
`else
|
103 |
|
|
if (mem202 !== 16'h6997) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6997 (CONFIG 6) =====");
|
104 |
|
|
if (mem204 !== 16'h6915) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6915 (CONFIG 6) =====");
|
105 |
|
|
if (mem206 !== 16'h6982) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6982 (CONFIG 6) =====");
|
106 |
|
|
`endif
|
107 |
|
|
if (mem208 !== 16'h6900) tb_error("====== WATCHDOG RD/WR ACCESS: WDTCTL != 0x6900 (CONFIG 6) =====");
|
108 |
|
|
`endif
|
109 |
|
|
`endif
|
110 |
|
|
`endif
|
111 |
202 |
olivier.gi |
|
112 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
113 |
134 |
olivier.gi |
`ifdef WATCHDOG_MUX
|
114 |
|
|
`else
|
115 |
|
|
`ifdef WATCHDOG_NOMUX_ACLK
|
116 |
|
|
// From there, force the watchdog clock to DCO_CLK to speedup simulation
|
117 |
202 |
olivier.gi |
force lfxt_clk = dco_clk;
|
118 |
134 |
olivier.gi |
`endif
|
119 |
|
|
`endif
|
120 |
|
|
`endif
|
121 |
2 |
olivier.gi |
|
122 |
|
|
// WATCHDOG TEST: WATCHDOG MODE /64
|
123 |
|
|
//--------------------------------------------------------
|
124 |
|
|
|
125 |
|
|
@(mem250===16'h2000);
|
126 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
127 |
134 |
olivier.gi |
if (mem200 !== 16'h000B) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000B =====");
|
128 |
|
|
`else
|
129 |
2 |
olivier.gi |
if (mem200 !== 16'h000A) tb_error("====== WATCHDOG MODE /64: @0x200 != 0x000A =====");
|
130 |
134 |
olivier.gi |
`endif
|
131 |
202 |
olivier.gi |
|
132 |
2 |
olivier.gi |
$display("Watchdog mode /64 mode test completed...");
|
133 |
|
|
|
134 |
202 |
olivier.gi |
|
135 |
2 |
olivier.gi |
// WATCHDOG TEST: INTERVAL MODE /512
|
136 |
|
|
//--------------------------------------------------------
|
137 |
|
|
|
138 |
|
|
@(mem250===16'h3000);
|
139 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
140 |
134 |
olivier.gi |
if (mem202 !== 16'h0056) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0056 =====");
|
141 |
|
|
`else
|
142 |
2 |
olivier.gi |
if (mem202 !== 16'h0055) tb_error("====== WATCHDOG MODE /512: @0x202 != 0x0055 =====");
|
143 |
134 |
olivier.gi |
`endif
|
144 |
2 |
olivier.gi |
|
145 |
|
|
$display("Watchdog mode /512 mode test completed...");
|
146 |
|
|
|
147 |
202 |
olivier.gi |
|
148 |
2 |
olivier.gi |
// WATCHDOG TEST: INTERVAL MODE /8192
|
149 |
|
|
//--------------------------------------------------------
|
150 |
|
|
|
151 |
|
|
@(mem250===16'h4000);
|
152 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
153 |
134 |
olivier.gi |
if (mem204 !== 16'h0556) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0556 =====");
|
154 |
|
|
`else
|
155 |
2 |
olivier.gi |
if (mem204 !== 16'h0555) tb_error("====== WATCHDOG MODE /8192: @0x204 != 0x0555 =====");
|
156 |
134 |
olivier.gi |
`endif
|
157 |
2 |
olivier.gi |
|
158 |
|
|
$display("Watchdog mode /8192 mode test completed...");
|
159 |
|
|
|
160 |
202 |
olivier.gi |
|
161 |
2 |
olivier.gi |
// WATCHDOG TEST: INTERVAL MODE /32768
|
162 |
|
|
//--------------------------------------------------------
|
163 |
|
|
|
164 |
|
|
@(mem250===16'h5000);
|
165 |
180 |
olivier.gi |
`ifdef ASIC_CLOCKING
|
166 |
134 |
olivier.gi |
if (mem206 !== 16'h1556) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1556 =====");
|
167 |
|
|
`else
|
168 |
2 |
olivier.gi |
if (mem206 !== 16'h1555) tb_error("====== WATCHDOG MODE /32768: @0x206 != 0x1555 =====");
|
169 |
134 |
olivier.gi |
`endif
|
170 |
2 |
olivier.gi |
|
171 |
|
|
$display("Watchdog mode /32768 mode test completed...");
|
172 |
|
|
|
173 |
134 |
olivier.gi |
`else
|
174 |
202 |
olivier.gi |
tb_skip_finish("| (the Watchdog is not included) |");
|
175 |
134 |
olivier.gi |
`endif
|
176 |
2 |
olivier.gi |
|
177 |
|
|
stimulus_done = 1;
|
178 |
|
|
end
|