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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_wkup.v] - Blame information for rev 134

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/*===========================================================================*/
/* Copyright (C) 2001 Authors                                                */
/*                                                                           */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any   */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer.                                                               */
/*                                                                           */
/* This source file is free software; you can redistribute it and/or modify  */
/* it under the terms of the GNU Lesser General Public License as published  */
/* by the Free Software Foundation; either version 2.1 of the License, or    */
/* (at your option) any later version.                                       */
/*                                                                           */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
/* License for more details.                                                 */
/*                                                                           */
/* You should have received a copy of the GNU Lesser General Public License  */
/* along with this source; if not, write to the Free Software Foundation,    */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
/*                                                                           */
/*===========================================================================*/
/*                            WATCHDOG TIMER                                 */
/*---------------------------------------------------------------------------*/
/* Test the Watdog timer:                                                    */
/*                        - Interval timer mode.                             */
/*                                                                           */
/* Author(s):                                                                */
/*             - Olivier Girard,    olgirard@gmail.com                       */
/*                                                                           */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $                                                                */
/* $LastChangedBy: olivier.girard $                                          */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
/*===========================================================================*/
 
`define LONG_TIMEOUT
 
integer dco_clk_cnt;
always @(negedge dco_clk)
  dco_clk_cnt <= dco_clk_cnt+1;
 
integer mclk_cnt;
always @(negedge mclk)
  mclk_cnt <= mclk_cnt+1;
 
integer smclk_cnt;
always @(negedge smclk)
  smclk_cnt <= smclk_cnt+1;
 
integer aclk_cnt;
`ifdef ASIC
always @(negedge aclk)
  aclk_cnt <= aclk_cnt+1;
`else
always @(negedge lfxt_clk)
  aclk_cnt <= aclk_cnt+1;
`endif
 
integer inst_cnt;
always @(inst_number)
  inst_cnt <= inst_cnt+1;
 
reg watchdog_clock;
`ifdef ASIC
  `ifdef WATCHDOG_MUX
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
  `else
    `ifdef WATCHDOG_NOMUX_ACLK
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
    `else
       always @(posedge dco_clk  or negedge dco_clk)  watchdog_clock <= dco_clk;
    `endif
  `endif
`else
       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
`endif
 
integer watchdog_clock_cnt;
always @(posedge watchdog_clock)
  watchdog_clock_cnt <= watchdog_clock_cnt+1;
 
always @(posedge dut.wdt_irq)
  watchdog_clock_cnt = 1'b0;
 
 
integer ii;
integer jj;
 
initial
   begin
      $display(" ===============================================");
      $display("|                 START SIMULATION              |");
      $display(" ===============================================");
      repeat(5) @(posedge mclk);
      stimulus_done = 0;
      ii = 0;
      jj = 0;
 
`ifdef WATCHDOG
 
 
      // WATCHDOG TEST:  INTERVAL MODE /64
      //--------------------------------------------------------
 
      @(r15==16'h1000);
 
`ifdef ASIC
  `ifdef WATCHDOG_MUX
    `ifdef ACLK_DIVIDER
      repeat(5) @(posedge watchdog_clock);
    `else
      repeat(4) @(posedge watchdog_clock);
    `endif
  `else
    `ifdef WATCHDOG_NOMUX_ACLK
      `ifdef ACLK_DIVIDER
        repeat(6) @(posedge watchdog_clock);
      `else
        repeat(5) @(posedge watchdog_clock);
      `endif
    `else
      repeat(21) @(posedge watchdog_clock);
    `endif
  `endif
`endif
 
      for ( ii=0; ii < 9; ii=ii+1)
        begin
           repeat(1) @(posedge watchdog_clock);
           jj = 1;
           dco_clk_cnt = 0;
           mclk_cnt    = 0;
           smclk_cnt   = 0;
           aclk_cnt    = 0;
           inst_cnt    = 0;
           `ifdef ASIC
             `ifdef WATCHDOG_MUX
                 repeat(62) @(posedge watchdog_clock);
                 jj = 2;
                 if (dco_clk_cnt !==  0)   tb_error("====== DCO_CLK is running                     (CONFIG 1) =====");
                 if (mclk_cnt    !==  0)   tb_error("====== MCLK    is running                     (CONFIG 1) =====");
                 if (smclk_cnt   !==  0)   tb_error("====== SMCLK   is running                     (CONFIG 1) =====");
                 if (aclk_cnt    !== 62)   tb_error("====== ACLK    is not running                 (CONFIG 1) =====");
                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 1) =====");
                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 1) =====");
                 repeat(1) @(posedge watchdog_clock);
                 jj = 3;
                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 1) =====");
             `else
               `ifdef WATCHDOG_NOMUX_ACLK
                 repeat(62) @(posedge watchdog_clock);
                 jj = 2;
                 if (dco_clk_cnt !== 0)    tb_error("====== DCO_CLK is running                     (CONFIG 2) =====");
                 if (mclk_cnt    !== 0)    tb_error("====== MCLK    is running                     (CONFIG 2) =====");
                 if (smclk_cnt   !== 0)    tb_error("====== SMCLK   is running                     (CONFIG 2) =====");
                 if (aclk_cnt    !== 62)   tb_error("====== ACLK    is not running                 (CONFIG 2) =====");
                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 2) =====");
                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 2) =====");
                 repeat(1) @(posedge watchdog_clock);
                 jj = 3;
                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 2) =====");
               `else
                 repeat(39) @(posedge watchdog_clock);
                 jj = 2;
                 if (dco_clk_cnt !== 39)   tb_error("====== DCO_CLK is not running                 (CONFIG 3) =====");
                 if (mclk_cnt    !== 0)    tb_error("====== MCLK    is running                     (CONFIG 3) =====");
                 if (smclk_cnt   !== 39)   tb_error("====== SMCLK   is not running                 (CONFIG 3) =====");
                 if (aclk_cnt    === 0)    tb_error("====== ACLK    is not running                 (CONFIG 3) =====");
                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 3) =====");
                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 3) =====");
                 repeat(24) @(posedge watchdog_clock);
                 jj = 3;
                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 3) =====");
               `endif
             `endif
           `else
                 repeat(62) @(posedge watchdog_clock);
                 jj = 2;
                 if (dco_clk_cnt  <  1800) tb_error("====== DCO_CLK is not running                 (CONFIG 4) =====");
                 if (mclk_cnt     <  1800) tb_error("====== MCLK    is not running                 (CONFIG 4) =====");
                 if (smclk_cnt    <  1800) tb_error("====== SMCLK   is not running                 (CONFIG 4) =====");
                 if (aclk_cnt    !== 62)   tb_error("====== ACLK    is not running                 (CONFIG 4) =====");
                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 4) =====");
                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 4) =====");
                 repeat(1) @(posedge watchdog_clock);
                 jj = 3;
                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 4) =====");
           `endif
        end
 
      // WATCHDOG TEST:  RESET MODE /64
      //--------------------------------------------------------
 
      @(r15==16'h5000);
      if (r7 !== 16'h0000) tb_error("====== WATCHDOG reset was not taken =====");
 
 
`else
      $display(" ===============================================");
      $display("|               SIMULATION SKIPPED              |");
      $display("|         (the Watchdog is not included)        |");
      $display(" ===============================================");
      $finish;
`endif
 
      stimulus_done = 1;
   end
 

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_wkup.v] - Blame information for rev 134

Line No.	Rev	Author	Line
1	134	olivier.gi	`/===========================================================================/`
2			`/* Copyright (C) 2001 Authors */`
3			`/* */`
4			`/* This source file may be used and distributed without restriction provided */`
5			`/* that this copyright statement is not removed from the file and that any */`
6			`/* derivative work contains the original copyright notice and the associated */`
7			`/* disclaimer. */`
8			`/* */`
9			`/* This source file is free software; you can redistribute it and/or modify */`
10			`/* it under the terms of the GNU Lesser General Public License as published */`
11			`/* by the Free Software Foundation; either version 2.1 of the License, or */`
12			`/* (at your option) any later version. */`
13			`/* */`
14			`/* This source is distributed in the hope that it will be useful, but WITHOUT*/`
15			`/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */`
16			`/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */`
17			`/* License for more details. */`
18			`/* */`
19			`/* You should have received a copy of the GNU Lesser General Public License */`
20			`/* along with this source; if not, write to the Free Software Foundation, */`
21			`/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */`
22			`/* */`
23			`/===========================================================================/`
24			`/* WATCHDOG TIMER */`
25			`/---------------------------------------------------------------------------/`
26			`/* Test the Watdog timer: */`
27			`/* - Interval timer mode. */`
28			`/* */`
29			`/* Author(s): */`
30			`/* - Olivier Girard, olgirard@gmail.com */`
31			`/* */`
32			`/---------------------------------------------------------------------------/`
33			`/* $Rev: 19 $ */`
34			`/* $LastChangedBy: olivier.girard $ */`
35			`/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */`
36			`/===========================================================================/`
37
38			`define LONG_TIMEOUT
39
40			`integer dco_clk_cnt;`
41			`always @(negedge dco_clk)`
42			`dco_clk_cnt <= dco_clk_cnt+1;`
43
44			`integer mclk_cnt;`
45			`always @(negedge mclk)`
46			`mclk_cnt <= mclk_cnt+1;`
47
48			`integer smclk_cnt;`
49			`always @(negedge smclk)`
50			`smclk_cnt <= smclk_cnt+1;`
51
52			`integer aclk_cnt;`
53			`ifdef ASIC
54			`always @(negedge aclk)`
55			`aclk_cnt <= aclk_cnt+1;`
56			`else
57			`always @(negedge lfxt_clk)`
58			`aclk_cnt <= aclk_cnt+1;`
59			`endif
60
61			`integer inst_cnt;`
62			`always @(inst_number)`
63			`inst_cnt <= inst_cnt+1;`
64
65			`reg watchdog_clock;`
66			`ifdef ASIC
67			`ifdef WATCHDOG_MUX
68			`always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;`
69			`else
70			`ifdef WATCHDOG_NOMUX_ACLK
71			`always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;`
72			`else
73			`always @(posedge dco_clk or negedge dco_clk) watchdog_clock <= dco_clk;`
74			`endif
75			`endif
76			`else
77			`always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;`
78			`endif
79
80			`integer watchdog_clock_cnt;`
81			`always @(posedge watchdog_clock)`
82			`watchdog_clock_cnt <= watchdog_clock_cnt+1;`
83
84			`always @(posedge dut.wdt_irq)`
85			`watchdog_clock_cnt = 1'b0;`
86
87
88			`integer ii;`
89			`integer jj;`
90
91			`initial`
92			`begin`
93			`$display(" ===============================================");`
94			`$display("\| START SIMULATION \|");`
95			`$display(" ===============================================");`
96			`repeat(5) @(posedge mclk);`
97			`stimulus_done = 0;`
98			`ii = 0;`
99			`jj = 0;`
100
101			`ifdef WATCHDOG
102
103
104			`// WATCHDOG TEST: INTERVAL MODE /64`
105			`//--------------------------------------------------------`
106
107			`@(r15==16'h1000);`
108
109			`ifdef ASIC
110			`ifdef WATCHDOG_MUX
111			`ifdef ACLK_DIVIDER
112			`repeat(5) @(posedge watchdog_clock);`
113			`else
114			`repeat(4) @(posedge watchdog_clock);`
115			`endif
116			`else
117			`ifdef WATCHDOG_NOMUX_ACLK
118			`ifdef ACLK_DIVIDER
119			`repeat(6) @(posedge watchdog_clock);`
120			`else
121			`repeat(5) @(posedge watchdog_clock);`
122			`endif
123			`else
124			`repeat(21) @(posedge watchdog_clock);`
125			`endif
126			`endif
127			`endif
128
129			`for ( ii=0; ii < 9; ii=ii+1)`
130			`begin`
131			`repeat(1) @(posedge watchdog_clock);`
132			`jj = 1;`
133			`dco_clk_cnt = 0;`
134			`mclk_cnt = 0;`
135			`smclk_cnt = 0;`
136			`aclk_cnt = 0;`
137			`inst_cnt = 0;`
138			`ifdef ASIC
139			`ifdef WATCHDOG_MUX
140			`repeat(62) @(posedge watchdog_clock);`
141			`jj = 2;`
142			`if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 1) =====");`
143			`if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 1) =====");`
144			`if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 1) =====");`
145			`if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 1) =====");`
146			`if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 1) =====");`
147			`if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 1) =====");`
148			`repeat(1) @(posedge watchdog_clock);`
149			`jj = 3;`
150			`if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 1) =====");`
151			`else
152			`ifdef WATCHDOG_NOMUX_ACLK
153			`repeat(62) @(posedge watchdog_clock);`
154			`jj = 2;`
155			`if (dco_clk_cnt !== 0) tb_error("====== DCO_CLK is running (CONFIG 2) =====");`
156			`if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 2) =====");`
157			`if (smclk_cnt !== 0) tb_error("====== SMCLK is running (CONFIG 2) =====");`
158			`if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 2) =====");`
159			`if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 2) =====");`
160			`if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 2) =====");`
161			`repeat(1) @(posedge watchdog_clock);`
162			`jj = 3;`
163			`if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 2) =====");`
164			`else
165			`repeat(39) @(posedge watchdog_clock);`
166			`jj = 2;`
167			`if (dco_clk_cnt !== 39) tb_error("====== DCO_CLK is not running (CONFIG 3) =====");`
168			`if (mclk_cnt !== 0) tb_error("====== MCLK is running (CONFIG 3) =====");`
169			`if (smclk_cnt !== 39) tb_error("====== SMCLK is not running (CONFIG 3) =====");`
170			`if (aclk_cnt === 0) tb_error("====== ACLK is not running (CONFIG 3) =====");`
171			`if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 3) =====");`
172			`if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 3) =====");`
173			`repeat(24) @(posedge watchdog_clock);`
174			`jj = 3;`
175			`if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 3) =====");`
176			`endif
177			`endif
178			`else
179			`repeat(62) @(posedge watchdog_clock);`
180			`jj = 2;`
181			`if (dco_clk_cnt < 1800) tb_error("====== DCO_CLK is not running (CONFIG 4) =====");`
182			`if (mclk_cnt < 1800) tb_error("====== MCLK is not running (CONFIG 4) =====");`
183			`if (smclk_cnt < 1800) tb_error("====== SMCLK is not running (CONFIG 4) =====");`
184			`if (aclk_cnt !== 62) tb_error("====== ACLK is not running (CONFIG 4) =====");`
185			`if (inst_cnt !== 0) tb_error("====== CPU is executing (CONFIG 4) =====");`
186			`if (r6 !== ii) tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 4) =====");`
187			`repeat(1) @(posedge watchdog_clock);`
188			`jj = 3;`
189			`if (r6 !== ii+1) tb_error("====== WATCHDOG interrupt was not taken (CONFIG 4) =====");`
190			`endif
191			`end`
192
193			`// WATCHDOG TEST: RESET MODE /64`
194			`//--------------------------------------------------------`
195
196			`@(r15==16'h5000);`
197			`if (r7 !== 16'h0000) tb_error("====== WATCHDOG reset was not taken =====");`
198
199
200			`else
201			`$display(" ===============================================");`
202			`$display("\| SIMULATION SKIPPED \|");`
203			`$display("\| (the Watchdog is not included) \|");`
204			`$display(" ===============================================");`
205			`$finish;`
206			`endif
207
208			`stimulus_done = 1;`
209			`end`
210