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[/] [openmsp430/] [trunk/] [core/] [sim/] [rtl_sim/] [src/] [wdt_wkup.v] - Blame information for rev 134

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1 134 olivier.gi
/*===========================================================================*/
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/* Copyright (C) 2001 Authors                                                */
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/*                                                                           */
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/* This source file may be used and distributed without restriction provided */
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/* that this copyright statement is not removed from the file and that any   */
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/* derivative work contains the original copyright notice and the associated */
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/* disclaimer.                                                               */
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/*                                                                           */
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/* This source file is free software; you can redistribute it and/or modify  */
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/* it under the terms of the GNU Lesser General Public License as published  */
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/* by the Free Software Foundation; either version 2.1 of the License, or    */
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/* (at your option) any later version.                                       */
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/*                                                                           */
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/* This source is distributed in the hope that it will be useful, but WITHOUT*/
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/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or     */
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/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public       */
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/* License for more details.                                                 */
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/*                                                                           */
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/* You should have received a copy of the GNU Lesser General Public License  */
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/* along with this source; if not, write to the Free Software Foundation,    */
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/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA        */
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/*                                                                           */
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/*===========================================================================*/
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/*                            WATCHDOG TIMER                                 */
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/*---------------------------------------------------------------------------*/
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/* Test the Watdog timer:                                                    */
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/*                        - Interval timer mode.                             */
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/*                                                                           */
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/* Author(s):                                                                */
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/*             - Olivier Girard,    olgirard@gmail.com                       */
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/*                                                                           */
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/*---------------------------------------------------------------------------*/
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/* $Rev: 19 $                                                                */
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/* $LastChangedBy: olivier.girard $                                          */
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/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $          */
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/*===========================================================================*/
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`define LONG_TIMEOUT
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integer dco_clk_cnt;
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always @(negedge dco_clk)
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  dco_clk_cnt <= dco_clk_cnt+1;
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integer mclk_cnt;
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always @(negedge mclk)
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  mclk_cnt <= mclk_cnt+1;
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integer smclk_cnt;
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always @(negedge smclk)
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  smclk_cnt <= smclk_cnt+1;
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integer aclk_cnt;
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`ifdef ASIC
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always @(negedge aclk)
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  aclk_cnt <= aclk_cnt+1;
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`else
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always @(negedge lfxt_clk)
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  aclk_cnt <= aclk_cnt+1;
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`endif
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integer inst_cnt;
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always @(inst_number)
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  inst_cnt <= inst_cnt+1;
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reg watchdog_clock;
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`ifdef ASIC
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  `ifdef WATCHDOG_MUX
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       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
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  `else
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    `ifdef WATCHDOG_NOMUX_ACLK
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       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
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    `else
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       always @(posedge dco_clk  or negedge dco_clk)  watchdog_clock <= dco_clk;
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    `endif
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  `endif
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`else
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       always @(posedge lfxt_clk or negedge lfxt_clk) watchdog_clock <= lfxt_clk;
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`endif
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integer watchdog_clock_cnt;
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always @(posedge watchdog_clock)
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  watchdog_clock_cnt <= watchdog_clock_cnt+1;
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always @(posedge dut.wdt_irq)
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  watchdog_clock_cnt = 1'b0;
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integer ii;
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integer jj;
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initial
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   begin
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      $display(" ===============================================");
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      $display("|                 START SIMULATION              |");
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      $display(" ===============================================");
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      repeat(5) @(posedge mclk);
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      stimulus_done = 0;
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      ii = 0;
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      jj = 0;
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`ifdef WATCHDOG
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      // WATCHDOG TEST:  INTERVAL MODE /64
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      //--------------------------------------------------------
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      @(r15==16'h1000);
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`ifdef ASIC
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  `ifdef WATCHDOG_MUX
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    `ifdef ACLK_DIVIDER
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      repeat(5) @(posedge watchdog_clock);
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    `else
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      repeat(4) @(posedge watchdog_clock);
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    `endif
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  `else
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    `ifdef WATCHDOG_NOMUX_ACLK
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      `ifdef ACLK_DIVIDER
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        repeat(6) @(posedge watchdog_clock);
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      `else
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        repeat(5) @(posedge watchdog_clock);
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      `endif
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    `else
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      repeat(21) @(posedge watchdog_clock);
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    `endif
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  `endif
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`endif
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      for ( ii=0; ii < 9; ii=ii+1)
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        begin
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           repeat(1) @(posedge watchdog_clock);
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           jj = 1;
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           dco_clk_cnt = 0;
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           mclk_cnt    = 0;
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           smclk_cnt   = 0;
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           aclk_cnt    = 0;
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           inst_cnt    = 0;
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           `ifdef ASIC
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             `ifdef WATCHDOG_MUX
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                 repeat(62) @(posedge watchdog_clock);
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                 jj = 2;
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                 if (dco_clk_cnt !==  0)   tb_error("====== DCO_CLK is running                     (CONFIG 1) =====");
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                 if (mclk_cnt    !==  0)   tb_error("====== MCLK    is running                     (CONFIG 1) =====");
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                 if (smclk_cnt   !==  0)   tb_error("====== SMCLK   is running                     (CONFIG 1) =====");
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                 if (aclk_cnt    !== 62)   tb_error("====== ACLK    is not running                 (CONFIG 1) =====");
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                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 1) =====");
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                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 1) =====");
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                 repeat(1) @(posedge watchdog_clock);
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                 jj = 3;
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                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 1) =====");
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             `else
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               `ifdef WATCHDOG_NOMUX_ACLK
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                 repeat(62) @(posedge watchdog_clock);
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                 jj = 2;
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                 if (dco_clk_cnt !== 0)    tb_error("====== DCO_CLK is running                     (CONFIG 2) =====");
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                 if (mclk_cnt    !== 0)    tb_error("====== MCLK    is running                     (CONFIG 2) =====");
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                 if (smclk_cnt   !== 0)    tb_error("====== SMCLK   is running                     (CONFIG 2) =====");
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                 if (aclk_cnt    !== 62)   tb_error("====== ACLK    is not running                 (CONFIG 2) =====");
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                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 2) =====");
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                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 2) =====");
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                 repeat(1) @(posedge watchdog_clock);
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                 jj = 3;
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                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 2) =====");
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               `else
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                 repeat(39) @(posedge watchdog_clock);
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                 jj = 2;
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                 if (dco_clk_cnt !== 39)   tb_error("====== DCO_CLK is not running                 (CONFIG 3) =====");
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                 if (mclk_cnt    !== 0)    tb_error("====== MCLK    is running                     (CONFIG 3) =====");
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                 if (smclk_cnt   !== 39)   tb_error("====== SMCLK   is not running                 (CONFIG 3) =====");
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                 if (aclk_cnt    === 0)    tb_error("====== ACLK    is not running                 (CONFIG 3) =====");
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                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 3) =====");
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                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 3) =====");
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                 repeat(24) @(posedge watchdog_clock);
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                 jj = 3;
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                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 3) =====");
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               `endif
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             `endif
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           `else
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                 repeat(62) @(posedge watchdog_clock);
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                 jj = 2;
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                 if (dco_clk_cnt  <  1800) tb_error("====== DCO_CLK is not running                 (CONFIG 4) =====");
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                 if (mclk_cnt     <  1800) tb_error("====== MCLK    is not running                 (CONFIG 4) =====");
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                 if (smclk_cnt    <  1800) tb_error("====== SMCLK   is not running                 (CONFIG 4) =====");
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                 if (aclk_cnt    !== 62)   tb_error("====== ACLK    is not running                 (CONFIG 4) =====");
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                 if (inst_cnt    !== 0)    tb_error("====== CPU is executing                       (CONFIG 4) =====");
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                 if (r6          !== ii)   tb_error("====== WATCHDOG interrupt was taken too early (CONFIG 4) =====");
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                 repeat(1) @(posedge watchdog_clock);
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                 jj = 3;
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                 if (r6          !== ii+1) tb_error("====== WATCHDOG interrupt was not taken       (CONFIG 4) =====");
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           `endif
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        end
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      // WATCHDOG TEST:  RESET MODE /64
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      //--------------------------------------------------------
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      @(r15==16'h5000);
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      if (r7 !== 16'h0000) tb_error("====== WATCHDOG reset was not taken =====");
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`else
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      $display(" ===============================================");
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      $display("|               SIMULATION SKIPPED              |");
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      $display("|         (the Watchdog is not included)        |");
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      $display(" ===============================================");
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      $finish;
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`endif
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      stimulus_done = 1;
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   end
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