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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [libero_designer.tcl] - Blame information for rev 74

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Line No. Rev Author Line
1 64 olivier.gi
 
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new_design -name "design_fpga" -family "<DEVICE_FAMILY>" -path {.} -block "off"
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set_device -die     "<DEVICE_NAME>" \
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           -package "484 FBGA" \
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                   -speed   "<SPEED_GRADE>"
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import_source -format "edif" -edif_flavor "GENERIC" {./rev_1/design_files.edn} \
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              -format "sdc"  -scenario "Primary"    {../design_files.sdc}      \
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                          -merge_physical "no" -merge_timing "yes"
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compile -pdc_abort_on_error "on"              -pdc_eco_display_unmatched_objects "off" -pdc_eco_max_warnings 10000         \
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        -demote_globals "off"                 -demote_globals_max_fanout 12            -promote_globals "off"              \
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            -promote_globals_min_fanout 200       -promote_globals_max_limit  0            -localclock_max_shared_instances 12 \
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            -localclock_buffer_tree_max_fanout 12 -combine_register "off"                  -delete_buffer_tree "off"           \
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            -delete_buffer_tree_max_fanout 12     -report_high_fanout_nets_limit 10
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layout -timing_driven -placer_high_effort "on" -seq_opt "on"
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report -type "timer"             -format "TEXT"            -analysis "max"            -print_summary "yes"   \
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       -use_slack_threshold "no" -print_paths "yes"        -max_paths 5               -max_expanded_paths 1  \
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           -include_user_sets "no"   -include_pin_to_pin "yes" -select_clock_domains "no"                        \
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      {./report_timing_max.txt}
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report -type "status" \
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      {./report_status.txt}
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