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68 |
olivier.gi |
#####################################################################################
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# START SYNTHESIS
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#====================================================================================
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# ProASIC3E (A3PE1500), speedgrade: Std
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#====================================================================================
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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# 12 10 0 0 0 0 0 1
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#====================================================================================
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Clock Domain: dco_clk
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Period (ns): 61.969
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Frequency (MHz): 16.137
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Required Period (ns): 40.000
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Required Frequency (MHz): 25.000
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| 16 |
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External Setup (ns): 60.413
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| 17 |
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External Hold (ns): 0.000
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Min Clock-To-Out (ns): 0.000
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Max Clock-To-Out (ns): 72.849
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Input to Output
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Min Delay (ns): 0.000
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Max Delay (ns): 71.293
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====================================================================================
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Compile report:
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===============
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CORE Used: 4734
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Core Information:
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Type | Instances | Core tiles
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| 34 |
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--------|--------------|-----------
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| 35 |
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COMB | 4184 | 4184
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| 36 |
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SEQ | 550 | 550
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| 37 |
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====================================================================================
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# SYNTHESIS DONE
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#####################################################################################
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#####################################################################################
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| 44 |
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# START SYNTHESIS
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| 45 |
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#====================================================================================
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| 46 |
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# ProASIC3E (A3PE1500), speedgrade: -1
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| 47 |
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#====================================================================================
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| 48 |
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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# 12 10 0 0 0 0 0 1
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#====================================================================================
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| 51 |
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Clock Domain: dco_clk
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| 54 |
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Period (ns): 52.723
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| 55 |
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Frequency (MHz): 18.967
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| 56 |
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Required Period (ns): 40.000
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| 57 |
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Required Frequency (MHz): 25.000
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| 58 |
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External Setup (ns): 49.425
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| 59 |
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External Hold (ns): 0.276
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| 60 |
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Min Clock-To-Out (ns): 3.206
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| 61 |
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Max Clock-To-Out (ns): 58.337
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Input to Output
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| 64 |
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Min Delay (ns): 2.045
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Max Delay (ns): 55.039
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====================================================================================
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| 69 |
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Compile report:
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| 70 |
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===============
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| 71 |
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| 72 |
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CORE Used: 4585
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| 73 |
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Core Information:
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| 74 |
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| 75 |
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Type | Instances | Core tiles
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| 76 |
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--------|--------------|-----------
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| 77 |
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COMB | 4033 | 4033
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| 78 |
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SEQ | 552 | 552
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====================================================================================
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# SYNTHESIS DONE
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#####################################################################################
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#####################################################################################
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| 86 |
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# START SYNTHESIS
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| 87 |
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#====================================================================================
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| 88 |
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# ProASIC3E (A3PE1500), speedgrade: -2
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| 89 |
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#====================================================================================
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| 90 |
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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# 12 10 0 0 0 0 0 1
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#====================================================================================
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| 93 |
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| 94 |
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Clock Domain: dco_clk
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| 96 |
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Period (ns): 47.977
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| 97 |
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Frequency (MHz): 20.843
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| 98 |
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Required Period (ns): 40.000
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| 99 |
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Required Frequency (MHz): 25.000
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| 100 |
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External Setup (ns): 44.738
|
| 101 |
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External Hold (ns): 0.216
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| 102 |
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Min Clock-To-Out (ns): 3.281
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| 103 |
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Max Clock-To-Out (ns): 52.477
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Input to Output
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| 106 |
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Min Delay (ns): 2.088
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Max Delay (ns): 49.238
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====================================================================================
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Compile report:
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===============
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CORE Used: 4573
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Core Information:
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Type | Instances | Core tiles
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| 118 |
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--------|--------------|-----------
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| 119 |
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COMB | 4020 | 4020
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| 120 |
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SEQ | 553 | 553
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| 121 |
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| 122 |
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====================================================================================
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# SYNTHESIS DONE
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#####################################################################################
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#####################################################################################
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| 128 |
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# START SYNTHESIS
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| 129 |
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#====================================================================================
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| 130 |
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# ProASIC3L (A3P1000L), speedgrade: Std
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| 131 |
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#====================================================================================
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| 132 |
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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# 12 10 0 0 0 0 0 1
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#====================================================================================
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| 136 |
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Clock Domain: dco_clk
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| 138 |
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Period (ns): 70.092
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Frequency (MHz): 14.267
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Required Period (ns): 40.000
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| 141 |
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Required Frequency (MHz): 25.000
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| 142 |
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External Setup (ns): 67.167
|
| 143 |
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External Hold (ns): 0.206
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| 144 |
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Min Clock-To-Out (ns): 7.443
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| 145 |
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Max Clock-To-Out (ns): 78.104
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Input to Output
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| 148 |
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Min Delay (ns): 4.745
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| 149 |
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Max Delay (ns): 75.179
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| 150 |
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| 152 |
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====================================================================================
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| 153 |
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Compile report:
|
| 154 |
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===============
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| 155 |
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| 156 |
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CORE Used: 4665
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| 157 |
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Core Information:
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| 158 |
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| 159 |
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Type | Instances | Core tiles
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| 160 |
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--------|--------------|-----------
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| 161 |
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COMB | 4113 | 4113
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| 162 |
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SEQ | 552 | 552
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| 163 |
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| 164 |
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| 165 |
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====================================================================================
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| 166 |
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# SYNTHESIS DONE
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| 167 |
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#####################################################################################
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| 168 |
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| 169 |
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#####################################################################################
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| 170 |
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# START SYNTHESIS
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| 171 |
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#====================================================================================
|
| 172 |
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# ProASIC3L (A3P1000L), speedgrade: -1
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| 173 |
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#====================================================================================
|
| 174 |
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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| 175 |
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# 12 10 0 0 0 0 0 1
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| 176 |
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#====================================================================================
|
| 177 |
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| 178 |
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| 179 |
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Clock Domain: dco_clk
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| 180 |
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Period (ns): 57.781
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| 181 |
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Frequency (MHz): 17.307
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| 182 |
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Required Period (ns): 40.000
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| 183 |
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Required Frequency (MHz): 25.000
|
| 184 |
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External Setup (ns): 56.549
|
| 185 |
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External Hold (ns): 0.295
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| 186 |
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Min Clock-To-Out (ns): 6.027
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| 187 |
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Max Clock-To-Out (ns): 65.937
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| 188 |
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| 189 |
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Input to Output
|
| 190 |
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Min Delay (ns): 4.220
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| 191 |
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Max Delay (ns): 64.705
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| 192 |
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| 193 |
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| 194 |
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====================================================================================
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| 195 |
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Compile report:
|
| 196 |
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===============
|
| 197 |
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| 198 |
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CORE Used: 4595
|
| 199 |
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Core Information:
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| 200 |
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| 201 |
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Type | Instances | Core tiles
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| 202 |
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--------|--------------|-----------
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| 203 |
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COMB | 4044 | 4044
|
| 204 |
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SEQ | 551 | 551
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| 205 |
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| 206 |
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| 207 |
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====================================================================================
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| 208 |
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# SYNTHESIS DONE
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| 209 |
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#####################################################################################
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| 210 |
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| 211 |
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#####################################################################################
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| 212 |
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# START SYNTHESIS
|
| 213 |
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#====================================================================================
|
| 214 |
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# ProASIC3 (A3P1000), speedgrade: Std
|
| 215 |
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#====================================================================================
|
| 216 |
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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| 217 |
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# 12 10 0 0 0 0 0 1
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| 218 |
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#====================================================================================
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| 219 |
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| 220 |
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| 221 |
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Clock Domain: dco_clk
|
| 222 |
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Period (ns): 64.007
|
| 223 |
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Frequency (MHz): 15.623
|
| 224 |
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Required Period (ns): 40.000
|
| 225 |
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Required Frequency (MHz): 25.000
|
| 226 |
|
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External Setup (ns): 62.387
|
| 227 |
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External Hold (ns): 0.000
|
| 228 |
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Min Clock-To-Out (ns): 0.000
|
| 229 |
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Max Clock-To-Out (ns): 71.427
|
| 230 |
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| 231 |
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Input to Output
|
| 232 |
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Min Delay (ns): 0.000
|
| 233 |
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Max Delay (ns): 69.807
|
| 234 |
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| 235 |
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| 236 |
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====================================================================================
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| 237 |
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Compile report:
|
| 238 |
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===============
|
| 239 |
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| 240 |
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CORE Used: 4734
|
| 241 |
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Core Information:
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| 242 |
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| 243 |
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Type | Instances | Core tiles
|
| 244 |
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--------|--------------|-----------
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| 245 |
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COMB | 4184 | 4184
|
| 246 |
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SEQ | 550 | 550
|
| 247 |
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| 248 |
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| 249 |
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====================================================================================
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| 250 |
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# SYNTHESIS DONE
|
| 251 |
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#####################################################################################
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| 252 |
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| 253 |
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#####################################################################################
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| 254 |
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# START SYNTHESIS
|
| 255 |
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#====================================================================================
|
| 256 |
|
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# ProASIC3 (A3P1000), speedgrade: -1
|
| 257 |
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#====================================================================================
|
| 258 |
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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| 259 |
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# 12 10 0 0 0 0 0 1
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| 260 |
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#====================================================================================
|
| 261 |
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|
| 262 |
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|
| 263 |
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Clock Domain: dco_clk
|
| 264 |
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Period (ns): 52.047
|
| 265 |
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Frequency (MHz): 19.213
|
| 266 |
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Required Period (ns): 40.000
|
| 267 |
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Required Frequency (MHz): 25.000
|
| 268 |
|
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External Setup (ns): 49.153
|
| 269 |
|
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External Hold (ns): 0.379
|
| 270 |
|
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Min Clock-To-Out (ns): 3.098
|
| 271 |
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Max Clock-To-Out (ns): 59.549
|
| 272 |
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|
| 273 |
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Input to Output
|
| 274 |
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Min Delay (ns): 1.854
|
| 275 |
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Max Delay (ns): 56.655
|
| 276 |
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| 277 |
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| 278 |
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====================================================================================
|
| 279 |
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Compile report:
|
| 280 |
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===============
|
| 281 |
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| 282 |
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CORE Used: 4585
|
| 283 |
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Core Information:
|
| 284 |
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| 285 |
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Type | Instances | Core tiles
|
| 286 |
|
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--------|--------------|-----------
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| 287 |
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COMB | 4033 | 4033
|
| 288 |
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SEQ | 552 | 552
|
| 289 |
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| 290 |
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|
| 291 |
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====================================================================================
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| 292 |
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# SYNTHESIS DONE
|
| 293 |
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#####################################################################################
|
| 294 |
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|
| 295 |
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#####################################################################################
|
| 296 |
|
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# START SYNTHESIS
|
| 297 |
|
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#====================================================================================
|
| 298 |
|
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# ProASIC3 (A3P1000), speedgrade: -2
|
| 299 |
|
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#====================================================================================
|
| 300 |
|
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
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| 301 |
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# 12 10 0 0 0 0 0 1
|
| 302 |
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#====================================================================================
|
| 303 |
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|
| 304 |
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|
| 305 |
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Clock Domain: dco_clk
|
| 306 |
|
|
Period (ns): 45.521
|
| 307 |
|
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Frequency (MHz): 21.968
|
| 308 |
|
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Required Period (ns): 40.000
|
| 309 |
|
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Required Frequency (MHz): 25.000
|
| 310 |
|
|
External Setup (ns): 42.871
|
| 311 |
|
|
External Hold (ns): 0.659
|
| 312 |
|
|
Min Clock-To-Out (ns): 3.201
|
| 313 |
|
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Max Clock-To-Out (ns): 50.665
|
| 314 |
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|
| 315 |
|
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Input to Output
|
| 316 |
|
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Min Delay (ns): 1.940
|
| 317 |
|
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Max Delay (ns): 48.015
|
| 318 |
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|
| 319 |
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|
| 320 |
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====================================================================================
|
| 321 |
|
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Compile report:
|
| 322 |
|
|
===============
|
| 323 |
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|
| 324 |
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CORE Used: 4573
|
| 325 |
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Core Information:
|
| 326 |
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|
| 327 |
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Type | Instances | Core tiles
|
| 328 |
|
|
--------|--------------|-----------
|
| 329 |
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COMB | 4020 | 4020
|
| 330 |
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SEQ | 553 | 553
|
| 331 |
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|
| 332 |
|
|
|
| 333 |
|
|
====================================================================================
|
| 334 |
|
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# SYNTHESIS DONE
|
| 335 |
|
|
#####################################################################################
|
| 336 |
|
|
|
| 337 |
|
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#####################################################################################
|
| 338 |
|
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# START SYNTHESIS
|
| 339 |
|
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#====================================================================================
|
| 340 |
|
|
# Fusion (AFS1500), speedgrade: Std
|
| 341 |
|
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#====================================================================================
|
| 342 |
|
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# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
|
| 343 |
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# 12 10 0 0 0 0 0 1
|
| 344 |
|
|
#====================================================================================
|
| 345 |
|
|
|
| 346 |
|
|
|
| 347 |
|
|
Clock Domain: dco_clk
|
| 348 |
|
|
Period (ns): 63.147
|
| 349 |
|
|
Frequency (MHz): 15.836
|
| 350 |
|
|
Required Period (ns): 40.000
|
| 351 |
|
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Required Frequency (MHz): 25.000
|
| 352 |
|
|
External Setup (ns): 59.732
|
| 353 |
|
|
External Hold (ns): 0.000
|
| 354 |
|
|
Min Clock-To-Out (ns): 0.000
|
| 355 |
|
|
Max Clock-To-Out (ns): 73.607
|
| 356 |
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|
| 357 |
|
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Input to Output
|
| 358 |
|
|
Min Delay (ns): 0.000
|
| 359 |
|
|
Max Delay (ns): 70.192
|
| 360 |
|
|
|
| 361 |
|
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|
| 362 |
|
|
====================================================================================
|
| 363 |
|
|
Compile report:
|
| 364 |
|
|
===============
|
| 365 |
|
|
|
| 366 |
|
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CORE Used: 4734
|
| 367 |
|
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Core Information:
|
| 368 |
|
|
|
| 369 |
|
|
Type | Instances | Core tiles
|
| 370 |
|
|
--------|--------------|-----------
|
| 371 |
|
|
COMB | 4184 | 4184
|
| 372 |
|
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SEQ | 550 | 550
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
====================================================================================
|
| 376 |
|
|
# SYNTHESIS DONE
|
| 377 |
|
|
#####################################################################################
|
| 378 |
|
|
|
| 379 |
|
|
#####################################################################################
|
| 380 |
|
|
# START SYNTHESIS
|
| 381 |
|
|
#====================================================================================
|
| 382 |
|
|
# Fusion (AFS1500), speedgrade: -1
|
| 383 |
|
|
#====================================================================================
|
| 384 |
|
|
# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
|
| 385 |
|
|
# 12 10 0 0 0 0 0 1
|
| 386 |
|
|
#====================================================================================
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
Clock Domain: dco_clk
|
| 390 |
|
|
Period (ns): 54.158
|
| 391 |
|
|
Frequency (MHz): 18.464
|
| 392 |
|
|
Required Period (ns): 40.000
|
| 393 |
|
|
Required Frequency (MHz): 25.000
|
| 394 |
|
|
External Setup (ns): 46.454
|
| 395 |
|
|
External Hold (ns): 0.600
|
| 396 |
|
|
Min Clock-To-Out (ns): 3.076
|
| 397 |
|
|
Max Clock-To-Out (ns): 62.871
|
| 398 |
|
|
|
| 399 |
|
|
Input to Output
|
| 400 |
|
|
Min Delay (ns): 2.213
|
| 401 |
|
|
Max Delay (ns): 55.167
|
| 402 |
|
|
|
| 403 |
|
|
|
| 404 |
|
|
====================================================================================
|
| 405 |
|
|
Compile report:
|
| 406 |
|
|
===============
|
| 407 |
|
|
|
| 408 |
|
|
CORE Used: 4585
|
| 409 |
|
|
Core Information:
|
| 410 |
|
|
|
| 411 |
|
|
Type | Instances | Core tiles
|
| 412 |
|
|
--------|--------------|-----------
|
| 413 |
|
|
COMB | 4033 | 4033
|
| 414 |
|
|
SEQ | 552 | 552
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
====================================================================================
|
| 418 |
|
|
# SYNTHESIS DONE
|
| 419 |
|
|
#####################################################################################
|
| 420 |
|
|
|
| 421 |
|
|
#####################################################################################
|
| 422 |
|
|
# START SYNTHESIS
|
| 423 |
|
|
#====================================================================================
|
| 424 |
|
|
# Fusion (AFS1500), speedgrade: -2
|
| 425 |
|
|
#====================================================================================
|
| 426 |
|
|
# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
|
| 427 |
|
|
# 12 10 0 0 0 0 0 1
|
| 428 |
|
|
#====================================================================================
|
| 429 |
|
|
|
| 430 |
|
|
|
| 431 |
|
|
Clock Domain: dco_clk
|
| 432 |
|
|
Period (ns): 46.868
|
| 433 |
|
|
Frequency (MHz): 21.337
|
| 434 |
|
|
Required Period (ns): 40.000
|
| 435 |
|
|
Required Frequency (MHz): 25.000
|
| 436 |
|
|
External Setup (ns): 41.526
|
| 437 |
|
|
External Hold (ns): 0.613
|
| 438 |
|
|
Min Clock-To-Out (ns): 3.009
|
| 439 |
|
|
Max Clock-To-Out (ns): 52.492
|
| 440 |
|
|
|
| 441 |
|
|
Input to Output
|
| 442 |
|
|
Min Delay (ns): 2.258
|
| 443 |
|
|
Max Delay (ns): 47.150
|
| 444 |
|
|
|
| 445 |
|
|
|
| 446 |
|
|
====================================================================================
|
| 447 |
|
|
Compile report:
|
| 448 |
|
|
===============
|
| 449 |
|
|
|
| 450 |
|
|
CORE Used: 4573
|
| 451 |
|
|
Core Information:
|
| 452 |
|
|
|
| 453 |
|
|
Type | Instances | Core tiles
|
| 454 |
|
|
--------|--------------|-----------
|
| 455 |
|
|
COMB | 4020 | 4020
|
| 456 |
|
|
SEQ | 553 | 553
|
| 457 |
|
|
|
| 458 |
|
|
|
| 459 |
|
|
====================================================================================
|
| 460 |
|
|
# SYNTHESIS DONE
|
| 461 |
|
|
#####################################################################################
|
| 462 |
|
|
|
| 463 |
|
|
#####################################################################################
|
| 464 |
|
|
# START SYNTHESIS
|
| 465 |
|
|
#====================================================================================
|
| 466 |
|
|
# IGLOOE (AGLE600V5), speedgrade: Std
|
| 467 |
|
|
#====================================================================================
|
| 468 |
|
|
# PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
|
| 469 |
|
|
# 12 10 0 0 0 0 0 1
|
| 470 |
|
|
#====================================================================================
|
| 471 |
|
|
|
| 472 |
|
|
|
| 473 |
|
|
Clock Domain: dco_clk
|
| 474 |
|
|
Period (ns): 68.930
|
| 475 |
|
|
Frequency (MHz): 14.507
|
| 476 |
|
|
Required Period (ns): 40.000
|
| 477 |
|
|
Required Frequency (MHz): 25.000
|
| 478 |
|
|
External Setup (ns): 66.686
|
| 479 |
|
|
External Hold (ns): 0.000
|
| 480 |
|
|
Min Clock-To-Out (ns): 0.000
|
| 481 |
|
|
Max Clock-To-Out (ns): 76.255
|
| 482 |
|
|
|
| 483 |
|
|
Input to Output
|
| 484 |
|
|
Min Delay (ns): 0.000
|
| 485 |
|
|
Max Delay (ns): 74.011
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
====================================================================================
|
| 489 |
|
|
Compile report:
|
| 490 |
|
|
===============
|
| 491 |
|
|
|
| 492 |
|
|
CORE Used: 4844
|
| 493 |
|
|
Core Information:
|
| 494 |
|
|
|
| 495 |
|
|
Type | Instances | Core tiles
|
| 496 |
|
|
--------|--------------|-----------
|
| 497 |
|
|
COMB | 4292 | 4292
|
| 498 |
|
|
SEQ | 552 | 552
|
| 499 |
|
|
|
| 500 |
|
|
|
| 501 |
|
|
====================================================================================
|
| 502 |
|
|
# SYNTHESIS DONE
|
| 503 |
|
|
#####################################################################################
|
| 504 |
|
|
|
| 505 |
|
|
|
| 506 |
|
|
#####################################################################################
|
| 507 |
|
|
# ANALYSIS DONE
|
| 508 |
|
|
#####################################################################################
|
| 509 |
|
|
|
