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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [run_analysis.tcl] - Blame information for rev 74

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#!/usr/bin/tclsh
#------------------------------------------------------------------------------
# Copyright (C) 2001 Authors
#
# This source file may be used and distributed without restriction provided
# that this copyright statement is not removed from the file and that any
# derivative work contains the original copyright notice and the associated
# disclaimer.
#
# This source file is free software; you can redistribute it and/or modify
# it under the terms of the GNU Lesser General Public License as published
# by the Free Software Foundation; either version 2.1 of the License, or
# (at your option) any later version.
#
# This source is distributed in the hope that it will be useful, but WITHOUT
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
# License for more details.
#
# You should have received a copy of the GNU Lesser General Public License
# along with this source; if not, write to the Free Software Foundation,
# Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
#
#------------------------------------------------------------------------------
# 
# File Name: run_analysis.tcl
# 
# Author(s):
#             - Olivier Girard,    olgirard@gmail.com
#
#------------------------------------------------------------------------------
# $Rev: 17 $
# $LastChangedBy: olivier.girard $
# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $
#------------------------------------------------------------------------------
package require Tclx
 
###############################################################################
#                         SET SOME GLOBAL VARIABLES                           #
###############################################################################
 
# Set tools
set SYNPLICITY      "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify.exe"
set LIBERO_DESIGNER "C:\\\\Actel\\\\Libero_v8.5\\\\Designer\\\\bin\\\\designer.exe"
 
# Set the different FPGA architectures & models to be checked (it should have a FBGA484 package)
set fpgaConfigs {{"ProASIC3E"   A3PE1500   {Std -1 -2}}
                 {"ProASIC3L"   A3P1000L   {Std -1}}
                 {"ProASIC3"    A3P1000    {Std -1 -2}}
                 {"Fusion"      AFS1500    {Std -1 -2}}
                 {"IGLOOE"      AGLE600V5  {Std}}}
 
 
# Set the different RTL configurations to be analysed
set rtlDefines  {PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}
set rtlConfigs {{    12          10          0         0            0          0            0         0}
                {    12          10          1         0            0          0            0         0}
                {    12          10          1         1            0          0            0         0}
                {    12          10          1         1            1          0            0         0}
                {    12          10          1         1            1          1            0         0}
                {    12          10          1         1            1          1            1         0}}
set rtlConfigs {{    12          10          0         0            0          0            0         1}}
 
 
# RTL configuration files
set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"
set designFiles    {../../rtl/verilog/openMSP430.v
                    ../../rtl/verilog/omsp_frontend.v
                    ../../rtl/verilog/omsp_execution_unit.v
                    ../../rtl/verilog/omsp_register_file.v
                    ../../rtl/verilog/omsp_alu.v
                    ../../rtl/verilog/omsp_mem_backbone.v
                    ../../rtl/verilog/omsp_clock_module.v
                    ../../rtl/verilog/omsp_sfr.v
                    ../../rtl/verilog/omsp_watchdog.v
                    ../../rtl/verilog/omsp_dbg.v
                    ../../rtl/verilog/omsp_dbg_uart.v
                    ../../rtl/verilog/omsp_dbg_hwbrk.v
                    ../../rtl/verilog/omsp_multiplier.v
                    ../../rtl/verilog/openMSP430_undefines.v
                    ../../rtl/verilog/timescale.v
}
 
###############################################################################
#                              PERFORM ANALYSIS                               #
###############################################################################
proc sleep {time} {
      after [expr $time*1000] set end 1
      vwait end
  }
 
# Copy design files
foreach designFile $designFiles {
        file copy -force $designFile "./src/"
}
 
# Create log file
file delete "./run_analysis.log"
set f_logFile [open "./run_analysis.log" w]
 
# Perform analysis
foreach rtlConfig $rtlConfigs {
 
    #-------------------------------------------------------------------------#
    #                        Generate RTL configuration                       #
    #-------------------------------------------------------------------------#
 
    # Read original define file
    if [catch {open $omspConfigFile r} f_omspConfigFile] {
        puts $f_logFile "ERROR: Cannot open file $omspConfigFile"
        close $f_logFile
        exit 1
    }
    set configFile [read $f_omspConfigFile]
    close $f_omspConfigFile
 
 
    # Update defines
    set idx 0
    foreach rtlDefine $rtlDefines {
 
        if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} {
        } else {
            if {[lindex $rtlConfig $idx]==0} {
                regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile
            }
        }
        set idx [expr $idx+1]
    }
 
 
    # Write the new file
    set f_configFile [open "./src/[file tail $omspConfigFile]" w]
    puts $f_configFile $configFile
    close $f_configFile
 
    #-------------------------------------------------------------------------#
    #                      Perform analysis for each FPGA                     #
    #-------------------------------------------------------------------------#
    foreach fpgaConfig $fpgaConfigs {
        foreach speedGrade [lindex $fpgaConfig 2] {
 
            # Cleanup
            file delete -force ./WORK
        file mkdir ./WORK
        cd ./WORK
 
            # Copy Synplify tcl command files
            if [catch {open "../synplify.tcl" r} f_synplify_tcl] {
                puts $f_logFile "ERROR: Cannot open Synplify command file file ../synplify.tcl"
                close $f_logFile
                exit 1
            }
            set synplify_tcl [read $f_synplify_tcl]
            close $f_synplify_tcl
 
            regsub -all {<DEVICE_NAME>}   $synplify_tcl "[string toupper [lindex $fpgaConfig 1]]" synplify_tcl
            regsub -all {<DEVICE_FAMILY>} $synplify_tcl "[string toupper [lindex $fpgaConfig 0]]" synplify_tcl
            regsub -all {<SPEED_GRADE>}   $synplify_tcl "$speedGrade"                             synplify_tcl
 
            set f_synplify_tcl [open "synplify.tcl" w]
            puts $f_synplify_tcl $synplify_tcl
            close $f_synplify_tcl
 
                # Copy Libero Designer tcl command files
            if [catch {open "../libero_designer.tcl" r} f_libero_designer_tcl] {
                puts $f_logFile "ERROR: Cannot open Libero Designer command file file ../libero_designer.tcl"
                close $f_logFile
                exit 1
            }
            set libero_designer_tcl [read $f_libero_designer_tcl]
            close $f_libero_designer_tcl
 
            regsub -all {<DEVICE_NAME>}   $libero_designer_tcl "[lindex $fpgaConfig 1]" libero_designer_tcl
            regsub -all {<DEVICE_FAMILY>} $libero_designer_tcl "[lindex $fpgaConfig 0]" libero_designer_tcl
            regsub -all {<SPEED_GRADE>}   $libero_designer_tcl "$speedGrade"            libero_designer_tcl
 
            set f_libero_designer_tcl [open "libero_designer.tcl" w]
            puts $f_libero_designer_tcl $libero_designer_tcl
            close $f_libero_designer_tcl
 
            # Run synthesis
            puts $f_logFile "#####################################################################################"
            puts $f_logFile "#                            START SYNTHESIS"
            puts $f_logFile "#===================================================================================="
            puts $f_logFile "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: $speedGrade"
            puts $f_logFile "#===================================================================================="
            puts $f_logFile "# $rtlDefines"
            puts $f_logFile "# $rtlConfig"
            puts $f_logFile "#===================================================================================="
                flush $f_logFile
 
                # Run synthesis
                set synplify_done 0
                while {[string eq $synplify_done 0]} {
 
                        sleep 10
                        eval exec $SYNPLICITY synplify.tcl
                        sleep 30
 
                        # Wait until EDIF file is generated
                        set synplify_timeout 0
 
#                       puts  $f_logFile "START LOOP: $synplify_timeout ($synplify_done)"
#                       flush $f_logFile
 
                        while {!([file exists "./rev_1/design_files.edn"] | ($synplify_timeout==100))} {
                                sleep 6
#                               puts  $f_logFile "YOPYOP: $synplify_timeout"
#                               flush $f_logFile
                                set synplify_timeout [expr $synplify_timeout+1]
                        }
                        if ($synplify_timeout<100) {
                           set synplify_done 1
                        }
#                       puts  $f_logFile "DONE: $synplify_timeout ($synplify_done)"
#                       flush $f_logFile
 
                        # Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script
                        sleep 10
                        eval exec taskkill /IM synplify.exe
                        sleep 20
                        if {[string eq $synplify_done 0]} {
                                sleep 180
                        }
                }
#               puts  $f_logFile "SYNPLIFY DONE: $synplify_timeout ($synplify_done)"
#               flush $f_logFile
 
                # Run place & route
                eval exec $LIBERO_DESIGNER script:libero_designer.tcl logfile:libero_designer.log
 
 
                # Extract timing information
            if [catch {open "report_timing_max.txt" r} f_timing] {
                    puts $f_logFile "ERROR: Cannot open timing file"
                        close $f_logFile
                    exit 1
            }
            set timingFile [read $f_timing]
            close $f_timing
                regexp {SUMMARY(.*)END SUMMARY} $timingFile whole_match timing
            puts $f_logFile $timing
            puts $f_logFile "===================================================================================="
 
            # Extract size information
            if [catch {open "report_status.txt" r} f_area] {
                puts $f_logFile "ERROR: Cannot open status file: report_status.txt"
                close $f_logFile
                exit 1
            }
            set areaFile [read $f_area]
            close $f_area
            regexp {(Compile report:.*?)Total:} $areaFile whole_match area1
            regexp {(Core Information:.*?)I/O Function:} $areaFile whole_match area2
            puts $f_logFile $area1
            puts $f_logFile $area2
            puts $f_logFile "===================================================================================="
 
            puts $f_logFile "#                            SYNTHESIS DONE"
            puts $f_logFile "#####################################################################################"
            puts $f_logFile ""
                flush $f_logFile
            cd ../
                sleep 3
        }
    }
 
}
puts $f_logFile ""
puts $f_logFile "#####################################################################################"
puts $f_logFile "#                            ANALYSIS DONE"
puts $f_logFile "#####################################################################################"
puts $f_logFile ""
close $f_logFile
exit 0

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Subversion Repositories openmsp430

[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [run_analysis.tcl] - Blame information for rev 74

Line No.	Rev	Author	Line
1	64	olivier.gi	`#!/usr/bin/tclsh`
2			`#------------------------------------------------------------------------------`
3			`# Copyright (C) 2001 Authors`
4			`#`
5			`# This source file may be used and distributed without restriction provided`
6			`# that this copyright statement is not removed from the file and that any`
7			`# derivative work contains the original copyright notice and the associated`
8			`# disclaimer.`
9			`#`
10			`# This source file is free software; you can redistribute it and/or modify`
11			`# it under the terms of the GNU Lesser General Public License as published`
12			`# by the Free Software Foundation; either version 2.1 of the License, or`
13			`# (at your option) any later version.`
14			`#`
15			`# This source is distributed in the hope that it will be useful, but WITHOUT`
16			`# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
17			`# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
18			`# License for more details.`
19			`#`
20			`# You should have received a copy of the GNU Lesser General Public License`
21			`# along with this source; if not, write to the Free Software Foundation,`
22			`# Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
23			`#`
24			`#------------------------------------------------------------------------------`
25			`#`
26			`# File Name: run_analysis.tcl`
27			`#`
28			`# Author(s):`
29			`# - Olivier Girard, olgirard@gmail.com`
30			`#`
31			`#------------------------------------------------------------------------------`
32			`# $Rev: 17 $`
33			`# $LastChangedBy: olivier.girard $`
34			`# $LastChangedDate: 2009-08-04 23:15:39 +0200 (Tue, 04 Aug 2009) $`
35			`#------------------------------------------------------------------------------`
36			`package require Tclx`
37
38			`###############################################################################`
39			`# SET SOME GLOBAL VARIABLES #`
40			`###############################################################################`
41
42			`# Set tools`
43			`set SYNPLICITY "C:\\\\Actel\\\\Libero_v8.5\\\\Synplify\\\\synplify_96A\\\\bin\\\\synplify.exe"`
44			`set LIBERO_DESIGNER "C:\\\\Actel\\\\Libero_v8.5\\\\Designer\\\\bin\\\\designer.exe"`
45
46			`# Set the different FPGA architectures & models to be checked (it should have a FBGA484 package)`
47			`set fpgaConfigs {{"ProASIC3E" A3PE1500 {Std -1 -2}}`
48			`{"ProASIC3L" A3P1000L {Std -1}}`
49			`{"ProASIC3" A3P1000 {Std -1 -2}}`
50			`{"Fusion" AFS1500 {Std -1 -2}}`
51			`{"IGLOOE" AGLE600V5 {Std}}}`
52
53
54			`# Set the different RTL configurations to be analysed`
55	68	olivier.gi	`set rtlDefines {PMEM_AWIDTH DMEM_AWIDTH DBG_EN DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER}`
56			`set rtlConfigs {{ 12 10 0 0 0 0 0 0}`
57			`{ 12 10 1 0 0 0 0 0}`
58			`{ 12 10 1 1 0 0 0 0}`
59			`{ 12 10 1 1 1 0 0 0}`
60			`{ 12 10 1 1 1 1 0 0}`
61			`{ 12 10 1 1 1 1 1 0}}`
62			`set rtlConfigs {{ 12 10 0 0 0 0 0 1}}`
63	64	olivier.gi
64
65			`# RTL configuration files`
66			`set omspConfigFile "../../rtl/verilog/openMSP430_defines.v"`
67			`set designFiles {../../rtl/verilog/openMSP430.v`
68			`../../rtl/verilog/omsp_frontend.v`
69			`../../rtl/verilog/omsp_execution_unit.v`
70			`../../rtl/verilog/omsp_register_file.v`
71			`../../rtl/verilog/omsp_alu.v`
72			`../../rtl/verilog/omsp_mem_backbone.v`
73			`../../rtl/verilog/omsp_clock_module.v`
74			`../../rtl/verilog/omsp_sfr.v`
75			`../../rtl/verilog/omsp_watchdog.v`
76			`../../rtl/verilog/omsp_dbg.v`
77			`../../rtl/verilog/omsp_dbg_uart.v`
78			`../../rtl/verilog/omsp_dbg_hwbrk.v`
79	68	olivier.gi	`../../rtl/verilog/omsp_multiplier.v`
80			`../../rtl/verilog/openMSP430_undefines.v`
81			`../../rtl/verilog/timescale.v`
82	64	olivier.gi	`}`
83
84			`###############################################################################`
85			`# PERFORM ANALYSIS #`
86			`###############################################################################`
87			`proc sleep {time} {`
88			`after [expr $time*1000] set end 1`
89			`vwait end`
90			`}`
91
92			`# Copy design files`
93			`foreach designFile $designFiles {`
94			`file copy -force $designFile "./src/"`
95			`}`
96
97			`# Create log file`
98			`file delete "./run_analysis.log"`
99			`set f_logFile [open "./run_analysis.log" w]`
100
101			`# Perform analysis`
102			`foreach rtlConfig $rtlConfigs {`
103
104			`#-------------------------------------------------------------------------#`
105			`# Generate RTL configuration #`
106			`#-------------------------------------------------------------------------#`
107
108			`# Read original define file`
109			`if [catch {open $omspConfigFile r} f_omspConfigFile] {`
110			`puts $f_logFile "ERROR: Cannot open file $omspConfigFile"`
111			`close $f_logFile`
112			`exit 1`
113			`}`
114			`set configFile [read $f_omspConfigFile]`
115			`close $f_omspConfigFile`
116
117
118			`# Update defines`
119			`set idx 0`
120			`foreach rtlDefine $rtlDefines {`
121
122			if {[regsub "`define\\s+$rtlDefine\\s+\\d+" $configFile "`define $rtlDefine [lindex $rtlConfig $idx]" configFile]} {
123			`} else {`
124			`if {[lindex $rtlConfig $idx]==0} {`
125			regsub "\\n`define\\s+$rtlDefine" $configFile "\n//`define $rtlDefine" configFile
126			`}`
127			`}`
128			`set idx [expr $idx+1]`
129			`}`
130
131
132			`# Write the new file`
133			`set f_configFile [open "./src/[file tail $omspConfigFile]" w]`
134			`puts $f_configFile $configFile`
135			`close $f_configFile`
136
137			`#-------------------------------------------------------------------------#`
138			`# Perform analysis for each FPGA #`
139			`#-------------------------------------------------------------------------#`
140			`foreach fpgaConfig $fpgaConfigs {`
141			`foreach speedGrade [lindex $fpgaConfig 2] {`
142
143			`# Cleanup`
144			`file delete -force ./WORK`
145			`file mkdir ./WORK`
146			`cd ./WORK`
147
148			`# Copy Synplify tcl command files`
149			`if [catch {open "../synplify.tcl" r} f_synplify_tcl] {`
150			`puts $f_logFile "ERROR: Cannot open Synplify command file file ../synplify.tcl"`
151			`close $f_logFile`
152			`exit 1`
153			`}`
154			`set synplify_tcl [read $f_synplify_tcl]`
155			`close $f_synplify_tcl`
156
157			`regsub -all {<DEVICE_NAME>} $synplify_tcl "[string toupper [lindex $fpgaConfig 1]]" synplify_tcl`
158			`regsub -all {<DEVICE_FAMILY>} $synplify_tcl "[string toupper [lindex $fpgaConfig 0]]" synplify_tcl`
159			`regsub -all {<SPEED_GRADE>} $synplify_tcl "$speedGrade" synplify_tcl`
160
161			`set f_synplify_tcl [open "synplify.tcl" w]`
162			`puts $f_synplify_tcl $synplify_tcl`
163			`close $f_synplify_tcl`
164
165			`# Copy Libero Designer tcl command files`
166			`if [catch {open "../libero_designer.tcl" r} f_libero_designer_tcl] {`
167			`puts $f_logFile "ERROR: Cannot open Libero Designer command file file ../libero_designer.tcl"`
168			`close $f_logFile`
169			`exit 1`
170			`}`
171			`set libero_designer_tcl [read $f_libero_designer_tcl]`
172			`close $f_libero_designer_tcl`
173
174			`regsub -all {<DEVICE_NAME>} $libero_designer_tcl "[lindex $fpgaConfig 1]" libero_designer_tcl`
175			`regsub -all {<DEVICE_FAMILY>} $libero_designer_tcl "[lindex $fpgaConfig 0]" libero_designer_tcl`
176			`regsub -all {<SPEED_GRADE>} $libero_designer_tcl "$speedGrade" libero_designer_tcl`
177
178			`set f_libero_designer_tcl [open "libero_designer.tcl" w]`
179			`puts $f_libero_designer_tcl $libero_designer_tcl`
180			`close $f_libero_designer_tcl`
181
182			`# Run synthesis`
183			`puts $f_logFile "#####################################################################################"`
184			`puts $f_logFile "# START SYNTHESIS"`
185			`puts $f_logFile "#===================================================================================="`
186			`puts $f_logFile "# [lindex $fpgaConfig 0] ([lindex $fpgaConfig 1]), speedgrade: $speedGrade"`
187			`puts $f_logFile "#===================================================================================="`
188			`puts $f_logFile "# $rtlDefines"`
189			`puts $f_logFile "# $rtlConfig"`
190			`puts $f_logFile "#===================================================================================="`
191			`flush $f_logFile`
192
193			`# Run synthesis`
194			`set synplify_done 0`
195			`while {[string eq $synplify_done 0]} {`
196
197			`sleep 10`
198			`eval exec $SYNPLICITY synplify.tcl`
199			`sleep 30`
200
201			`# Wait until EDIF file is generated`
202			`set synplify_timeout 0`
203
204			`# puts $f_logFile "START LOOP: $synplify_timeout ($synplify_done)"`
205			`# flush $f_logFile`
206
207			`while {!([file exists "./rev_1/design_files.edn"] \| ($synplify_timeout==100))} {`
208			`sleep 6`
209			`# puts $f_logFile "YOPYOP: $synplify_timeout"`
210			`# flush $f_logFile`
211			`set synplify_timeout [expr $synplify_timeout+1]`
212			`}`
213			`if ($synplify_timeout<100) {`
214			`set synplify_done 1`
215			`}`
216			`# puts $f_logFile "DONE: $synplify_timeout ($synplify_done)"`
217			`# flush $f_logFile`
218
219			`# Kill the Synplify task with taskkill since it can't be properly closed with the synplify.tcl script`
220			`sleep 10`
221			`eval exec taskkill /IM synplify.exe`
222			`sleep 20`
223			`if {[string eq $synplify_done 0]} {`
224			`sleep 180`
225			`}`
226			`}`
227			`# puts $f_logFile "SYNPLIFY DONE: $synplify_timeout ($synplify_done)"`
228			`# flush $f_logFile`
229
230			`# Run place & route`
231			`eval exec $LIBERO_DESIGNER script:libero_designer.tcl logfile:libero_designer.log`
232
233
234			`# Extract timing information`
235			`if [catch {open "report_timing_max.txt" r} f_timing] {`
236			`puts $f_logFile "ERROR: Cannot open timing file"`
237			`close $f_logFile`
238			`exit 1`
239			`}`
240			`set timingFile [read $f_timing]`
241			`close $f_timing`
242			`regexp {SUMMARY(.*)END SUMMARY} $timingFile whole_match timing`
243			`puts $f_logFile $timing`
244			`puts $f_logFile "===================================================================================="`
245
246			`# Extract size information`
247			`if [catch {open "report_status.txt" r} f_area] {`
248			`puts $f_logFile "ERROR: Cannot open status file: report_status.txt"`
249			`close $f_logFile`
250			`exit 1`
251			`}`
252			`set areaFile [read $f_area]`
253			`close $f_area`
254			`regexp {(Compile report:.*?)Total:} $areaFile whole_match area1`
255			`regexp {(Core Information:.*?)I/O Function:} $areaFile whole_match area2`
256			`puts $f_logFile $area1`
257			`puts $f_logFile $area2`
258			`puts $f_logFile "===================================================================================="`
259
260			`puts $f_logFile "# SYNTHESIS DONE"`
261			`puts $f_logFile "#####################################################################################"`
262			`puts $f_logFile ""`
263			`flush $f_logFile`
264			`cd ../`
265			`sleep 3`
266			`}`
267			`}`
268
269			`}`
270			`puts $f_logFile ""`
271			`puts $f_logFile "#####################################################################################"`
272			`puts $f_logFile "# ANALYSIS DONE"`
273			`puts $f_logFile "#####################################################################################"`
274			`puts $f_logFile ""`
275			`close $f_logFile`
276			`exit 0`