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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [synplify.tcl] - Blame information for rev 99

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#add_file options
add_file -verilog    "../design_files.v"
add_file -constraint "../design_files.sdc"
 
 
#implementation: "rev_1"
impl -add rev_1 -type fpga
 
#device options
set_option -technology  <DEVICE_FAMILY>
set_option -part        <DEVICE_NAME>
set_option -package     FBGA484
set_option -speed_grade <SPEED_GRADE>
set_option -part_companion ""
 
#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "openMSP430"
 
#map options
set_option -frequency 30.000
set_option -vendor_xcompatible_mode 0
set_option -vendor_xcompatible_mode 0
set_option -run_prop_extract 1
set_option -fanout_limit 24
set_option -globalthreshold 50
set_option -maxfan_hard 0
set_option -disable_io_insertion 0
set_option -retiming 0
set_option -report_path 4000
set_option -opcond COMWC
set_option -update_models_cp 0
set_option -preserve_registers 0
 
 
#sequential_optimizations options
set_option -symbolic_fsm_compiler 1
 
#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0
 
#automatic place and route (vendor) options
set_option -write_apr_constraint 1
 
#set result format/file last
project -result_format "edif"
project -result_file "./rev_1/design_files.edn"
 
#
#implementation attributes
 
set_option -vlog_std v2001
set_option -dup 0
set_option -project_relative_includes 1
impl -active "rev_1"
 
 
# Run synthesis
project -run synthesis
 
# Save and quit
project -save rev_1.prj
 
#exit 0
 

Line No.	Rev	Author	Line
1	64	olivier.gi
2
3
4			`#add_file options`
5			`add_file -verilog "../design_files.v"`
6			`add_file -constraint "../design_files.sdc"`
7
8
9			`#implementation: "rev_1"`
10			`impl -add rev_1 -type fpga`
11
12			`#device options`
13			`set_option -technology <DEVICE_FAMILY>`
14			`set_option -part <DEVICE_NAME>`
15			`set_option -package FBGA484`
16			`set_option -speed_grade <SPEED_GRADE>`
17			`set_option -part_companion ""`
18
19			`#compilation/mapping options`
20			`set_option -default_enum_encoding default`
21			`set_option -resource_sharing 1`
22			`set_option -use_fsm_explorer 0`
23			`set_option -top_module "openMSP430"`
24
25			`#map options`
26			`set_option -frequency 30.000`
27			`set_option -vendor_xcompatible_mode 0`
28			`set_option -vendor_xcompatible_mode 0`
29			`set_option -run_prop_extract 1`
30			`set_option -fanout_limit 24`
31			`set_option -globalthreshold 50`
32			`set_option -maxfan_hard 0`
33			`set_option -disable_io_insertion 0`
34			`set_option -retiming 0`
35			`set_option -report_path 4000`
36			`set_option -opcond COMWC`
37			`set_option -update_models_cp 0`
38			`set_option -preserve_registers 0`
39
40
41			`#sequential_optimizations options`
42			`set_option -symbolic_fsm_compiler 1`
43
44			`#simulation options`
45			`set_option -write_verilog 0`
46			`set_option -write_vhdl 0`
47
48			`#automatic place and route (vendor) options`
49			`set_option -write_apr_constraint 1`
50
51			`#set result format/file last`
52			`project -result_format "edif"`
53			`project -result_file "./rev_1/design_files.edn"`
54
55			`#`
56			`#implementation attributes`
57
58			`set_option -vlog_std v2001`
59			`set_option -dup 0`
60			`set_option -project_relative_includes 1`
61			`impl -active "rev_1"`
62
63
64			`# Run synthesis`
65			`project -run synthesis`
66
67			`# Save and quit`
68			`project -save rev_1.prj`
69
70			`#exit 0`
71

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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [actel/] [synplify.tcl] - Blame information for rev 99