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olivier.gi |
# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# Quartus II: Generate Tcl File for Project
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# File: openMSP430_fpga.tcl
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# Generated on: Tue Jan 19 23:11:05 2010
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# Load Quartus II Tcl packages
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package require ::quartus::project
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package require ::quartus::flow
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# Create project
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project_new -revision openMSP430_fpga openMSP430_fpga
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# Make assignments
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set_global_assignment -name DEVICE <DEVICE_NAME>
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set_global_assignment -name FAMILY "<DEVICE_FAMILY>"
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set_global_assignment -name VERILOG_FILE ..\\design_files.v
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set_global_assignment -name SEARCH_PATH ..\\src/
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set_global_assignment -name FMAX_REQUIREMENT "240 MHz" -section_id main_clock
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set_instance_assignment -name CLOCK_SETTINGS main_clock -to dco_clk
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set_global_assignment -name OPTIMIZATION_TECHNIQUE <SPEED_AREA>
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE <SPEED_AREA>
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set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE <SPEED_AREA>
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set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE <SPEED_AREA>
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
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set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name CDF_FILE Chain1.cdf
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
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# Commit assignments
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export_assignments
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# Run synthesis
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execute_flow -compile
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