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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: openMSP430_defines.v
// 
// *Module Description:
//                      openMSP430 Configuration file
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 57 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $
//----------------------------------------------------------------------------
`include "openMSP430_undefines.v"
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// Program Memory Size:
//                    9 ->  1 kB
//                   10 ->  2 kB
//                   11 ->  4 kB
//                   12 ->  8 kB
//                   13 -> 16 kB
//                   14 -> 32 kB
`define PMEM_AWIDTH 12
 
// Data Memory Size:
//                    6 ->  128 B
//                    7 ->  256 B
//                    8 ->  512 B
//                    9 ->    1 kB
//                   10 ->    2 kB
//                   11 ->    4 kB
//                   12 ->    8 kB
//                   13 ->   16 kB
//                   14 ->   32 kB
`define DMEM_AWIDTH 10
 
// Include/Exclude Hardware Multiplier
`define MULTIPLIER
 
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
//`define DBG_EN
 
// Debug interface selection
//             `define DBG_UART -> Enable UART (8N1) debug interface
//             `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
//
`define DBG_UART
//`define DBG_JTAG
 
// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)
//             `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
//             `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
//             `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
//             `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
//
//`define DBG_HWBRK_0
//`define DBG_HWBRK_1
//`define DBG_HWBRK_2
//`define DBG_HWBRK_3
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Program and Data Memory sizes
`define PMEM_SIZE  (2 << `PMEM_AWIDTH)
`define DMEM_SIZE  (2 << `DMEM_AWIDTH)
 
// Data Memory Base Adresses
`define DMEM_BASE  16'h0200
 
// Program & Data Memory most significant address bit (for 16 bit words)
`define PMEM_MSB   `PMEM_AWIDTH-1
`define DMEM_MSB   `DMEM_AWIDTH-1
 
 
// Instructions type
`define INST_SO  0
`define INST_JMP 1
`define INST_TO  2
 
// Single-operand arithmetic
`define RRC    0
`define SWPB   1
`define RRA    2
`define SXT    3
`define PUSH   4
`define CALL   5
`define RETI   6
`define IRQ    7
 
// Conditional jump
`define JNE    0
`define JEQ    1
`define JNC    2
`define JC     3
`define JN     4
`define JGE    5
`define JL     6
`define JMP    7
 
// Two-operand arithmetic
`define MOV    0
`define ADD    1
`define ADDC   2
`define SUBC   3
`define SUB    4
`define CMP    5
`define DADD   6
`define BIT    7
`define BIC    8
`define BIS    9
`define XOR   10
`define AND   11
 
// Addressing modes
`define DIR      0
`define IDX      1
`define INDIR    2
`define INDIR_I  3
`define SYMB     4
`define IMM      5
`define ABS      6
`define CONST    7
 
// Execution state machine
`define E_IRQ_0    4'h0
`define E_IRQ_1    4'h1
`define E_IRQ_2    4'h2
`define E_IRQ_3    4'h3
`define E_IRQ_4    4'h4
`define E_SRC_AD   4'h5
`define E_SRC_RD   4'h6
`define E_SRC_WR   4'h7
`define E_DST_AD   4'h8
`define E_DST_RD   4'h9
`define E_DST_WR   4'hA
`define E_EXEC     4'hB
`define E_JUMP     4'hC
`define E_IDLE     4'hD
 
// ALU control signals
`define ALU_SRC_INV   0
`define ALU_INC       1
`define ALU_INC_C     2
`define ALU_ADD       3
`define ALU_AND       4
`define ALU_OR        5
`define ALU_XOR       6
`define ALU_DADD      7
`define ALU_STAT_7    8
`define ALU_STAT_F    9
`define ALU_SHIFT    10
`define EXEC_NO_WR   11
 
// Debug interface
`define DBG_UART_WR   18
`define DBG_UART_BW   17
`define DBG_UART_ADDR 16:11
 
// Debug interface CPU_CTL register
`define HALT        0
`define RUN         1
`define ISTEP       2
`define SW_BRK_EN   3
`define FRZ_BRK_EN  4
`define RST_BRK_EN  5
`define CPU_RST     6
 
// Debug interface CPU_STAT register
`define HALT_RUN    0
`define PUC_PND     1
`define SWBRK_PND   3
`define HWBRK0_PND  4
`define HWBRK1_PND  5
 
// Debug interface BRKx_CTL register
`define BRK_MODE_RD 0
`define BRK_MODE_WR 1
`define BRK_MODE    1:0
`define BRK_EN      2
`define BRK_I_EN    3
`define BRK_RANGE   4
 
// Basic clock module: BCSCTL1 Control Register
`define DIVAx       5:4
 
// Basic clock module: BCSCTL2 Control Register
`define SELS        3
`define DIVSx       2:1
 
// Timer A: TACTL Control Register
`define TASSELx     9:8
`define TAIDx       7:6
`define TAMCx       5:4
`define TACLR       2
`define TAIE        1
`define TAIFG       0
 
// Timer A: TACCTLx Capture/Compare Control Register
`define TACMx      15:14
`define TACCISx    13:12
`define TASCS      11
`define TASCCI     10
`define TACAP       8
`define TAOUTMODx   7:5
`define TACCIE      4
`define TACCI       3
`define TAOUT       2
`define TACOV       1
`define TACCIFG     0
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`define DBG_SWBRK_OP 16'h4343
 
// Debug interface ID
`define DBG_ID  24'h4D5350
 
// Debug UART interface auto data synchronization
// If the following define is commented out, then
// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly
// defined.
`define DBG_UART_AUTO_SYNC
 
// Debug UART interface data rate
//      In order to properly setup the UART debug interface, you
//      need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and
//      the chosen BAUD rate from the UART interface.
//
//`define DBG_UART_BAUD    9600
//`define DBG_UART_BAUD   19200
//`define DBG_UART_BAUD   38400
//`define DBG_UART_BAUD   57600
//`define DBG_UART_BAUD  115200
//`define DBG_UART_BAUD  230400
//`define DBG_UART_BAUD  460800
//`define DBG_UART_BAUD  576000
//`define DBG_UART_BAUD  921600
`define DBG_UART_BAUD 2000000
`define DBG_DCO_FREQ  20000000
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
 
// Enable/Disable the hardware breakpoint RANGE mode
`define HWBRK_RANGE 1'b0
 
// Check configuration
`ifdef DBG_EN
 `ifdef DBG_UART
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED
   `endif
 `else
   `ifdef DBG_JTAG
CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED
   `else
CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED
   `endif
 `endif
`endif
 
//
// MULTIPLIER CONFIGURATION
//======================================
 
// If uncommented, the following define selects
// the 16x16 multiplier (1 cycle) instead of the
// default 16x8 multplier (2 cycles)
//`define MPY_16x16
 

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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [altera/] [src/] [openMSP430_defines.v] - Blame information for rev 141

Line No.	Rev	Author	Line
1	63	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: openMSP430_defines.v`
26			`//`
27			`// *Module Description:`
28			`// openMSP430 Configuration file`
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev: 57 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2010-02-01 23:56:03 +0100 (Mon, 01 Feb 2010) $`
37			`//----------------------------------------------------------------------------`
38			`include "openMSP430_undefines.v"
39
40			`//----------------------------------------------------------------------------`
41			`// SYSTEM CONFIGURATION`
42			`//----------------------------------------------------------------------------`
43
44			`// Program Memory Size:`
45			`// 9 -> 1 kB`
46			`// 10 -> 2 kB`
47			`// 11 -> 4 kB`
48			`// 12 -> 8 kB`
49			`// 13 -> 16 kB`
50			`// 14 -> 32 kB`
51			`define PMEM_AWIDTH 12
52
53			`// Data Memory Size:`
54			`// 6 -> 128 B`
55			`// 7 -> 256 B`
56			`// 8 -> 512 B`
57			`// 9 -> 1 kB`
58			`// 10 -> 2 kB`
59			`// 11 -> 4 kB`
60			`// 12 -> 8 kB`
61			`// 13 -> 16 kB`
62			`// 14 -> 32 kB`
63			`define DMEM_AWIDTH 10
64
65	68	olivier.gi	`// Include/Exclude Hardware Multiplier`
66			`define MULTIPLIER
67
68
69	63	olivier.gi	`//----------------------------------------------------------------------------`
70			`// REMOTE DEBUGGING INTERFACE CONFIGURATION`
71			`//----------------------------------------------------------------------------`
72
73			`// Include Debug interface`
74			//`define DBG_EN
75
76			`// Debug interface selection`
77			// `define DBG_UART -> Enable UART (8N1) debug interface
78			// `define DBG_JTAG -> DON'T UNCOMMENT, NOT SUPPORTED
79			`//`
80			`define DBG_UART
81			//`define DBG_JTAG
82
83			`// Number of hardware breakpoints (each unit contains 2 hw address breakpoints)`
84			// `define DBG_HWBRK_0 -> Include hardware breakpoints unit 0
85			// `define DBG_HWBRK_1 -> Include hardware breakpoints unit 1
86			// `define DBG_HWBRK_2 -> Include hardware breakpoints unit 2
87			// `define DBG_HWBRK_3 -> Include hardware breakpoints unit 3
88			`//`
89			//`define DBG_HWBRK_0
90			//`define DBG_HWBRK_1
91			//`define DBG_HWBRK_2
92			//`define DBG_HWBRK_3
93
94
95			`//==========================================================================//`
96			`//==========================================================================//`
97			`//==========================================================================//`
98			`//==========================================================================//`
99			`//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//`
100			`//==========================================================================//`
101			`//==========================================================================//`
102			`//==========================================================================//`
103			`//==========================================================================//`
104
105			`// Program and Data Memory sizes`
106			`define PMEM_SIZE (2 << `PMEM_AWIDTH)
107			`define DMEM_SIZE (2 << `DMEM_AWIDTH)
108
109			`// Data Memory Base Adresses`
110			`define DMEM_BASE 16'h0200
111
112			`// Program & Data Memory most significant address bit (for 16 bit words)`
113			`define PMEM_MSB `PMEM_AWIDTH-1
114			`define DMEM_MSB `DMEM_AWIDTH-1
115
116
117			`// Instructions type`
118			`define INST_SO 0
119			`define INST_JMP 1
120			`define INST_TO 2
121
122			`// Single-operand arithmetic`
123			`define RRC 0
124			`define SWPB 1
125			`define RRA 2
126			`define SXT 3
127			`define PUSH 4
128			`define CALL 5
129			`define RETI 6
130			`define IRQ 7
131
132			`// Conditional jump`
133			`define JNE 0
134			`define JEQ 1
135			`define JNC 2
136			`define JC 3
137			`define JN 4
138			`define JGE 5
139			`define JL 6
140			`define JMP 7
141
142			`// Two-operand arithmetic`
143			`define MOV 0
144			`define ADD 1
145			`define ADDC 2
146			`define SUBC 3
147			`define SUB 4
148			`define CMP 5
149			`define DADD 6
150			`define BIT 7
151			`define BIC 8
152			`define BIS 9
153			`define XOR 10
154			`define AND 11
155
156			`// Addressing modes`
157			`define DIR 0
158			`define IDX 1
159			`define INDIR 2
160			`define INDIR_I 3
161			`define SYMB 4
162			`define IMM 5
163			`define ABS 6
164			`define CONST 7
165
166			`// Execution state machine`
167			`define E_IRQ_0 4'h0
168			`define E_IRQ_1 4'h1
169			`define E_IRQ_2 4'h2
170			`define E_IRQ_3 4'h3
171			`define E_IRQ_4 4'h4
172			`define E_SRC_AD 4'h5
173			`define E_SRC_RD 4'h6
174			`define E_SRC_WR 4'h7
175			`define E_DST_AD 4'h8
176			`define E_DST_RD 4'h9
177			`define E_DST_WR 4'hA
178			`define E_EXEC 4'hB
179			`define E_JUMP 4'hC
180			`define E_IDLE 4'hD
181
182			`// ALU control signals`
183			`define ALU_SRC_INV 0
184			`define ALU_INC 1
185			`define ALU_INC_C 2
186			`define ALU_ADD 3
187			`define ALU_AND 4
188			`define ALU_OR 5
189			`define ALU_XOR 6
190			`define ALU_DADD 7
191			`define ALU_STAT_7 8
192			`define ALU_STAT_F 9
193			`define ALU_SHIFT 10
194			`define EXEC_NO_WR 11
195
196			`// Debug interface`
197			`define DBG_UART_WR 18
198			`define DBG_UART_BW 17
199			`define DBG_UART_ADDR 16:11
200
201			`// Debug interface CPU_CTL register`
202			`define HALT 0
203			`define RUN 1
204			`define ISTEP 2
205			`define SW_BRK_EN 3
206			`define FRZ_BRK_EN 4
207			`define RST_BRK_EN 5
208			`define CPU_RST 6
209
210			`// Debug interface CPU_STAT register`
211			`define HALT_RUN 0
212			`define PUC_PND 1
213			`define SWBRK_PND 3
214			`define HWBRK0_PND 4
215			`define HWBRK1_PND 5
216
217			`// Debug interface BRKx_CTL register`
218			`define BRK_MODE_RD 0
219			`define BRK_MODE_WR 1
220			`define BRK_MODE 1:0
221			`define BRK_EN 2
222			`define BRK_I_EN 3
223			`define BRK_RANGE 4
224
225			`// Basic clock module: BCSCTL1 Control Register`
226			`define DIVAx 5:4
227
228			`// Basic clock module: BCSCTL2 Control Register`
229			`define SELS 3
230			`define DIVSx 2:1
231
232			`// Timer A: TACTL Control Register`
233			`define TASSELx 9:8
234			`define TAIDx 7:6
235			`define TAMCx 5:4
236			`define TACLR 2
237			`define TAIE 1
238			`define TAIFG 0
239
240			`// Timer A: TACCTLx Capture/Compare Control Register`
241			`define TACMx 15:14
242			`define TACCISx 13:12
243			`define TASCS 11
244			`define TASCCI 10
245			`define TACAP 8
246			`define TAOUTMODx 7:5
247			`define TACCIE 4
248			`define TACCI 3
249			`define TAOUT 2
250			`define TACOV 1
251			`define TACCIFG 0
252
253			`//`
254			`// DEBUG INTERFACE EXTRA CONFIGURATION`
255			`//======================================`
256
257			`// Debug interface: Software breakpoint opcode`
258			`define DBG_SWBRK_OP 16'h4343
259
260			`// Debug interface ID`
261			`define DBG_ID 24'h4D5350
262
263			`// Debug UART interface auto data synchronization`
264			`// If the following define is commented out, then`
265			`// the DBG_UART_BAUD and DBG_DCO_FREQ need to be properly`
266			`// defined.`
267			`define DBG_UART_AUTO_SYNC
268
269			`// Debug UART interface data rate`
270			`// In order to properly setup the UART debug interface, you`
271			`// need to specify the DCO_CLK frequency (DBG_DCO_FREQ) and`
272			`// the chosen BAUD rate from the UART interface.`
273			`//`
274			//`define DBG_UART_BAUD 9600
275			//`define DBG_UART_BAUD 19200
276			//`define DBG_UART_BAUD 38400
277			//`define DBG_UART_BAUD 57600
278			//`define DBG_UART_BAUD 115200
279			//`define DBG_UART_BAUD 230400
280			//`define DBG_UART_BAUD 460800
281			//`define DBG_UART_BAUD 576000
282			//`define DBG_UART_BAUD 921600
283			`define DBG_UART_BAUD 2000000
284			`define DBG_DCO_FREQ 20000000
285			`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1)
286
287			`// Enable/Disable the hardware breakpoint RANGE mode`
288			`define HWBRK_RANGE 1'b0
289
290			`// Check configuration`
291			`ifdef DBG_EN
292			`ifdef DBG_UART
293			`ifdef DBG_JTAG
294			`CONFIGURATION ERROR: JTAG AND UART DEBUG INTERFACE ARE BOTH ENABLED`
295			`endif
296			`else
297			`ifdef DBG_JTAG
298			`CONFIGURATION ERROR: JTAG INTERFACE NOT SUPPORTED`
299			`else
300			`CONFIGURATION ERROR: JTAG OR UART DEBUG INTERFACE SHOULD BE ENABLED`
301			`endif
302			`endif
303			`endif
304
305	68	olivier.gi	`//`
306			`// MULTIPLIER CONFIGURATION`
307			`//======================================`
308
309			`// If uncommented, the following define selects`
310			`// the 16x16 multiplier (1 cycle) instead of the`
311			`// default 16x8 multplier (2 cycles)`
312			//`define MPY_16x16
313