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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [altera/] [src/] [openMSP430_undefines.v] - Blame information for rev 100

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//----------------------------------------------------------------------------
// Copyright (C) 2001 Authors
//
// This source file may be used and distributed without restriction provided
// that this copyright statement is not removed from the file and that any
// derivative work contains the original copyright notice and the associated
// disclaimer.
//
// This source file is free software; you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published
// by the Free Software Foundation; either version 2.1 of the License, or
// (at your option) any later version.
//
// This source is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
// License for more details.
//
// You should have received a copy of the GNU Lesser General Public License
// along with this source; if not, write to the Free Software Foundation,
// Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
//
//----------------------------------------------------------------------------
// 
// *File Name: openMSP430_undefines.v
// 
// *Module Description:
//                      openMSP430 Verilog `undef file
//
// *Author(s):
//              - Olivier Girard,    olgirard@gmail.com
//
//----------------------------------------------------------------------------
// $Rev: 23 $
// $LastChangedBy: olivier.girard $
// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $
//----------------------------------------------------------------------------
 
//----------------------------------------------------------------------------
// SYSTEM CONFIGURATION
//----------------------------------------------------------------------------
 
// Program Memory Size:
`ifdef PMEM_AWIDTH
`undef PMEM_AWIDTH
`endif
 
// Data Memory Size:
`ifdef DMEM_AWIDTH
`undef DMEM_AWIDTH
`endif
 
//----------------------------------------------------------------------------
// REMOTE DEBUGGING INTERFACE CONFIGURATION
//----------------------------------------------------------------------------
 
// Include Debug interface
`ifdef DBG_EN
`undef DBG_EN
`endif
 
// Debug interface selection
`ifdef DBG_UART
`undef DBG_UART
`endif
`ifdef DBG_JTAG
`undef DBG_JTAG
`endif
 
// Number of hardware breakpoints
`ifdef DBG_HWBRK_0
`undef DBG_HWBRK_0
`endif
`ifdef DBG_HWBRK_1
`undef DBG_HWBRK_1
`endif
`ifdef DBG_HWBRK_2
`undef DBG_HWBRK_2
`endif
`ifdef DBG_HWBRK_3
`undef DBG_HWBRK_3
`endif
 
 
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//=====        SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!!      =====//
//==========================================================================//
//==========================================================================//
//==========================================================================//
//==========================================================================//
 
// Program and Data Memory sizes
`ifdef PMEM_SIZE
`undef PMEM_SIZE
`endif
`ifdef DMEM_SIZE
`undef DMEM_SIZE
`endif
 
// Data Memory Base Adresses
`ifdef DMEM_BASE
`undef DMEM_BASE
`endif
 
// Program & Data Memory most significant address bit (for 16 bit words)
`ifdef PMEM_MSB
`undef PMEM_MSB
`endif
`ifdef DMEM_MSB
`undef DMEM_MSB
`endif
 
 
// Instructions type
`ifdef INST_SO
`undef INST_SO
`endif
`ifdef INST_JMP
`undef INST_JMP
`endif
`ifdef INST_TO
`undef INST_TO
`endif
 
// Single-operand arithmetic
`ifdef RRC
`undef RRC
`endif
`ifdef SWPB
`undef SWPB
`endif
`ifdef RRA
`undef RRA
`endif
`ifdef SXT
`undef SXT
`endif
`ifdef PUSH
`undef PUSH
`endif
`ifdef CALL
`undef CALL
`endif
`ifdef RETI
`undef RETI
`endif
`ifdef IRQ
`undef IRQ
`endif
 
// Conditional jump
`ifdef JNE
`undef JNE
`endif
`ifdef JEQ
`undef JEQ
`endif
`ifdef JNC
`undef JNC
`endif
`ifdef JC
`undef JC
`endif
`ifdef JN
`undef JN
`endif
`ifdef JGE
`undef JGE
`endif
`ifdef JL
`undef JL
`endif
`ifdef JMP
`undef JMP
`endif
 
// Two-operand arithmetic
`ifdef MOV
`undef MOV
`endif
`ifdef ADD
`undef ADD
`endif
`ifdef ADDC
`undef ADDC
`endif
`ifdef SUBC
`undef SUBC
`endif
`ifdef SUB
`undef SUB
`endif
`ifdef CMP
`undef CMP
`endif
`ifdef DADD
`undef DADD
`endif
`ifdef BIT
`undef BIT
`endif
`ifdef BIC
`undef BIC
`endif
`ifdef BIS
`undef BIS
`endif
`ifdef XOR
`undef XOR
`endif
`ifdef AND
`undef AND
`endif
 
// Addressing modes
`ifdef DIR
`undef DIR
`endif
`ifdef IDX
`undef IDX
`endif
`ifdef INDIR
`undef INDIR
`endif
`ifdef INDIR_I
`undef INDIR_I
`endif
`ifdef SYMB
`undef SYMB
`endif
`ifdef IMM
`undef IMM
`endif
`ifdef ABS
`undef ABS
`endif
`ifdef CONST
`undef CONST
`endif
 
// Execution state machine
`ifdef E_IRQ_0
`undef E_IRQ_0
`endif
`ifdef E_IRQ_1
`undef E_IRQ_1
`endif
`ifdef E_IRQ_2
`undef E_IRQ_2
`endif
`ifdef E_IRQ_3
`undef E_IRQ_3
`endif
`ifdef E_IRQ_4
`undef E_IRQ_4
`endif
`ifdef E_SRC_AD
`undef E_SRC_AD
`endif
`ifdef E_SRC_RD
`undef E_SRC_RD
`endif
`ifdef E_SRC_WR
`undef E_SRC_WR
`endif
`ifdef E_DST_AD
`undef E_DST_AD
`endif
`ifdef E_DST_RD
`undef E_DST_RD
`endif
`ifdef E_DST_WR
`undef E_DST_WR
`endif
`ifdef E_EXEC
`undef E_EXEC
`endif
`ifdef E_JUMP
`undef E_JUMP
`endif
`ifdef E_IDLE
`undef E_IDLE
`endif
 
// ALU control signals
`ifdef ALU_SRC_INV
`undef ALU_SRC_INV
`endif
`ifdef ALU_INC
`undef ALU_INC
`endif
`ifdef ALU_INC_C
`undef ALU_INC_C
`endif
`ifdef ALU_ADD
`undef ALU_ADD
`endif
`ifdef ALU_AND
`undef ALU_AND
`endif
`ifdef ALU_OR
`undef ALU_OR
`endif
`ifdef ALU_XOR
`undef ALU_XOR
`endif
`ifdef ALU_DADD
`undef ALU_DADD
`endif
`ifdef ALU_STAT_7
`undef ALU_STAT_7
`endif
`ifdef ALU_STAT_F
`undef ALU_STAT_F
`endif
`ifdef ALU_SHIFT
`undef ALU_SHIFT
`endif
`ifdef EXEC_NO_WR
`undef EXEC_NO_WR
`endif
 
// Debug interface
`ifdef DBG_UART_WR
`undef DBG_UART_WR
`endif
`ifdef DBG_UART_BW
`undef DBG_UART_BW
`endif
`ifdef DBG_UART_ADDR
`undef DBG_UART_ADDR
`endif
 
// Debug interface CPU_CTL register
`ifdef HALT
`undef HALT
`endif
`ifdef RUN
`undef RUN
`endif
`ifdef ISTEP
`undef ISTEP
`endif
`ifdef SW_BRK_EN
`undef SW_BRK_EN
`endif
`ifdef FRZ_BRK_EN
`undef FRZ_BRK_EN
`endif
`ifdef RST_BRK_EN
`undef RST_BRK_EN
`endif
`ifdef CPU_RST
`undef CPU_RST
`endif
 
// Debug interface CPU_STAT register
`ifdef HALT_RUN
`undef HALT_RUN
`endif
`ifdef PUC_PND
`undef PUC_PND
`endif
`ifdef SWBRK_PND
`undef SWBRK_PND
`endif
`ifdef HWBRK0_PND
`undef HWBRK0_PND
`endif
`ifdef HWBRK1_PND
`undef HWBRK1_PND
`endif
 
// Debug interface BRKx_CTL register
`ifdef BRK_MODE_RD
`undef BRK_MODE_RD
`endif
`ifdef BRK_MODE_WR
`undef BRK_MODE_WR
`endif
`ifdef BRK_MODE
`undef BRK_MODE
`endif
`ifdef BRK_EN
`undef BRK_EN
`endif
`ifdef BRK_I_EN
`undef BRK_I_EN
`endif
`ifdef BRK_RANGE
`undef BRK_RANGE
`endif
 
// Basic clock module: BCSCTL1 Control Register
`ifdef DIVAx
`undef DIVAx
`endif
 
// Basic clock module: BCSCTL2 Control Register
`ifdef SELS
`undef SELS
`endif
`ifdef DIVSx
`undef DIVSx
`endif
 
// Timer A: TACTL Control Register
`ifdef TASSELx
`undef TASSELx
`endif
`ifdef TAIDx
`undef TAIDx
`endif
`ifdef TAMCx
`undef TAMCx
`endif
`ifdef TACLR
`undef TACLR
`endif
`ifdef TAIE
`undef TAIE
`endif
`ifdef TAIFG
`undef TAIFG
`endif
 
// Timer A: TACCTLx Capture/Compare Control Register
`ifdef TACMx
`undef TACMx
`endif
`ifdef TACCISx
`undef TACCISx
`endif
`ifdef TASCS
`undef TASCS
`endif
`ifdef TASCCI
`undef TASCCI
`endif
`ifdef TACAP
`undef TACAP
`endif
`ifdef TAOUTMODx
`undef TAOUTMODx
`endif
`ifdef TACCIE
`undef TACCIE
`endif
`ifdef TACCI
`undef TACCI
`endif
`ifdef TAOUT
`undef TAOUT
`endif
`ifdef TACOV
`undef TACOV
`endif
`ifdef TACCIFG
`undef TACCIFG
`endif
 
//
// DEBUG INTERFACE EXTRA CONFIGURATION
//======================================
 
// Debug interface: Software breakpoint opcode
`ifdef DBG_SWBRK_OP
`undef DBG_SWBRK_OP
`endif
 
// Debug interface ID
`ifdef DBG_ID
`undef DBG_ID
`endif
 
// Debug UART interface auto data synchronization
`ifdef DBG_UART_AUTO_SYNC
`undef DBG_UART_AUTO_SYNC
`endif
 
// Debug UART interface data rate
`ifdef DBG_UART_BAUD
`undef DBG_UART_BAUD
`endif
`ifdef DBG_DCO_FREQ
`undef DBG_DCO_FREQ
`endif
`ifdef DBG_UART_CNT
`undef DBG_UART_CNT
`endif

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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [altera/] [src/] [openMSP430_undefines.v] - Blame information for rev 100

Line No.	Rev	Author	Line
1	63	olivier.gi	`//----------------------------------------------------------------------------`
2			`// Copyright (C) 2001 Authors`
3			`//`
4			`// This source file may be used and distributed without restriction provided`
5			`// that this copyright statement is not removed from the file and that any`
6			`// derivative work contains the original copyright notice and the associated`
7			`// disclaimer.`
8			`//`
9			`// This source file is free software; you can redistribute it and/or modify`
10			`// it under the terms of the GNU Lesser General Public License as published`
11			`// by the Free Software Foundation; either version 2.1 of the License, or`
12			`// (at your option) any later version.`
13			`//`
14			`// This source is distributed in the hope that it will be useful, but WITHOUT`
15			`// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
16			`// FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public`
17			`// License for more details.`
18			`//`
19			`// You should have received a copy of the GNU Lesser General Public License`
20			`// along with this source; if not, write to the Free Software Foundation,`
21			`// Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA`
22			`//`
23			`//----------------------------------------------------------------------------`
24			`//`
25			`// *File Name: openMSP430_undefines.v`
26			`//`
27			`// *Module Description:`
28			// openMSP430 Verilog `undef file
29			`//`
30			`// *Author(s):`
31			`// - Olivier Girard, olgirard@gmail.com`
32			`//`
33			`//----------------------------------------------------------------------------`
34			`// $Rev: 23 $`
35			`// $LastChangedBy: olivier.girard $`
36			`// $LastChangedDate: 2009-08-30 18:39:26 +0200 (Sun, 30 Aug 2009) $`
37			`//----------------------------------------------------------------------------`
38
39			`//----------------------------------------------------------------------------`
40			`// SYSTEM CONFIGURATION`
41			`//----------------------------------------------------------------------------`
42
43			`// Program Memory Size:`
44			`ifdef PMEM_AWIDTH
45			`undef PMEM_AWIDTH
46			`endif
47
48			`// Data Memory Size:`
49			`ifdef DMEM_AWIDTH
50			`undef DMEM_AWIDTH
51			`endif
52
53			`//----------------------------------------------------------------------------`
54			`// REMOTE DEBUGGING INTERFACE CONFIGURATION`
55			`//----------------------------------------------------------------------------`
56
57			`// Include Debug interface`
58			`ifdef DBG_EN
59			`undef DBG_EN
60			`endif
61
62			`// Debug interface selection`
63			`ifdef DBG_UART
64			`undef DBG_UART
65			`endif
66			`ifdef DBG_JTAG
67			`undef DBG_JTAG
68			`endif
69
70			`// Number of hardware breakpoints`
71			`ifdef DBG_HWBRK_0
72			`undef DBG_HWBRK_0
73			`endif
74			`ifdef DBG_HWBRK_1
75			`undef DBG_HWBRK_1
76			`endif
77			`ifdef DBG_HWBRK_2
78			`undef DBG_HWBRK_2
79			`endif
80			`ifdef DBG_HWBRK_3
81			`undef DBG_HWBRK_3
82			`endif
83
84
85			`//==========================================================================//`
86			`//==========================================================================//`
87			`//==========================================================================//`
88			`//==========================================================================//`
89			`//===== SYSTEM CONSTANTS --- !!!!!!!! DO NOT EDIT !!!!!!!! =====//`
90			`//==========================================================================//`
91			`//==========================================================================//`
92			`//==========================================================================//`
93			`//==========================================================================//`
94
95			`// Program and Data Memory sizes`
96			`ifdef PMEM_SIZE
97			`undef PMEM_SIZE
98			`endif
99			`ifdef DMEM_SIZE
100			`undef DMEM_SIZE
101			`endif
102
103			`// Data Memory Base Adresses`
104			`ifdef DMEM_BASE
105			`undef DMEM_BASE
106			`endif
107
108			`// Program & Data Memory most significant address bit (for 16 bit words)`
109			`ifdef PMEM_MSB
110			`undef PMEM_MSB
111			`endif
112			`ifdef DMEM_MSB
113			`undef DMEM_MSB
114			`endif
115
116
117			`// Instructions type`
118			`ifdef INST_SO
119			`undef INST_SO
120			`endif
121			`ifdef INST_JMP
122			`undef INST_JMP
123			`endif
124			`ifdef INST_TO
125			`undef INST_TO
126			`endif
127
128			`// Single-operand arithmetic`
129			`ifdef RRC
130			`undef RRC
131			`endif
132			`ifdef SWPB
133			`undef SWPB
134			`endif
135			`ifdef RRA
136			`undef RRA
137			`endif
138			`ifdef SXT
139			`undef SXT
140			`endif
141			`ifdef PUSH
142			`undef PUSH
143			`endif
144			`ifdef CALL
145			`undef CALL
146			`endif
147			`ifdef RETI
148			`undef RETI
149			`endif
150			`ifdef IRQ
151			`undef IRQ
152			`endif
153
154			`// Conditional jump`
155			`ifdef JNE
156			`undef JNE
157			`endif
158			`ifdef JEQ
159			`undef JEQ
160			`endif
161			`ifdef JNC
162			`undef JNC
163			`endif
164			`ifdef JC
165			`undef JC
166			`endif
167			`ifdef JN
168			`undef JN
169			`endif
170			`ifdef JGE
171			`undef JGE
172			`endif
173			`ifdef JL
174			`undef JL
175			`endif
176			`ifdef JMP
177			`undef JMP
178			`endif
179
180			`// Two-operand arithmetic`
181			`ifdef MOV
182			`undef MOV
183			`endif
184			`ifdef ADD
185			`undef ADD
186			`endif
187			`ifdef ADDC
188			`undef ADDC
189			`endif
190			`ifdef SUBC
191			`undef SUBC
192			`endif
193			`ifdef SUB
194			`undef SUB
195			`endif
196			`ifdef CMP
197			`undef CMP
198			`endif
199			`ifdef DADD
200			`undef DADD
201			`endif
202			`ifdef BIT
203			`undef BIT
204			`endif
205			`ifdef BIC
206			`undef BIC
207			`endif
208			`ifdef BIS
209			`undef BIS
210			`endif
211			`ifdef XOR
212			`undef XOR
213			`endif
214			`ifdef AND
215			`undef AND
216			`endif
217
218			`// Addressing modes`
219			`ifdef DIR
220			`undef DIR
221			`endif
222			`ifdef IDX
223			`undef IDX
224			`endif
225			`ifdef INDIR
226			`undef INDIR
227			`endif
228			`ifdef INDIR_I
229			`undef INDIR_I
230			`endif
231			`ifdef SYMB
232			`undef SYMB
233			`endif
234			`ifdef IMM
235			`undef IMM
236			`endif
237			`ifdef ABS
238			`undef ABS
239			`endif
240			`ifdef CONST
241			`undef CONST
242			`endif
243
244			`// Execution state machine`
245			`ifdef E_IRQ_0
246			`undef E_IRQ_0
247			`endif
248			`ifdef E_IRQ_1
249			`undef E_IRQ_1
250			`endif
251			`ifdef E_IRQ_2
252			`undef E_IRQ_2
253			`endif
254			`ifdef E_IRQ_3
255			`undef E_IRQ_3
256			`endif
257			`ifdef E_IRQ_4
258			`undef E_IRQ_4
259			`endif
260			`ifdef E_SRC_AD
261			`undef E_SRC_AD
262			`endif
263			`ifdef E_SRC_RD
264			`undef E_SRC_RD
265			`endif
266			`ifdef E_SRC_WR
267			`undef E_SRC_WR
268			`endif
269			`ifdef E_DST_AD
270			`undef E_DST_AD
271			`endif
272			`ifdef E_DST_RD
273			`undef E_DST_RD
274			`endif
275			`ifdef E_DST_WR
276			`undef E_DST_WR
277			`endif
278			`ifdef E_EXEC
279			`undef E_EXEC
280			`endif
281			`ifdef E_JUMP
282			`undef E_JUMP
283			`endif
284			`ifdef E_IDLE
285			`undef E_IDLE
286			`endif
287
288			`// ALU control signals`
289			`ifdef ALU_SRC_INV
290			`undef ALU_SRC_INV
291			`endif
292			`ifdef ALU_INC
293			`undef ALU_INC
294			`endif
295			`ifdef ALU_INC_C
296			`undef ALU_INC_C
297			`endif
298			`ifdef ALU_ADD
299			`undef ALU_ADD
300			`endif
301			`ifdef ALU_AND
302			`undef ALU_AND
303			`endif
304			`ifdef ALU_OR
305			`undef ALU_OR
306			`endif
307			`ifdef ALU_XOR
308			`undef ALU_XOR
309			`endif
310			`ifdef ALU_DADD
311			`undef ALU_DADD
312			`endif
313			`ifdef ALU_STAT_7
314			`undef ALU_STAT_7
315			`endif
316			`ifdef ALU_STAT_F
317			`undef ALU_STAT_F
318			`endif
319			`ifdef ALU_SHIFT
320			`undef ALU_SHIFT
321			`endif
322			`ifdef EXEC_NO_WR
323			`undef EXEC_NO_WR
324			`endif
325
326			`// Debug interface`
327			`ifdef DBG_UART_WR
328			`undef DBG_UART_WR
329			`endif
330			`ifdef DBG_UART_BW
331			`undef DBG_UART_BW
332			`endif
333			`ifdef DBG_UART_ADDR
334			`undef DBG_UART_ADDR
335			`endif
336
337			`// Debug interface CPU_CTL register`
338			`ifdef HALT
339			`undef HALT
340			`endif
341			`ifdef RUN
342			`undef RUN
343			`endif
344			`ifdef ISTEP
345			`undef ISTEP
346			`endif
347			`ifdef SW_BRK_EN
348			`undef SW_BRK_EN
349			`endif
350			`ifdef FRZ_BRK_EN
351			`undef FRZ_BRK_EN
352			`endif
353			`ifdef RST_BRK_EN
354			`undef RST_BRK_EN
355			`endif
356			`ifdef CPU_RST
357			`undef CPU_RST
358			`endif
359
360			`// Debug interface CPU_STAT register`
361			`ifdef HALT_RUN
362			`undef HALT_RUN
363			`endif
364			`ifdef PUC_PND
365			`undef PUC_PND
366			`endif
367			`ifdef SWBRK_PND
368			`undef SWBRK_PND
369			`endif
370			`ifdef HWBRK0_PND
371			`undef HWBRK0_PND
372			`endif
373			`ifdef HWBRK1_PND
374			`undef HWBRK1_PND
375			`endif
376
377			`// Debug interface BRKx_CTL register`
378			`ifdef BRK_MODE_RD
379			`undef BRK_MODE_RD
380			`endif
381			`ifdef BRK_MODE_WR
382			`undef BRK_MODE_WR
383			`endif
384			`ifdef BRK_MODE
385			`undef BRK_MODE
386			`endif
387			`ifdef BRK_EN
388			`undef BRK_EN
389			`endif
390			`ifdef BRK_I_EN
391			`undef BRK_I_EN
392			`endif
393			`ifdef BRK_RANGE
394			`undef BRK_RANGE
395			`endif
396
397			`// Basic clock module: BCSCTL1 Control Register`
398			`ifdef DIVAx
399			`undef DIVAx
400			`endif
401
402			`// Basic clock module: BCSCTL2 Control Register`
403			`ifdef SELS
404			`undef SELS
405			`endif
406			`ifdef DIVSx
407			`undef DIVSx
408			`endif
409
410			`// Timer A: TACTL Control Register`
411			`ifdef TASSELx
412			`undef TASSELx
413			`endif
414			`ifdef TAIDx
415			`undef TAIDx
416			`endif
417			`ifdef TAMCx
418			`undef TAMCx
419			`endif
420			`ifdef TACLR
421			`undef TACLR
422			`endif
423			`ifdef TAIE
424			`undef TAIE
425			`endif
426			`ifdef TAIFG
427			`undef TAIFG
428			`endif
429
430			`// Timer A: TACCTLx Capture/Compare Control Register`
431			`ifdef TACMx
432			`undef TACMx
433			`endif
434			`ifdef TACCISx
435			`undef TACCISx
436			`endif
437			`ifdef TASCS
438			`undef TASCS
439			`endif
440			`ifdef TASCCI
441			`undef TASCCI
442			`endif
443			`ifdef TACAP
444			`undef TACAP
445			`endif
446			`ifdef TAOUTMODx
447			`undef TAOUTMODx
448			`endif
449			`ifdef TACCIE
450			`undef TACCIE
451			`endif
452			`ifdef TACCI
453			`undef TACCI
454			`endif
455			`ifdef TAOUT
456			`undef TAOUT
457			`endif
458			`ifdef TACOV
459			`undef TACOV
460			`endif
461			`ifdef TACCIFG
462			`undef TACCIFG
463			`endif
464
465			`//`
466			`// DEBUG INTERFACE EXTRA CONFIGURATION`
467			`//======================================`
468
469			`// Debug interface: Software breakpoint opcode`
470			`ifdef DBG_SWBRK_OP
471			`undef DBG_SWBRK_OP
472			`endif
473
474			`// Debug interface ID`
475			`ifdef DBG_ID
476			`undef DBG_ID
477			`endif
478
479			`// Debug UART interface auto data synchronization`
480			`ifdef DBG_UART_AUTO_SYNC
481			`undef DBG_UART_AUTO_SYNC
482			`endif
483
484			`// Debug UART interface data rate`
485			`ifdef DBG_UART_BAUD
486			`undef DBG_UART_BAUD
487			`endif
488			`ifdef DBG_DCO_FREQ
489			`undef DBG_DCO_FREQ
490			`endif
491			`ifdef DBG_UART_CNT
492			`undef DBG_UART_CNT
493			`endif