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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [constraints.tcl] - Blame information for rev 147

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##############################################################################
#                                                                            #
#                            CLOCK DEFINITION                                #
#                                                                            #
##############################################################################
 
#set CLOCK_PERIOD 100.0; #  10 MHz
#set CLOCK_PERIOD 66.6; #  15 MHz
#set CLOCK_PERIOD 50.0; #  20 MHz
set CLOCK_PERIOD 40.0; #  25 MHz
#set CLOCK_PERIOD 33.3; #  30 MHz
#set CLOCK_PERIOD 30.0; #  33 MHz
#set CLOCK_PERIOD 25.0; #  40 MHz
#set CLOCK_PERIOD 22.2; #  45 MHz
#set CLOCK_PERIOD 20.0; #  50 MHz
#set CLOCK_PERIOD 16.7; #  60 MHz
#set CLOCK_PERIOD 15.4; #  65 MHz
#set CLOCK_PERIOD 15.0; #  66 MHz
#set CLOCK_PERIOD 14.3; #  70 MHz
#set CLOCK_PERIOD 12.5; #  80 MHz
#set CLOCK_PERIOD 11.1; #  90 MHz
#set CLOCK_PERIOD 10.0; # 100 MHz
#set CLOCK_PERIOD  8.0; # 125 MHz
 
 
create_clock -name     "dco_clk"                              \
             -period   "$CLOCK_PERIOD"                        \
             -waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
             [get_ports dco_clk]
 
create_clock -name     "lfxt_clk"                             \
             -period   "$CLOCK_PERIOD"                        \
             -waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
             [get_ports lfxt_clk]
 
 
##############################################################################
#                                                                            #
#                          CREATE PATH GROUPS                                #
#                                                                            #
##############################################################################
 
group_path -name REGOUT      -to   [all_outputs]
group_path -name REGIN       -from [remove_from_collection [all_inputs] [get_ports dco_clk]]
group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports dco_clk]] -to [all_outputs]
 
 
##############################################################################
#                                                                            #
#                          BOUNDARY TIMINGS                                  #
#                                                                            #
##############################################################################
# NOTE: There are some path through between Program/Data memory signals
#      which are limiting the maximum frequency achievable by the core.
#       The memory constraints set on these interfaces are therefore quite
#      critical regarding the achievable performance of the core.
#       As a consequence, the constrains on the pmem_*/dmem_* signals must
#      be set with some absolute values as they are specified by the targeted
#      process RAM/ROM generator.
 
#================#
# PROGRAM MEMORY #
#================#
 
set PMEM_DOUT_DLY    2.25
 
set PMEM_ADDR_DLY    0.64
set PMEM_CEN_DLY     0.63
set PMEM_DIN_DLY     0.39
set PMEM_WEN_DLY     0.44
 
set_input_delay  $PMEM_DOUT_DLY            -max -clock "dco_clk"  [get_ports pmem_dout]
set_input_delay  0                         -min -clock "dco_clk"  [get_ports pmem_dout]
 
set_output_delay $PMEM_ADDR_DLY -add_delay -max -clock "dco_clk"  [get_ports pmem_addr]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_addr]
 
set_output_delay $PMEM_CEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports pmem_cen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_cen]
 
set_output_delay $PMEM_DIN_DLY  -add_delay -max -clock "dco_clk"  [get_ports pmem_din]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_din]
 
set_output_delay $PMEM_WEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports pmem_wen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_wen]
 
 
#================#
# DATA MEMORY    #
#================#
 
set DMEM_DOUT_DLY    2.25
 
set DMEM_ADDR_DLY    0.64
set DMEM_CEN_DLY     0.63
set DMEM_DIN_DLY     0.39
set DMEM_WEN_DLY     0.44
 
 
set_input_delay $DMEM_DOUT_DLY             -max -clock "dco_clk"  [get_ports dmem_dout]
set_input_delay 0                          -min -clock "dco_clk"  [get_ports dmem_dout]
 
set_output_delay $DMEM_ADDR_DLY -add_delay -max -clock "dco_clk"  [get_ports dmem_addr]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_addr]
 
set_output_delay $DMEM_CEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports dmem_cen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_cen]
 
set_output_delay $DMEM_DIN_DLY  -add_delay -max -clock "dco_clk"  [get_ports dmem_din]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_din]
 
set_output_delay $DMEM_WEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports dmem_wen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_wen]
 
 
#==========================#
# REMAINING INPUT PORTS    #
#==========================#
 
set IRQ_DLY          [expr ($CLOCK_PERIOD/100) * 30]
set PER_DOUT_DLY     [expr ($CLOCK_PERIOD/100) * 20]
 
 
set_input_delay $IRQ_DLY       -max -clock "dco_clk"  [get_ports irq]
set_input_delay 0              -min -clock "dco_clk"  [get_ports irq]
 
set_input_delay $PER_DOUT_DLY  -max -clock "dco_clk"  [get_ports per_dout]
set_input_delay 0              -min -clock "dco_clk"  [get_ports per_dout]
 
 
#=========================#
# REMAINING OUTPUT PORTS  #
#=========================#
 
set ACLK_EN_DLY      [expr ($CLOCK_PERIOD/100) * 85]
set SMCLK_EN_DLY     [expr ($CLOCK_PERIOD/100) * 85]
set DBG_FREEZE_DLY   [expr ($CLOCK_PERIOD/100) * 85]
set IRQ_ACC_DLY      [expr ($CLOCK_PERIOD/100) * 60]
 
set PER_ADDR_DLY     [expr ($CLOCK_PERIOD/100) * 25]
set PER_DIN_DLY      [expr ($CLOCK_PERIOD/100) * 25]
set PER_WEN_DLY      [expr ($CLOCK_PERIOD/100) * 25]
set PER_EN_DLY       [expr ($CLOCK_PERIOD/100) * 25]
 
set PUC_DLY          [expr ($CLOCK_PERIOD/100) * 75]
 
 
set_output_delay $ACLK_EN_DLY    -add_delay -max -clock "dco_clk"             [get_ports aclk_en]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports aclk_en]
 
set_output_delay $SMCLK_EN_DLY   -add_delay -max -clock "dco_clk"             [get_ports smclk_en]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports smclk_en]
 
set_output_delay $DBG_FREEZE_DLY -add_delay -max -clock "dco_clk"             [get_ports dbg_freeze]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports dbg_freeze]
 
set_output_delay $IRQ_ACC_DLY    -add_delay -max -clock "dco_clk"             [get_ports irq_acc]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports irq_acc]
 
 
set_output_delay $PER_ADDR_DLY   -add_delay -max -clock "dco_clk"             [get_ports per_addr]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_addr]
 
set_output_delay $PER_DIN_DLY    -add_delay -max -clock "dco_clk"             [get_ports per_din]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_din]
 
set_output_delay $PER_WEN_DLY    -add_delay -max -clock "dco_clk"             [get_ports per_we]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_we]
 
set_output_delay $PER_EN_DLY     -add_delay -max -clock "dco_clk"             [get_ports per_en]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_en]
 
set_output_delay $PUC_DLY        -add_delay -max -clock "dco_clk"             [get_ports puc_rst]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports puc_rst]
 
 
#========================#
# FEEDTHROUGH EXCEPTIONS #
#========================#
 
#set_max_delay [expr 2.0 + $DMEM_DOUT_DLY + $DMEM_ADDR_DLY] \
#              -from       [get_ports dmem_dout]            \
#              -to         [get_ports dmem_addr]            \
#              -group_path FEEDTHROUGH
 
 
#===============#
# FALSE PATHS   #
#===============#
# The following signals are internaly synchronized to
# the dco_clk domain and can be set as false path.
 
set_false_path -from dbg_uart_rxd
set_false_path -to   dbg_uart_txd
 
set_false_path -from nmi
set_false_path -from lfxt_clk
set_false_path -from reset_n
 
set_false_path -from cpu_en
set_false_path -from dbg_en

Line No.	Rev	Author	Line
1	2	olivier.gi	`##############################################################################`
2			`# #`
3			`# CLOCK DEFINITION #`
4			`# #`
5			`##############################################################################`
6
7	134	olivier.gi	`#set CLOCK_PERIOD 100.0; # 10 MHz`
8			`#set CLOCK_PERIOD 66.6; # 15 MHz`
9			`#set CLOCK_PERIOD 50.0; # 20 MHz`
10			`set CLOCK_PERIOD 40.0; # 25 MHz`
11			`#set CLOCK_PERIOD 33.3; # 30 MHz`
12	2	olivier.gi	`#set CLOCK_PERIOD 30.0; # 33 MHz`
13	134	olivier.gi	`#set CLOCK_PERIOD 25.0; # 40 MHz`
14			`#set CLOCK_PERIOD 22.2; # 45 MHz`
15			`#set CLOCK_PERIOD 20.0; # 50 MHz`
16			`#set CLOCK_PERIOD 16.7; # 60 MHz`
17			`#set CLOCK_PERIOD 15.4; # 65 MHz`
18	2	olivier.gi	`#set CLOCK_PERIOD 15.0; # 66 MHz`
19	134	olivier.gi	`#set CLOCK_PERIOD 14.3; # 70 MHz`
20			`#set CLOCK_PERIOD 12.5; # 80 MHz`
21			`#set CLOCK_PERIOD 11.1; # 90 MHz`
22	2	olivier.gi	`#set CLOCK_PERIOD 10.0; # 100 MHz`
23			`#set CLOCK_PERIOD 8.0; # 125 MHz`
24
25
26	56	olivier.gi	`create_clock -name "dco_clk" \`
27	2	olivier.gi	`-period "$CLOCK_PERIOD" \`
28			`-waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \`
29	56	olivier.gi	`[get_ports dco_clk]`
30	2	olivier.gi
31	134	olivier.gi	`create_clock -name "lfxt_clk" \`
32			`-period "$CLOCK_PERIOD" \`
33			`-waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \`
34			`[get_ports lfxt_clk]`
35	2	olivier.gi
36	134	olivier.gi
37	2	olivier.gi	`##############################################################################`
38			`# #`
39			`# CREATE PATH GROUPS #`
40			`# #`
41			`##############################################################################`
42
43			`group_path -name REGOUT -to [all_outputs]`
44	56	olivier.gi	`group_path -name REGIN -from [remove_from_collection [all_inputs] [get_ports dco_clk]]`
45			`group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports dco_clk]] -to [all_outputs]`
46	2	olivier.gi
47
48			`##############################################################################`
49			`# #`
50			`# BOUNDARY TIMINGS #`
51			`# #`
52			`##############################################################################`
53	56	olivier.gi	`# NOTE: There are some path through between Program/Data memory signals`
54			`# which are limiting the maximum frequency achievable by the core.`
55			`# The memory constraints set on these interfaces are therefore quite`
56			`# critical regarding the achievable performance of the core.`
57			`# As a consequence, the constrains on the pmem_/dmem_ signals must`
58			`# be set with some absolute values as they are specified by the targeted`
59			`# process RAM/ROM generator.`
60	2	olivier.gi
61	56	olivier.gi	`#================#`
62			`# PROGRAM MEMORY #`
63			`#================#`
64	2	olivier.gi
65	56	olivier.gi	`set PMEM_DOUT_DLY 2.25`
66	2	olivier.gi
67	56	olivier.gi	`set PMEM_ADDR_DLY 0.64`
68			`set PMEM_CEN_DLY 0.63`
69			`set PMEM_DIN_DLY 0.39`
70			`set PMEM_WEN_DLY 0.44`
71	2	olivier.gi
72	56	olivier.gi	`set_input_delay $PMEM_DOUT_DLY -max -clock "dco_clk" [get_ports pmem_dout]`
73			`set_input_delay 0 -min -clock "dco_clk" [get_ports pmem_dout]`
74	2	olivier.gi
75	56	olivier.gi	`set_output_delay $PMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_addr]`
76			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_addr]`
77	2	olivier.gi
78	56	olivier.gi	`set_output_delay $PMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_cen]`
79			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_cen]`
80	2	olivier.gi
81	56	olivier.gi	`set_output_delay $PMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_din]`
82			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_din]`
83	2	olivier.gi
84	56	olivier.gi	`set_output_delay $PMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_wen]`
85			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_wen]`
86	2	olivier.gi
87
88	56	olivier.gi	`#================#`
89			`# DATA MEMORY #`
90			`#================#`
91	2	olivier.gi
92	56	olivier.gi	`set DMEM_DOUT_DLY 2.25`
93	2	olivier.gi
94	56	olivier.gi	`set DMEM_ADDR_DLY 0.64`
95			`set DMEM_CEN_DLY 0.63`
96			`set DMEM_DIN_DLY 0.39`
97			`set DMEM_WEN_DLY 0.44`
98	2	olivier.gi
99
100	56	olivier.gi	`set_input_delay $DMEM_DOUT_DLY -max -clock "dco_clk" [get_ports dmem_dout]`
101			`set_input_delay 0 -min -clock "dco_clk" [get_ports dmem_dout]`
102	2	olivier.gi
103	56	olivier.gi	`set_output_delay $DMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_addr]`
104			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_addr]`
105	2	olivier.gi
106	56	olivier.gi	`set_output_delay $DMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_cen]`
107			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_cen]`
108	2	olivier.gi
109	56	olivier.gi	`set_output_delay $DMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_din]`
110			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_din]`
111	2	olivier.gi
112	56	olivier.gi	`set_output_delay $DMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_wen]`
113			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_wen]`
114	2	olivier.gi
115
116	56	olivier.gi	`#==========================#`
117			`# REMAINING INPUT PORTS #`
118			`#==========================#`
119	2	olivier.gi
120	56	olivier.gi	`set IRQ_DLY [expr ($CLOCK_PERIOD/100) * 30]`
121			`set PER_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]`
122	2	olivier.gi
123
124	56	olivier.gi	`set_input_delay $IRQ_DLY -max -clock "dco_clk" [get_ports irq]`
125			`set_input_delay 0 -min -clock "dco_clk" [get_ports irq]`
126	2	olivier.gi
127	56	olivier.gi	`set_input_delay $PER_DOUT_DLY -max -clock "dco_clk" [get_ports per_dout]`
128			`set_input_delay 0 -min -clock "dco_clk" [get_ports per_dout]`
129	2	olivier.gi
130
131	56	olivier.gi	`#=========================#`
132			`# REMAINING OUTPUT PORTS #`
133			`#=========================#`
134	2	olivier.gi
135	56	olivier.gi	`set ACLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]`
136			`set SMCLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]`
137			`set DBG_FREEZE_DLY [expr ($CLOCK_PERIOD/100) * 85]`
138			`set IRQ_ACC_DLY [expr ($CLOCK_PERIOD/100) * 60]`
139	2	olivier.gi
140	56	olivier.gi	`set PER_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 25]`
141			`set PER_DIN_DLY [expr ($CLOCK_PERIOD/100) * 25]`
142			`set PER_WEN_DLY [expr ($CLOCK_PERIOD/100) * 25]`
143			`set PER_EN_DLY [expr ($CLOCK_PERIOD/100) * 25]`
144	2	olivier.gi
145	56	olivier.gi	`set PUC_DLY [expr ($CLOCK_PERIOD/100) * 75]`
146	2	olivier.gi
147
148	56	olivier.gi	`set_output_delay $ACLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports aclk_en]`
149			`set_output_delay 0 -min -clock "dco_clk" [get_ports aclk_en]`
150	2	olivier.gi
151	56	olivier.gi	`set_output_delay $SMCLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports smclk_en]`
152			`set_output_delay 0 -min -clock "dco_clk" [get_ports smclk_en]`
153
154			`set_output_delay $DBG_FREEZE_DLY -add_delay -max -clock "dco_clk" [get_ports dbg_freeze]`
155			`set_output_delay 0 -min -clock "dco_clk" [get_ports dbg_freeze]`
156
157			`set_output_delay $IRQ_ACC_DLY -add_delay -max -clock "dco_clk" [get_ports irq_acc]`
158			`set_output_delay 0 -min -clock "dco_clk" [get_ports irq_acc]`
159
160
161			`set_output_delay $PER_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports per_addr]`
162			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_addr]`
163
164			`set_output_delay $PER_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports per_din]`
165			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_din]`
166
167	111	olivier.gi	`set_output_delay $PER_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports per_we]`
168			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_we]`
169	56	olivier.gi
170			`set_output_delay $PER_EN_DLY -add_delay -max -clock "dco_clk" [get_ports per_en]`
171			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_en]`
172
173	111	olivier.gi	`set_output_delay $PUC_DLY -add_delay -max -clock "dco_clk" [get_ports puc_rst]`
174			`set_output_delay 0 -min -clock "dco_clk" [get_ports puc_rst]`
175	56	olivier.gi
176
177	2	olivier.gi	`#========================#`
178			`# FEEDTHROUGH EXCEPTIONS #`
179			`#========================#`
180
181	56	olivier.gi	`#set_max_delay [expr 2.0 + $DMEM_DOUT_DLY + $DMEM_ADDR_DLY] \`
182			`# -from [get_ports dmem_dout] \`
183			`# -to [get_ports dmem_addr] \`
184	2	olivier.gi	`# -group_path FEEDTHROUGH`
185
186	56	olivier.gi
187			`#===============#`
188			`# FALSE PATHS #`
189			`#===============#`
190			`# The following signals are internaly synchronized to`
191			`# the dco_clk domain and can be set as false path.`
192
193			`set_false_path -from dbg_uart_rxd`
194			`set_false_path -to dbg_uart_txd`
195
196			`set_false_path -from nmi`
197			`set_false_path -from lfxt_clk`
198			`set_false_path -from reset_n`
199	111	olivier.gi
200			`set_false_path -from cpu_en`
201			`set_false_path -from dbg_en`

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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [constraints.tcl] - Blame information for rev 147