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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [constraints.tcl] - Blame information for rev 60

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##############################################################################
#                                                                            #
#                            CLOCK DEFINITION                                #
#                                                                            #
##############################################################################
 
#set CLOCK_PERIOD 40.0; #  25 MHz
#set CLOCK_PERIOD 30.0; #  33 MHz
set CLOCK_PERIOD 20.0; #  50 MHz
#set CLOCK_PERIOD 15.0; #  66 MHz
#set CLOCK_PERIOD 10.0; # 100 MHz
#set CLOCK_PERIOD  8.0; # 125 MHz
 
 
create_clock -name     "dco_clk"                              \
             -period   "$CLOCK_PERIOD"                        \
             -waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \
             [get_ports dco_clk]
 
 
##############################################################################
#                                                                            #
#                          CREATE PATH GROUPS                                #
#                                                                            #
##############################################################################
 
group_path -name REGOUT      -to   [all_outputs]
group_path -name REGIN       -from [remove_from_collection [all_inputs] [get_ports dco_clk]]
group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports dco_clk]] -to [all_outputs]
 
 
##############################################################################
#                                                                            #
#                          BOUNDARY TIMINGS                                  #
#                                                                            #
##############################################################################
# NOTE: There are some path through between Program/Data memory signals
#      which are limiting the maximum frequency achievable by the core.
#       The memory constraints set on these interfaces are therefore quite
#      critical regarding the achievable performance of the core.
#       As a consequence, the constrains on the pmem_*/dmem_* signals must
#      be set with some absolute values as they are specified by the targeted
#      process RAM/ROM generator.
 
#================#
# PROGRAM MEMORY #
#================#
 
set PMEM_DOUT_DLY    2.25
 
set PMEM_ADDR_DLY    0.64
set PMEM_CEN_DLY     0.63
set PMEM_DIN_DLY     0.39
set PMEM_WEN_DLY     0.44
 
set_input_delay  $PMEM_DOUT_DLY            -max -clock "dco_clk"  [get_ports pmem_dout]
set_input_delay  0                         -min -clock "dco_clk"  [get_ports pmem_dout]
 
set_output_delay $PMEM_ADDR_DLY -add_delay -max -clock "dco_clk"  [get_ports pmem_addr]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_addr]
 
set_output_delay $PMEM_CEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports pmem_cen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_cen]
 
set_output_delay $PMEM_DIN_DLY  -add_delay -max -clock "dco_clk"  [get_ports pmem_din]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_din]
 
set_output_delay $PMEM_WEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports pmem_wen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports pmem_wen]
 
 
#================#
# DATA MEMORY    #
#================#
 
set DMEM_DOUT_DLY    2.25
 
set DMEM_ADDR_DLY    0.64
set DMEM_CEN_DLY     0.63
set DMEM_DIN_DLY     0.39
set DMEM_WEN_DLY     0.44
 
 
set_input_delay $DMEM_DOUT_DLY             -max -clock "dco_clk"  [get_ports dmem_dout]
set_input_delay 0                          -min -clock "dco_clk"  [get_ports dmem_dout]
 
set_output_delay $DMEM_ADDR_DLY -add_delay -max -clock "dco_clk"  [get_ports dmem_addr]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_addr]
 
set_output_delay $DMEM_CEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports dmem_cen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_cen]
 
set_output_delay $DMEM_DIN_DLY  -add_delay -max -clock "dco_clk"  [get_ports dmem_din]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_din]
 
set_output_delay $DMEM_WEN_DLY  -add_delay -max -clock "dco_clk"  [get_ports dmem_wen]
set_output_delay 0                         -min -clock "dco_clk"  [get_ports dmem_wen]
 
 
#==========================#
# REMAINING INPUT PORTS    #
#==========================#
 
set IRQ_DLY          [expr ($CLOCK_PERIOD/100) * 30]
set PER_DOUT_DLY     [expr ($CLOCK_PERIOD/100) * 20]
 
 
set_input_delay $IRQ_DLY       -max -clock "dco_clk"  [get_ports irq]
set_input_delay 0              -min -clock "dco_clk"  [get_ports irq]
 
set_input_delay $PER_DOUT_DLY  -max -clock "dco_clk"  [get_ports per_dout]
set_input_delay 0              -min -clock "dco_clk"  [get_ports per_dout]
 
 
#=========================#
# REMAINING OUTPUT PORTS  #
#=========================#
 
set ACLK_EN_DLY      [expr ($CLOCK_PERIOD/100) * 85]
set SMCLK_EN_DLY     [expr ($CLOCK_PERIOD/100) * 85]
set DBG_FREEZE_DLY   [expr ($CLOCK_PERIOD/100) * 85]
set IRQ_ACC_DLY      [expr ($CLOCK_PERIOD/100) * 60]
 
set PER_ADDR_DLY     [expr ($CLOCK_PERIOD/100) * 25]
set PER_DIN_DLY      [expr ($CLOCK_PERIOD/100) * 25]
set PER_WEN_DLY      [expr ($CLOCK_PERIOD/100) * 25]
set PER_EN_DLY       [expr ($CLOCK_PERIOD/100) * 25]
 
set PUC_DLY          [expr ($CLOCK_PERIOD/100) * 75]
 
 
set_output_delay $ACLK_EN_DLY    -add_delay -max -clock "dco_clk"             [get_ports aclk_en]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports aclk_en]
 
set_output_delay $SMCLK_EN_DLY   -add_delay -max -clock "dco_clk"             [get_ports smclk_en]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports smclk_en]
 
set_output_delay $DBG_FREEZE_DLY -add_delay -max -clock "dco_clk"             [get_ports dbg_freeze]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports dbg_freeze]
 
set_output_delay $IRQ_ACC_DLY    -add_delay -max -clock "dco_clk"             [get_ports irq_acc]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports irq_acc]
 
 
set_output_delay $PER_ADDR_DLY   -add_delay -max -clock "dco_clk"             [get_ports per_addr]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_addr]
 
set_output_delay $PER_DIN_DLY    -add_delay -max -clock "dco_clk"             [get_ports per_din]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_din]
 
set_output_delay $PER_WEN_DLY    -add_delay -max -clock "dco_clk"             [get_ports per_wen]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_wen]
 
set_output_delay $PER_EN_DLY     -add_delay -max -clock "dco_clk"             [get_ports per_en]
set_output_delay 0                          -min -clock "dco_clk"             [get_ports per_en]
 
set_output_delay $PUC_DLY        -add_delay -max -clock "dco_clk" -clock_fall [get_ports puc]
set_output_delay 0                          -min -clock "dco_clk" -clock_fall [get_ports puc]
 
 
#========================#
# FEEDTHROUGH EXCEPTIONS #
#========================#
 
#set_max_delay [expr 2.0 + $DMEM_DOUT_DLY + $DMEM_ADDR_DLY] \
#              -from       [get_ports dmem_dout]            \
#              -to         [get_ports dmem_addr]            \
#              -group_path FEEDTHROUGH
 
 
#===============#
# FALSE PATHS   #
#===============#
# The following signals are internaly synchronized to
# the dco_clk domain and can be set as false path.
 
set_false_path -from dbg_uart_rxd
set_false_path -to   dbg_uart_txd
 
set_false_path -from nmi
set_false_path -from lfxt_clk
set_false_path -from reset_n

Line No.	Rev	Author	Line
1	2	olivier.gi	`##############################################################################`
2			`# #`
3			`# CLOCK DEFINITION #`
4			`# #`
5			`##############################################################################`
6
7			`#set CLOCK_PERIOD 40.0; # 25 MHz`
8			`#set CLOCK_PERIOD 30.0; # 33 MHz`
9			`set CLOCK_PERIOD 20.0; # 50 MHz`
10			`#set CLOCK_PERIOD 15.0; # 66 MHz`
11			`#set CLOCK_PERIOD 10.0; # 100 MHz`
12			`#set CLOCK_PERIOD 8.0; # 125 MHz`
13
14
15	56	olivier.gi	`create_clock -name "dco_clk" \`
16	2	olivier.gi	`-period "$CLOCK_PERIOD" \`
17			`-waveform "[expr $CLOCK_PERIOD/2] $CLOCK_PERIOD" \`
18	56	olivier.gi	`[get_ports dco_clk]`
19	2	olivier.gi
20
21			`##############################################################################`
22			`# #`
23			`# CREATE PATH GROUPS #`
24			`# #`
25			`##############################################################################`
26
27			`group_path -name REGOUT -to [all_outputs]`
28	56	olivier.gi	`group_path -name REGIN -from [remove_from_collection [all_inputs] [get_ports dco_clk]]`
29			`group_path -name FEEDTHROUGH -from [remove_from_collection [all_inputs] [get_ports dco_clk]] -to [all_outputs]`
30	2	olivier.gi
31
32			`##############################################################################`
33			`# #`
34			`# BOUNDARY TIMINGS #`
35			`# #`
36			`##############################################################################`
37	56	olivier.gi	`# NOTE: There are some path through between Program/Data memory signals`
38			`# which are limiting the maximum frequency achievable by the core.`
39			`# The memory constraints set on these interfaces are therefore quite`
40			`# critical regarding the achievable performance of the core.`
41			`# As a consequence, the constrains on the pmem_/dmem_ signals must`
42			`# be set with some absolute values as they are specified by the targeted`
43			`# process RAM/ROM generator.`
44	2	olivier.gi
45	56	olivier.gi	`#================#`
46			`# PROGRAM MEMORY #`
47			`#================#`
48	2	olivier.gi
49	56	olivier.gi	`set PMEM_DOUT_DLY 2.25`
50	2	olivier.gi
51	56	olivier.gi	`set PMEM_ADDR_DLY 0.64`
52			`set PMEM_CEN_DLY 0.63`
53			`set PMEM_DIN_DLY 0.39`
54			`set PMEM_WEN_DLY 0.44`
55	2	olivier.gi
56	56	olivier.gi	`set_input_delay $PMEM_DOUT_DLY -max -clock "dco_clk" [get_ports pmem_dout]`
57			`set_input_delay 0 -min -clock "dco_clk" [get_ports pmem_dout]`
58	2	olivier.gi
59	56	olivier.gi	`set_output_delay $PMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_addr]`
60			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_addr]`
61	2	olivier.gi
62	56	olivier.gi	`set_output_delay $PMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_cen]`
63			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_cen]`
64	2	olivier.gi
65	56	olivier.gi	`set_output_delay $PMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_din]`
66			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_din]`
67	2	olivier.gi
68	56	olivier.gi	`set_output_delay $PMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports pmem_wen]`
69			`set_output_delay 0 -min -clock "dco_clk" [get_ports pmem_wen]`
70	2	olivier.gi
71
72	56	olivier.gi	`#================#`
73			`# DATA MEMORY #`
74			`#================#`
75	2	olivier.gi
76	56	olivier.gi	`set DMEM_DOUT_DLY 2.25`
77	2	olivier.gi
78	56	olivier.gi	`set DMEM_ADDR_DLY 0.64`
79			`set DMEM_CEN_DLY 0.63`
80			`set DMEM_DIN_DLY 0.39`
81			`set DMEM_WEN_DLY 0.44`
82	2	olivier.gi
83
84	56	olivier.gi	`set_input_delay $DMEM_DOUT_DLY -max -clock "dco_clk" [get_ports dmem_dout]`
85			`set_input_delay 0 -min -clock "dco_clk" [get_ports dmem_dout]`
86	2	olivier.gi
87	56	olivier.gi	`set_output_delay $DMEM_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_addr]`
88			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_addr]`
89	2	olivier.gi
90	56	olivier.gi	`set_output_delay $DMEM_CEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_cen]`
91			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_cen]`
92	2	olivier.gi
93	56	olivier.gi	`set_output_delay $DMEM_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_din]`
94			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_din]`
95	2	olivier.gi
96	56	olivier.gi	`set_output_delay $DMEM_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports dmem_wen]`
97			`set_output_delay 0 -min -clock "dco_clk" [get_ports dmem_wen]`
98	2	olivier.gi
99
100	56	olivier.gi	`#==========================#`
101			`# REMAINING INPUT PORTS #`
102			`#==========================#`
103	2	olivier.gi
104	56	olivier.gi	`set IRQ_DLY [expr ($CLOCK_PERIOD/100) * 30]`
105			`set PER_DOUT_DLY [expr ($CLOCK_PERIOD/100) * 20]`
106	2	olivier.gi
107
108	56	olivier.gi	`set_input_delay $IRQ_DLY -max -clock "dco_clk" [get_ports irq]`
109			`set_input_delay 0 -min -clock "dco_clk" [get_ports irq]`
110	2	olivier.gi
111	56	olivier.gi	`set_input_delay $PER_DOUT_DLY -max -clock "dco_clk" [get_ports per_dout]`
112			`set_input_delay 0 -min -clock "dco_clk" [get_ports per_dout]`
113	2	olivier.gi
114
115	56	olivier.gi	`#=========================#`
116			`# REMAINING OUTPUT PORTS #`
117			`#=========================#`
118	2	olivier.gi
119	56	olivier.gi	`set ACLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]`
120			`set SMCLK_EN_DLY [expr ($CLOCK_PERIOD/100) * 85]`
121			`set DBG_FREEZE_DLY [expr ($CLOCK_PERIOD/100) * 85]`
122			`set IRQ_ACC_DLY [expr ($CLOCK_PERIOD/100) * 60]`
123	2	olivier.gi
124	56	olivier.gi	`set PER_ADDR_DLY [expr ($CLOCK_PERIOD/100) * 25]`
125			`set PER_DIN_DLY [expr ($CLOCK_PERIOD/100) * 25]`
126			`set PER_WEN_DLY [expr ($CLOCK_PERIOD/100) * 25]`
127			`set PER_EN_DLY [expr ($CLOCK_PERIOD/100) * 25]`
128	2	olivier.gi
129	56	olivier.gi	`set PUC_DLY [expr ($CLOCK_PERIOD/100) * 75]`
130	2	olivier.gi
131
132	56	olivier.gi	`set_output_delay $ACLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports aclk_en]`
133			`set_output_delay 0 -min -clock "dco_clk" [get_ports aclk_en]`
134	2	olivier.gi
135	56	olivier.gi	`set_output_delay $SMCLK_EN_DLY -add_delay -max -clock "dco_clk" [get_ports smclk_en]`
136			`set_output_delay 0 -min -clock "dco_clk" [get_ports smclk_en]`
137
138			`set_output_delay $DBG_FREEZE_DLY -add_delay -max -clock "dco_clk" [get_ports dbg_freeze]`
139			`set_output_delay 0 -min -clock "dco_clk" [get_ports dbg_freeze]`
140
141			`set_output_delay $IRQ_ACC_DLY -add_delay -max -clock "dco_clk" [get_ports irq_acc]`
142			`set_output_delay 0 -min -clock "dco_clk" [get_ports irq_acc]`
143
144
145			`set_output_delay $PER_ADDR_DLY -add_delay -max -clock "dco_clk" [get_ports per_addr]`
146			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_addr]`
147
148			`set_output_delay $PER_DIN_DLY -add_delay -max -clock "dco_clk" [get_ports per_din]`
149			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_din]`
150
151			`set_output_delay $PER_WEN_DLY -add_delay -max -clock "dco_clk" [get_ports per_wen]`
152			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_wen]`
153
154			`set_output_delay $PER_EN_DLY -add_delay -max -clock "dco_clk" [get_ports per_en]`
155			`set_output_delay 0 -min -clock "dco_clk" [get_ports per_en]`
156
157			`set_output_delay $PUC_DLY -add_delay -max -clock "dco_clk" -clock_fall [get_ports puc]`
158			`set_output_delay 0 -min -clock "dco_clk" -clock_fall [get_ports puc]`
159
160
161	2	olivier.gi	`#========================#`
162			`# FEEDTHROUGH EXCEPTIONS #`
163			`#========================#`
164
165	56	olivier.gi	`#set_max_delay [expr 2.0 + $DMEM_DOUT_DLY + $DMEM_ADDR_DLY] \`
166			`# -from [get_ports dmem_dout] \`
167			`# -to [get_ports dmem_addr] \`
168	2	olivier.gi	`# -group_path FEEDTHROUGH`
169
170	56	olivier.gi
171			`#===============#`
172			`# FALSE PATHS #`
173			`#===============#`
174			`# The following signals are internaly synchronized to`
175			`# the dco_clk domain and can be set as false path.`
176
177			`set_false_path -from dbg_uart_rxd`
178			`set_false_path -to dbg_uart_txd`
179
180			`set_false_path -from nmi`
181			`set_false_path -from lfxt_clk`
182			`set_false_path -from reset_n`

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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [synopsys/] [constraints.tcl] - Blame information for rev 60