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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [openMSP430_fpga.ucf] - Blame information for rev 62

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1 62 olivier.gi
#=============================================================================
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# Copyright (C) 2001 Authors
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#
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# This source file may be used and distributed without restriction provided
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# that this copyright statement is not removed from the file and that any
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# derivative work contains the original copyright notice and the associated
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# disclaimer.
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#
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# This source file is free software; you can redistribute it and/or modify
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# it under the terms of the GNU Lesser General Public License as published
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# by the Free Software Foundation; either version 2.1 of the License, or
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# (at your option) any later version.
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#
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# This source is distributed in the hope that it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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# License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public License
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# along with this source; if not, write to the Free Software Foundation,
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# Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
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#
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#-----------------------------------------------------------------------------
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#
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# File Name: openMSP430_fpga.ucf
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#
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# Author(s):
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#             - Olivier Girard,    olgirard@gmail.com
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#
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#-----------------------------------------------------------------------------
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# $Rev: 26 $
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# $LastChangedBy: olivier.girard $
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# $LastChangedDate: 2009-12-19 13:25:10 +0100 (Sat, 19 Dec 2009) $
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#=============================================================================
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#-----------------------------------------------------------------------------#
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# Clock configuration & ROM Block Assignments                                 #
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#-----------------------------------------------------------------------------#
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# CLOCKS Definition
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NET "dco_clk" PERIOD =  nS LOW  nS;
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