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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.area.log] - Blame information for rev 62

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Line No. Rev Author Line
1 62 olivier.gi 
#####################################################################################
2 
#                            START SYNTHESIS (AREA optimized)
3 
#====================================================================================
4 
# spartan3 (xc3s400pq208), speedgrade: -4
5 
#====================================================================================
6 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
7 
#     12          10          0         0            0          0            0
8 
#====================================================================================
9 
Clock to Setup on destination clock dco_clk
10 
---------------+---------+---------+---------+---------+
11 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
12 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
13 
---------------+---------+---------+---------+---------+
14 
dco_clk        |   39.257|         |         |    1.564|
15 
---------------+---------+---------+---------+---------+
16 
 
17 
====================================================================================
18 
Device utilization summary:
19 
---------------------------
20 
 
21 
Selected Device : 3s400pq208-4
22 
 
23 
 Number of Slices:                      898  out of   3584    25%
24 
 Number of Slice Flip Flops:            458  out of   7168     6%
25 
 Number of 4 input LUTs:               1609  out of   7168    22%
26 
 Number of IOs:                          80
27 
 Number of bonded IOBs:                  79  out of    141    56%
28 
    IOB Flip Flops:                      14
29 
 Number of BRAMs:                         6  out of     16    37%
30 
 Number of GCLKs:                         1  out of      8    12%
31 
 
32 
---------------------------
33 
 
34 
====================================================================================
35 
#                            SYNTHESIS DONE
36 
#####################################################################################
37 
 
38 
#####################################################################################
39 
#                            START SYNTHESIS (AREA optimized)
40 
#====================================================================================
41 
# spartan3 (xc3s400pq208), speedgrade: -5
42 
#====================================================================================
43 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
44 
#     12          10          0         0            0          0            0
45 
#====================================================================================
46 
Clock to Setup on destination clock dco_clk
47 
---------------+---------+---------+---------+---------+
48 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
49 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
50 
---------------+---------+---------+---------+---------+
51 
dco_clk        |   32.419|         |         |    1.361|
52 
---------------+---------+---------+---------+---------+
53 
 
54 
====================================================================================
55 
Device utilization summary:
56 
---------------------------
57 
 
58 
Selected Device : 3s400pq208-5
59 
 
60 
 Number of Slices:                      898  out of   3584    25%
61 
 Number of Slice Flip Flops:            458  out of   7168     6%
62 
 Number of 4 input LUTs:               1609  out of   7168    22%
63 
 Number of IOs:                          80
64 
 Number of bonded IOBs:                  79  out of    141    56%
65 
    IOB Flip Flops:                      14
66 
 Number of BRAMs:                         6  out of     16    37%
67 
 Number of GCLKs:                         1  out of      8    12%
68 
 
69 
---------------------------
70 
 
71 
====================================================================================
72 
#                            SYNTHESIS DONE
73 
#####################################################################################
74 
 
75 
#####################################################################################
76 
#                            START SYNTHESIS (AREA optimized)
77 
#====================================================================================
78 
# spartan3e (xc3s500epq208), speedgrade: -4
79 
#====================================================================================
80 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
81 
#     12          10          0         0            0          0            0
82 
#====================================================================================
83 
Clock to Setup on destination clock dco_clk
84 
---------------+---------+---------+---------+---------+
85 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
86 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
87 
---------------+---------+---------+---------+---------+
88 
dco_clk        |   37.815|         |         |    1.467|
89 
---------------+---------+---------+---------+---------+
90 
 
91 
====================================================================================
92 
Device utilization summary:
93 
---------------------------
94 
 
95 
Selected Device : 3s500epq208-4
96 
 
97 
 Number of Slices:                      903  out of   4656    19%
98 
 Number of Slice Flip Flops:            458  out of   9312     4%
99 
 Number of 4 input LUTs:               1615  out of   9312    17%
100 
 Number of IOs:                          80
101 
 Number of bonded IOBs:                  79  out of    158    50%
102 
    IOB Flip Flops:                      14
103 
 Number of BRAMs:                         6  out of     20    30%
104 
 Number of GCLKs:                         1  out of     24     4%
105 
 
106 
---------------------------
107 
 
108 
====================================================================================
109 
#                            SYNTHESIS DONE
110 
#####################################################################################
111 
 
112 
#####################################################################################
113 
#                            START SYNTHESIS (AREA optimized)
114 
#====================================================================================
115 
# spartan3e (xc3s500epq208), speedgrade: -5
116 
#====================================================================================
117 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
118 
#     12          10          0         0            0          0            0
119 
#====================================================================================
120 
Clock to Setup on destination clock dco_clk
121 
---------------+---------+---------+---------+---------+
122 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
123 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
124 
---------------+---------+---------+---------+---------+
125 
dco_clk        |   31.547|         |         |    1.276|
126 
---------------+---------+---------+---------+---------+
127 
 
128 
====================================================================================
129 
Device utilization summary:
130 
---------------------------
131 
 
132 
Selected Device : 3s500epq208-5
133 
 
134 
 Number of Slices:                      903  out of   4656    19%
135 
 Number of Slice Flip Flops:            458  out of   9312     4%
136 
 Number of 4 input LUTs:               1615  out of   9312    17%
137 
 Number of IOs:                          80
138 
 Number of bonded IOBs:                  79  out of    158    50%
139 
    IOB Flip Flops:                      14
140 
 Number of BRAMs:                         6  out of     20    30%
141 
 Number of GCLKs:                         1  out of     24     4%
142 
 
143 
---------------------------
144 
 
145 
====================================================================================
146 
#                            SYNTHESIS DONE
147 
#####################################################################################
148 
 
149 
#####################################################################################
150 
#                            START SYNTHESIS (AREA optimized)
151 
#====================================================================================
152 
# spartan3a (xc3s700aft256), speedgrade: -4
153 
#====================================================================================
154 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
155 
#     12          10          0         0            0          0            0
156 
#====================================================================================
157 
Clock to Setup on destination clock dco_clk
158 
---------------+---------+---------+---------+---------+
159 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
160 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
161 
---------------+---------+---------+---------+---------+
162 
dco_clk        |   37.308|         |         |    1.511|
163 
---------------+---------+---------+---------+---------+
164 
 
165 
====================================================================================
166 
Device utilization summary:
167 
---------------------------
168 
 
169 
Selected Device : 3s700aft256-4
170 
 
171 
 Number of Slices:                      911  out of   5888    15%
172 
 Number of Slice Flip Flops:            459  out of  11776     3%
173 
 Number of 4 input LUTs:               1629  out of  11776    13%
174 
 Number of IOs:                          80
175 
 Number of bonded IOBs:                  79  out of    161    49%
176 
    IOB Flip Flops:                      14
177 
 Number of BRAMs:                         5  out of     20    25%
178 
 Number of GCLKs:                         1  out of     24     4%
179 
 
180 
---------------------------
181 
 
182 
====================================================================================
183 
#                            SYNTHESIS DONE
184 
#####################################################################################
185 
 
186 
#####################################################################################
187 
#                            START SYNTHESIS (AREA optimized)
188 
#====================================================================================
189 
# spartan3a (xc3s700aft256), speedgrade: -5
190 
#====================================================================================
191 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
192 
#     12          10          0         0            0          0            0
193 
#====================================================================================
194 
Clock to Setup on destination clock dco_clk
195 
---------------+---------+---------+---------+---------+
196 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
197 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
198 
---------------+---------+---------+---------+---------+
199 
dco_clk        |   34.264|         |         |    1.192|
200 
---------------+---------+---------+---------+---------+
201 
 
202 
====================================================================================
203 
Device utilization summary:
204 
---------------------------
205 
 
206 
Selected Device : 3s700aft256-5
207 
 
208 
 Number of Slices:                      908  out of   5888    15%
209 
 Number of Slice Flip Flops:            459  out of  11776     3%
210 
 Number of 4 input LUTs:               1622  out of  11776    13%
211 
 Number of IOs:                          80
212 
 Number of bonded IOBs:                  79  out of    161    49%
213 
    IOB Flip Flops:                      14
214 
 Number of BRAMs:                         5  out of     20    25%
215 
 Number of GCLKs:                         1  out of     24     4%
216 
 
217 
---------------------------
218 
 
219 
====================================================================================
220 
#                            SYNTHESIS DONE
221 
#####################################################################################
222 
 
223 
#####################################################################################
224 
#                            START SYNTHESIS (AREA optimized)
225 
#====================================================================================
226 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
227 
#====================================================================================
228 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
229 
#     12          10          0         0            0          0            0
230 
#====================================================================================
231 
Clock to Setup on destination clock dco_clk
232 
---------------+---------+---------+---------+---------+
233 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
234 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
235 
---------------+---------+---------+---------+---------+
236 
dco_clk        |   37.189|         |         |    1.448|
237 
---------------+---------+---------+---------+---------+
238 
 
239 
====================================================================================
240 
Device utilization summary:
241 
---------------------------
242 
 
243 
Selected Device : 3sd1800acs484-4
244 
 
245 
 Number of Slices:                      913  out of  16640     5%
246 
 Number of Slice Flip Flops:            459  out of  33280     1%
247 
 Number of 4 input LUTs:               1628  out of  33280     4%
248 
 Number of IOs:                          80
249 
 Number of bonded IOBs:                  79  out of    309    25%
250 
    IOB Flip Flops:                      14
251 
 Number of BRAMs:                         5  out of     84     5%
252 
 Number of GCLKs:                         1  out of     24     4%
253 
 
254 
---------------------------
255 
 
256 
====================================================================================
257 
#                            SYNTHESIS DONE
258 
#####################################################################################
259 
 
260 
#####################################################################################
261 
#                            START SYNTHESIS (AREA optimized)
262 
#====================================================================================
263 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
264 
#====================================================================================
265 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
266 
#     12          10          0         0            0          0            0
267 
#====================================================================================
268 
Clock to Setup on destination clock dco_clk
269 
---------------+---------+---------+---------+---------+
270 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
271 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
272 
---------------+---------+---------+---------+---------+
273 
dco_clk        |   31.333|         |         |    1.192|
274 
---------------+---------+---------+---------+---------+
275 
 
276 
====================================================================================
277 
Device utilization summary:
278 
---------------------------
279 
 
280 
Selected Device : 3sd1800acs484-5
281 
 
282 
 Number of Slices:                      911  out of  16640     5%
283 
 Number of Slice Flip Flops:            459  out of  33280     1%
284 
 Number of 4 input LUTs:               1621  out of  33280     4%
285 
 Number of IOs:                          80
286 
 Number of bonded IOBs:                  79  out of    309    25%
287 
    IOB Flip Flops:                      14
288 
 Number of BRAMs:                         5  out of     84     5%
289 
 Number of GCLKs:                         1  out of     24     4%
290 
 
291 
---------------------------
292 
 
293 
====================================================================================
294 
#                            SYNTHESIS DONE
295 
#####################################################################################
296 
 
297 
#####################################################################################
298 
#                            START SYNTHESIS (AREA optimized)
299 
#====================================================================================
300 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
301 
#====================================================================================
302 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
303 
#     12          10          0         0            0          0            0
304 
#====================================================================================
305 
Clock to Setup on destination clock dco_clk
306 
---------------+---------+---------+---------+---------+
307 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
308 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
309 
---------------+---------+---------+---------+---------+
310 
dco_clk        |   30.902|    5.802|    2.842|    2.681|
311 
---------------+---------+---------+---------+---------+
312 
 
313 
====================================================================================
314 
Device utilization summary:
315 
---------------------------
316 
 
317 
Selected Device : 6slx45tfgg484-2
318 
 
319 
 
320 
Slice Logic Utilization:
321 
 Number of Slice Registers:             459  out of  54576     0%
322 
 Number of Slice LUTs:                 1277  out of  27288     4%
323 
    Number used as Logic:              1277  out of  27288     4%
324 
 
325 
Slice Logic Distribution:
326 
 Number of LUT Flip Flop pairs used:   1303
327 
   Number with an unused Flip Flop:     844  out of   1303    64%
328 
   Number with an unused LUT:            26  out of   1303     1%
329 
   Number of fully used LUT-FF pairs:   433  out of   1303    33%
330 
   Number of unique control sets:        45
331 
 
332 
IO Utilization:
333 
 Number of IOs:                          80
334 
 Number of bonded IOBs:                  79  out of    296    26%
335 
    IOB Flip Flops/Latches:              14
336 
 
337 
Specific Feature Utilization:
338 
 Number of Block RAM/FIFO:                5  out of    348     1%
339 
    Number using Block RAM only:          5
340 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
341 
 
342 
---------------------------
343 
 
344 
====================================================================================
345 
#                            SYNTHESIS DONE
346 
#####################################################################################
347 
 
348 
#####################################################################################
349 
#                            START SYNTHESIS (AREA optimized)
350 
#====================================================================================
351 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
352 
#====================================================================================
353 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
354 
#     12          10          0         0            0          0            0
355 
#====================================================================================
356 
Clock to Setup on destination clock dco_clk
357 
---------------+---------+---------+---------+---------+
358 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
359 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
360 
---------------+---------+---------+---------+---------+
361 
dco_clk        |   23.567|    4.891|    2.052|    1.687|
362 
---------------+---------+---------+---------+---------+
363 
 
364 
====================================================================================
365 
Device utilization summary:
366 
---------------------------
367 
 
368 
Selected Device : 6slx45tfgg484-3
369 
 
370 
 
371 
Slice Logic Utilization:
372 
 Number of Slice Registers:             459  out of  54576     0%
373 
 Number of Slice LUTs:                 1271  out of  27288     4%
374 
    Number used as Logic:              1271  out of  27288     4%
375 
 
376 
Slice Logic Distribution:
377 
 Number of LUT Flip Flop pairs used:   1296
378 
   Number with an unused Flip Flop:     837  out of   1296    64%
379 
   Number with an unused LUT:            25  out of   1296     1%
380 
   Number of fully used LUT-FF pairs:   434  out of   1296    33%
381 
   Number of unique control sets:        45
382 
 
383 
IO Utilization:
384 
 Number of IOs:                          80
385 
 Number of bonded IOBs:                  79  out of    296    26%
386 
    IOB Flip Flops/Latches:              14
387 
 
388 
Specific Feature Utilization:
389 
 Number of Block RAM/FIFO:                5  out of    348     1%
390 
    Number using Block RAM only:          5
391 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
392 
 
393 
---------------------------
394 
 
395 
====================================================================================
396 
#                            SYNTHESIS DONE
397 
#####################################################################################
398 
 
399 
#####################################################################################
400 
#                            START SYNTHESIS (AREA optimized)
401 
#====================================================================================
402 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
403 
#====================================================================================
404 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
405 
#     12          10          0         0            0          0            0
406 
#====================================================================================
407 
Clock to Setup on destination clock dco_clk
408 
---------------+---------+---------+---------+---------+
409 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
410 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
411 
---------------+---------+---------+---------+---------+
412 
dco_clk        |   20.735|    4.685|    1.744|    1.583|
413 
---------------+---------+---------+---------+---------+
414 
 
415 
====================================================================================
416 
Device utilization summary:
417 
---------------------------
418 
 
419 
Selected Device : 6slx45tfgg484-4
420 
 
421 
 
422 
Slice Logic Utilization:
423 
 Number of Slice Registers:             459  out of  54576     0%
424 
 Number of Slice LUTs:                 1267  out of  27288     4%
425 
    Number used as Logic:              1267  out of  27288     4%
426 
 
427 
Slice Logic Distribution:
428 
 Number of LUT Flip Flop pairs used:   1292
429 
   Number with an unused Flip Flop:     833  out of   1292    64%
430 
   Number with an unused LUT:            25  out of   1292     1%
431 
   Number of fully used LUT-FF pairs:   434  out of   1292    33%
432 
   Number of unique control sets:        45
433 
 
434 
IO Utilization:
435 
 Number of IOs:                          80
436 
 Number of bonded IOBs:                  79  out of    296    26%
437 
    IOB Flip Flops/Latches:              14
438 
 
439 
Specific Feature Utilization:
440 
 Number of Block RAM/FIFO:                5  out of    348     1%
441 
    Number using Block RAM only:          5
442 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
443 
 
444 
---------------------------
445 
 
446 
====================================================================================
447 
#                            SYNTHESIS DONE
448 
#####################################################################################
449 
 
450 
#####################################################################################
451 
#                            START SYNTHESIS (AREA optimized)
452 
#====================================================================================
453 
# virtex4 (xc4vlx25sf363), speedgrade: -10
454 
#====================================================================================
455 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
456 
#     12          10          0         0            0          0            0
457 
#====================================================================================
458 
Clock to Setup on destination clock dco_clk
459 
---------------+---------+---------+---------+---------+
460 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
461 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
462 
---------------+---------+---------+---------+---------+
463 
dco_clk        |   23.754|         |         |    1.115|
464 
---------------+---------+---------+---------+---------+
465 
 
466 
====================================================================================
467 
Device utilization summary:
468 
---------------------------
469 
 
470 
Selected Device : 4vlx25sf363-10
471 
 
472 
 Number of Slices:                      911  out of  10752     8%
473 
 Number of Slice Flip Flops:            459  out of  21504     2%
474 
 Number of 4 input LUTs:               1629  out of  21504     7%
475 
 Number of IOs:                          80
476 
 Number of bonded IOBs:                  79  out of    240    32%
477 
    IOB Flip Flops:                      14
478 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
479 
    Number used as RAMB16s:               5
480 
 Number of GCLKs:                         1  out of     32     3%
481 
 
482 
---------------------------
483 
 
484 
====================================================================================
485 
#                            SYNTHESIS DONE
486 
#####################################################################################
487 
 
488 
#####################################################################################
489 
#                            START SYNTHESIS (AREA optimized)
490 
#====================================================================================
491 
# virtex4 (xc4vlx25sf363), speedgrade: -11
492 
#====================================================================================
493 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
494 
#     12          10          0         0            0          0            0
495 
#====================================================================================
496 
Clock to Setup on destination clock dco_clk
497 
---------------+---------+---------+---------+---------+
498 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
499 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
500 
---------------+---------+---------+---------+---------+
501 
dco_clk        |   19.719|         |         |    0.952|
502 
---------------+---------+---------+---------+---------+
503 
 
504 
====================================================================================
505 
Device utilization summary:
506 
---------------------------
507 
 
508 
Selected Device : 4vlx25sf363-11
509 
 
510 
 Number of Slices:                      912  out of  10752     8%
511 
 Number of Slice Flip Flops:            459  out of  21504     2%
512 
 Number of 4 input LUTs:               1632  out of  21504     7%
513 
 Number of IOs:                          80
514 
 Number of bonded IOBs:                  79  out of    240    32%
515 
    IOB Flip Flops:                      14
516 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
517 
    Number used as RAMB16s:               5
518 
 Number of GCLKs:                         1  out of     32     3%
519 
 
520 
---------------------------
521 
 
522 
====================================================================================
523 
#                            SYNTHESIS DONE
524 
#####################################################################################
525 
 
526 
#####################################################################################
527 
#                            START SYNTHESIS (AREA optimized)
528 
#====================================================================================
529 
# virtex4 (xc4vlx25sf363), speedgrade: -12
530 
#====================================================================================
531 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
532 
#     12          10          0         0            0          0            0
533 
#====================================================================================
534 
Clock to Setup on destination clock dco_clk
535 
---------------+---------+---------+---------+---------+
536 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
537 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
538 
---------------+---------+---------+---------+---------+
539 
dco_clk        |   17.362|         |         |    0.846|
540 
---------------+---------+---------+---------+---------+
541 
 
542 
====================================================================================
543 
Device utilization summary:
544 
---------------------------
545 
 
546 
Selected Device : 4vlx25sf363-12
547 
 
548 
 Number of Slices:                      910  out of  10752     8%
549 
 Number of Slice Flip Flops:            459  out of  21504     2%
550 
 Number of 4 input LUTs:               1627  out of  21504     7%
551 
 Number of IOs:                          80
552 
 Number of bonded IOBs:                  79  out of    240    32%
553 
    IOB Flip Flops:                      14
554 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
555 
    Number used as RAMB16s:               5
556 
 Number of GCLKs:                         1  out of     32     3%
557 
 
558 
---------------------------
559 
 
560 
====================================================================================
561 
#                            SYNTHESIS DONE
562 
#####################################################################################
563 
 
564 
#####################################################################################
565 
#                            START SYNTHESIS (AREA optimized)
566 
#====================================================================================
567 
# virtex5 (xc5vlx30ff324), speedgrade: -1
568 
#====================================================================================
569 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
570 
#     12          10          0         0            0          0            0
571 
#====================================================================================
572 
Clock to Setup on destination clock dco_clk
573 
---------------+---------+---------+---------+---------+
574 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
575 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
576 
---------------+---------+---------+---------+---------+
577 
dco_clk        |   16.457|         |         |    1.310|
578 
---------------+---------+---------+---------+---------+
579 
 
580 
====================================================================================
581 
Device utilization summary:
582 
---------------------------
583 
 
584 
Selected Device : 5vlx30ff324-1
585 
 
586 
 
587 
Slice Logic Utilization:
588 
 Number of Slice Registers:             458  out of  19200     2%
589 
 Number of Slice LUTs:                 1219  out of  19200     6%
590 
    Number used as Logic:              1219  out of  19200     6%
591 
 
592 
Slice Logic Distribution:
593 
 Number of LUT Flip Flop pairs used:   1245
594 
   Number with an unused Flip Flop:     787  out of   1245    63%
595 
   Number with an unused LUT:            26  out of   1245     2%
596 
   Number of fully used LUT-FF pairs:   432  out of   1245    34%
597 
   Number of unique control sets:        43
598 
 
599 
IO Utilization:
600 
 Number of IOs:                          80
601 
 Number of bonded IOBs:                  79  out of    220    35%
602 
    IOB Flip Flops/Latches:              14
603 
 
604 
Specific Feature Utilization:
605 
 Number of Block RAM/FIFO:                3  out of     32     9%
606 
    Number using Block RAM only:          3
607 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
608 
 
609 
---------------------------
610 
 
611 
====================================================================================
612 
#                            SYNTHESIS DONE
613 
#####################################################################################
614 
 
615 
#####################################################################################
616 
#                            START SYNTHESIS (AREA optimized)
617 
#====================================================================================
618 
# virtex5 (xc5vlx30ff324), speedgrade: -2
619 
#====================================================================================
620 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
621 
#     12          10          0         0            0          0            0
622 
#====================================================================================
623 
Clock to Setup on destination clock dco_clk
624 
---------------+---------+---------+---------+---------+
625 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
626 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
627 
---------------+---------+---------+---------+---------+
628 
dco_clk        |   14.062|         |         |    0.682|
629 
---------------+---------+---------+---------+---------+
630 
 
631 
====================================================================================
632 
Device utilization summary:
633 
---------------------------
634 
 
635 
Selected Device : 5vlx30ff324-2
636 
 
637 
 
638 
Slice Logic Utilization:
639 
 Number of Slice Registers:             458  out of  19200     2%
640 
 Number of Slice LUTs:                 1221  out of  19200     6%
641 
    Number used as Logic:              1221  out of  19200     6%
642 
 
643 
Slice Logic Distribution:
644 
 Number of LUT Flip Flop pairs used:   1247
645 
   Number with an unused Flip Flop:     789  out of   1247    63%
646 
   Number with an unused LUT:            26  out of   1247     2%
647 
   Number of fully used LUT-FF pairs:   432  out of   1247    34%
648 
   Number of unique control sets:        43
649 
 
650 
IO Utilization:
651 
 Number of IOs:                          80
652 
 Number of bonded IOBs:                  79  out of    220    35%
653 
    IOB Flip Flops/Latches:              14
654 
 
655 
Specific Feature Utilization:
656 
 Number of Block RAM/FIFO:                3  out of     32     9%
657 
    Number using Block RAM only:          3
658 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
659 
 
660 
---------------------------
661 
 
662 
====================================================================================
663 
#                            SYNTHESIS DONE
664 
#####################################################################################
665 
 
666 
#####################################################################################
667 
#                            START SYNTHESIS (AREA optimized)
668 
#====================================================================================
669 
# virtex5 (xc5vlx30ff324), speedgrade: -3
670 
#====================================================================================
671 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
672 
#     12          10          0         0            0          0            0
673 
#====================================================================================
674 
Clock to Setup on destination clock dco_clk
675 
---------------+---------+---------+---------+---------+
676 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
677 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
678 
---------------+---------+---------+---------+---------+
679 
dco_clk        |   12.982|         |         |    0.605|
680 
---------------+---------+---------+---------+---------+
681 
 
682 
====================================================================================
683 
Device utilization summary:
684 
---------------------------
685 
 
686 
Selected Device : 5vlx30ff324-3
687 
 
688 
 
689 
Slice Logic Utilization:
690 
 Number of Slice Registers:             458  out of  19200     2%
691 
 Number of Slice LUTs:                 1215  out of  19200     6%
692 
    Number used as Logic:              1215  out of  19200     6%
693 
 
694 
Slice Logic Distribution:
695 
 Number of LUT Flip Flop pairs used:   1241
696 
   Number with an unused Flip Flop:     783  out of   1241    63%
697 
   Number with an unused LUT:            26  out of   1241     2%
698 
   Number of fully used LUT-FF pairs:   432  out of   1241    34%
699 
   Number of unique control sets:        43
700 
 
701 
IO Utilization:
702 
 Number of IOs:                          80
703 
 Number of bonded IOBs:                  79  out of    220    35%
704 
    IOB Flip Flops/Latches:              14
705 
 
706 
Specific Feature Utilization:
707 
 Number of Block RAM/FIFO:                3  out of     32     9%
708 
    Number using Block RAM only:          3
709 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
710 
 
711 
---------------------------
712 
 
713 
====================================================================================
714 
#                            SYNTHESIS DONE
715 
#####################################################################################
716 
 
717 
#####################################################################################
718 
#                            START SYNTHESIS (AREA optimized)
719 
#====================================================================================
720 
# virtex6 (xc6vlx75tff484), speedgrade: -1
721 
#====================================================================================
722 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
723 
#     12          10          0         0            0          0            0
724 
#====================================================================================
725 
Clock to Setup on destination clock dco_clk
726 
---------------+---------+---------+---------+---------+
727 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
728 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
729 
---------------+---------+---------+---------+---------+
730 
dco_clk        |   13.415|    3.960|    2.270|    0.606|
731 
---------------+---------+---------+---------+---------+
732 
 
733 
====================================================================================
734 
Device utilization summary:
735 
---------------------------
736 
 
737 
Selected Device : 6vlx75tff484-1
738 
 
739 
 
740 
Slice Logic Utilization:
741 
 Number of Slice Registers:             458  out of  93120     0%
742 
 Number of Slice LUTs:                 1237  out of  46560     2%
743 
    Number used as Logic:              1237  out of  46560     2%
744 
 
745 
Slice Logic Distribution:
746 
 Number of LUT Flip Flop pairs used:   1263
747 
   Number with an unused Flip Flop:     805  out of   1263    63%
748 
   Number with an unused LUT:            26  out of   1263     2%
749 
   Number of fully used LUT-FF pairs:   432  out of   1263    34%
750 
   Number of unique control sets:        44
751 
 
752 
IO Utilization:
753 
 Number of IOs:                          80
754 
 Number of bonded IOBs:                  79  out of    240    32%
755 
    IOB Flip Flops/Latches:              14
756 
 
757 
Specific Feature Utilization:
758 
 Number of Block RAM/FIFO:                3  out of    156     1%
759 
    Number using Block RAM only:          3
760 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
761 
 
762 
---------------------------
763 
 
764 
====================================================================================
765 
#                            SYNTHESIS DONE
766 
#####################################################################################
767 
 
768 
#####################################################################################
769 
#                            START SYNTHESIS (AREA optimized)
770 
#====================================================================================
771 
# virtex6 (xc6vlx75tff484), speedgrade: -2
772 
#====================================================================================
773 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
774 
#     12          10          0         0            0          0            0
775 
#====================================================================================
776 
Clock to Setup on destination clock dco_clk
777 
---------------+---------+---------+---------+---------+
778 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
779 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
780 
---------------+---------+---------+---------+---------+
781 
dco_clk        |   11.658|    2.819|    1.524|    0.593|
782 
---------------+---------+---------+---------+---------+
783 
 
784 
====================================================================================
785 
Device utilization summary:
786 
---------------------------
787 
 
788 
Selected Device : 6vlx75tff484-2
789 
 
790 
 
791 
Slice Logic Utilization:
792 
 Number of Slice Registers:             458  out of  93120     0%
793 
 Number of Slice LUTs:                 1235  out of  46560     2%
794 
    Number used as Logic:              1235  out of  46560     2%
795 
 
796 
Slice Logic Distribution:
797 
 Number of LUT Flip Flop pairs used:   1261
798 
   Number with an unused Flip Flop:     803  out of   1261    63%
799 
   Number with an unused LUT:            26  out of   1261     2%
800 
   Number of fully used LUT-FF pairs:   432  out of   1261    34%
801 
   Number of unique control sets:        44
802 
 
803 
IO Utilization:
804 
 Number of IOs:                          80
805 
 Number of bonded IOBs:                  79  out of    240    32%
806 
    IOB Flip Flops/Latches:              14
807 
 
808 
Specific Feature Utilization:
809 
 Number of Block RAM/FIFO:                3  out of    156     1%
810 
    Number using Block RAM only:          3
811 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
812 
 
813 
---------------------------
814 
 
815 
====================================================================================
816 
#                            SYNTHESIS DONE
817 
#####################################################################################
818 
 
819 
#####################################################################################
820 
#                            START SYNTHESIS (AREA optimized)
821 
#====================================================================================
822 
# virtex6 (xc6vlx75tff484), speedgrade: -3
823 
#====================================================================================
824 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
825 
#     12          10          0         0            0          0            0
826 
#====================================================================================
827 
Clock to Setup on destination clock dco_clk
828 
---------------+---------+---------+---------+---------+
829 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
830 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
831 
---------------+---------+---------+---------+---------+
832 
dco_clk        |   10.295|    3.146|    1.265|    0.463|
833 
---------------+---------+---------+---------+---------+
834 
 
835 
====================================================================================
836 
Device utilization summary:
837 
---------------------------
838 
 
839 
Selected Device : 6vlx75tff484-3
840 
 
841 
 
842 
Slice Logic Utilization:
843 
 Number of Slice Registers:             458  out of  93120     0%
844 
 Number of Slice LUTs:                 1234  out of  46560     2%
845 
    Number used as Logic:              1234  out of  46560     2%
846 
 
847 
Slice Logic Distribution:
848 
 Number of LUT Flip Flop pairs used:   1260
849 
   Number with an unused Flip Flop:     802  out of   1260    63%
850 
   Number with an unused LUT:            26  out of   1260     2%
851 
   Number of fully used LUT-FF pairs:   432  out of   1260    34%
852 
   Number of unique control sets:        44
853 
 
854 
IO Utilization:
855 
 Number of IOs:                          80
856 
 Number of bonded IOBs:                  79  out of    240    32%
857 
    IOB Flip Flops/Latches:              14
858 
 
859 
Specific Feature Utilization:
860 
 Number of Block RAM/FIFO:                3  out of    156     1%
861 
    Number using Block RAM only:          3
862 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
863 
 
864 
---------------------------
865 
 
866 
====================================================================================
867 
#                            SYNTHESIS DONE
868 
#####################################################################################
869 
 
870 
#####################################################################################
871 
#                            START SYNTHESIS (AREA optimized)
872 
#====================================================================================
873 
# spartan3 (xc3s400pq208), speedgrade: -4
874 
#====================================================================================
875 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
876 
#     12          10          1         0            0          0            0
877 
#====================================================================================
878 
Clock to Setup on destination clock dco_clk
879 
---------------+---------+---------+---------+---------+
880 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
881 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
882 
---------------+---------+---------+---------+---------+
883 
dco_clk        |   39.357|   24.190|         |    3.304|
884 
---------------+---------+---------+---------+---------+
885 
 
886 
====================================================================================
887 
Device utilization summary:
888 
---------------------------
889 
 
890 
Selected Device : 3s400pq208-4
891 
 
892 
 Number of Slices:                     1190  out of   3584    33%
893 
 Number of Slice Flip Flops:            594  out of   7168     8%
894 
 Number of 4 input LUTs:               2125  out of   7168    29%
895 
 Number of IOs:                          80
896 
 Number of bonded IOBs:                  80  out of    141    56%
897 
    IOB Flip Flops:                       8
898 
 Number of BRAMs:                         6  out of     16    37%
899 
 Number of GCLKs:                         1  out of      8    12%
900 
 
901 
---------------------------
902 
 
903 
====================================================================================
904 
#                            SYNTHESIS DONE
905 
#####################################################################################
906 
 
907 
#####################################################################################
908 
#                            START SYNTHESIS (AREA optimized)
909 
#====================================================================================
910 
# spartan3 (xc3s400pq208), speedgrade: -5
911 
#====================================================================================
912 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
913 
#     12          10          1         0            0          0            0
914 
#====================================================================================
915 
Clock to Setup on destination clock dco_clk
916 
---------------+---------+---------+---------+---------+
917 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
918 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
919 
---------------+---------+---------+---------+---------+
920 
dco_clk        |   33.462|   21.414|         |    1.369|
921 
---------------+---------+---------+---------+---------+
922 
 
923 
====================================================================================
924 
Device utilization summary:
925 
---------------------------
926 
 
927 
Selected Device : 3s400pq208-5
928 
 
929 
 Number of Slices:                     1191  out of   3584    33%
930 
 Number of Slice Flip Flops:            594  out of   7168     8%
931 
 Number of 4 input LUTs:               2127  out of   7168    29%
932 
 Number of IOs:                          80
933 
 Number of bonded IOBs:                  80  out of    141    56%
934 
    IOB Flip Flops:                       8
935 
 Number of BRAMs:                         6  out of     16    37%
936 
 Number of GCLKs:                         1  out of      8    12%
937 
 
938 
---------------------------
939 
 
940 
====================================================================================
941 
#                            SYNTHESIS DONE
942 
#####################################################################################
943 
 
944 
#####################################################################################
945 
#                            START SYNTHESIS (AREA optimized)
946 
#====================================================================================
947 
# spartan3e (xc3s500epq208), speedgrade: -4
948 
#====================================================================================
949 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
950 
#     12          10          1         0            0          0            0
951 
#====================================================================================
952 
Clock to Setup on destination clock dco_clk
953 
---------------+---------+---------+---------+---------+
954 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
955 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
956 
---------------+---------+---------+---------+---------+
957 
dco_clk        |   38.168|   23.835|         |    1.467|
958 
---------------+---------+---------+---------+---------+
959 
 
960 
====================================================================================
961 
Device utilization summary:
962 
---------------------------
963 
 
964 
Selected Device : 3s500epq208-4
965 
 
966 
 Number of Slices:                     1191  out of   4656    25%
967 
 Number of Slice Flip Flops:            594  out of   9312     6%
968 
 Number of 4 input LUTs:               2131  out of   9312    22%
969 
 Number of IOs:                          80
970 
 Number of bonded IOBs:                  80  out of    158    50%
971 
    IOB Flip Flops:                       8
972 
 Number of BRAMs:                         6  out of     20    30%
973 
 Number of GCLKs:                         1  out of     24     4%
974 
 
975 
---------------------------
976 
 
977 
====================================================================================
978 
#                            SYNTHESIS DONE
979 
#####################################################################################
980 
 
981 
#####################################################################################
982 
#                            START SYNTHESIS (AREA optimized)
983 
#====================================================================================
984 
# spartan3e (xc3s500epq208), speedgrade: -5
985 
#====================================================================================
986 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
987 
#     12          10          1         0            0          0            0
988 
#====================================================================================
989 
Clock to Setup on destination clock dco_clk
990 
---------------+---------+---------+---------+---------+
991 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
992 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
993 
---------------+---------+---------+---------+---------+
994 
dco_clk        |   33.433|   20.585|         |    1.175|
995 
---------------+---------+---------+---------+---------+
996 
 
997 
====================================================================================
998 
Device utilization summary:
999 
---------------------------
1000 
 
1001 
Selected Device : 3s500epq208-5
1002 
 
1003 
 Number of Slices:                     1191  out of   4656    25%
1004 
 Number of Slice Flip Flops:            594  out of   9312     6%
1005 
 Number of 4 input LUTs:               2131  out of   9312    22%
1006 
 Number of IOs:                          80
1007 
 Number of bonded IOBs:                  80  out of    158    50%
1008 
    IOB Flip Flops:                       8
1009 
 Number of BRAMs:                         6  out of     20    30%
1010 
 Number of GCLKs:                         1  out of     24     4%
1011 
 
1012 
---------------------------
1013 
 
1014 
====================================================================================
1015 
#                            SYNTHESIS DONE
1016 
#####################################################################################
1017 
 
1018 
#####################################################################################
1019 
#                            START SYNTHESIS (AREA optimized)
1020 
#====================================================================================
1021 
# spartan3a (xc3s700aft256), speedgrade: -4
1022 
#====================================================================================
1023 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1024 
#     12          10          1         0            0          0            0
1025 
#====================================================================================
1026 
Clock to Setup on destination clock dco_clk
1027 
---------------+---------+---------+---------+---------+
1028 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1029 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1030 
---------------+---------+---------+---------+---------+
1031 
dco_clk        |   41.728|   25.503|         |    2.123|
1032 
---------------+---------+---------+---------+---------+
1033 
 
1034 
====================================================================================
1035 
Device utilization summary:
1036 
---------------------------
1037 
 
1038 
Selected Device : 3s700aft256-4
1039 
 
1040 
 Number of Slices:                     1197  out of   5888    20%
1041 
 Number of Slice Flip Flops:            595  out of  11776     5%
1042 
 Number of 4 input LUTs:               2139  out of  11776    18%
1043 
 Number of IOs:                          80
1044 
 Number of bonded IOBs:                  80  out of    161    49%
1045 
    IOB Flip Flops:                       8
1046 
 Number of BRAMs:                         5  out of     20    25%
1047 
 Number of GCLKs:                         1  out of     24     4%
1048 
 
1049 
---------------------------
1050 
 
1051 
====================================================================================
1052 
#                            SYNTHESIS DONE
1053 
#####################################################################################
1054 
 
1055 
#####################################################################################
1056 
#                            START SYNTHESIS (AREA optimized)
1057 
#====================================================================================
1058 
# spartan3a (xc3s700aft256), speedgrade: -5
1059 
#====================================================================================
1060 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1061 
#     12          10          1         0            0          0            0
1062 
#====================================================================================
1063 
Clock to Setup on destination clock dco_clk
1064 
---------------+---------+---------+---------+---------+
1065 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1066 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1067 
---------------+---------+---------+---------+---------+
1068 
dco_clk        |   33.772|   22.023|         |    1.054|
1069 
---------------+---------+---------+---------+---------+
1070 
 
1071 
====================================================================================
1072 
Device utilization summary:
1073 
---------------------------
1074 
 
1075 
Selected Device : 3s700aft256-5
1076 
 
1077 
 Number of Slices:                     1195  out of   5888    20%
1078 
 Number of Slice Flip Flops:            595  out of  11776     5%
1079 
 Number of 4 input LUTs:               2138  out of  11776    18%
1080 
 Number of IOs:                          80
1081 
 Number of bonded IOBs:                  80  out of    161    49%
1082 
    IOB Flip Flops:                       8
1083 
 Number of BRAMs:                         5  out of     20    25%
1084 
 Number of GCLKs:                         1  out of     24     4%
1085 
 
1086 
---------------------------
1087 
 
1088 
====================================================================================
1089 
#                            SYNTHESIS DONE
1090 
#####################################################################################
1091 
 
1092 
#####################################################################################
1093 
#                            START SYNTHESIS (AREA optimized)
1094 
#====================================================================================
1095 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
1096 
#====================================================================================
1097 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1098 
#     12          10          1         0            0          0            0
1099 
#====================================================================================
1100 
Clock to Setup on destination clock dco_clk
1101 
---------------+---------+---------+---------+---------+
1102 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1103 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1104 
---------------+---------+---------+---------+---------+
1105 
dco_clk        |   42.462|   23.196|         |    1.448|
1106 
---------------+---------+---------+---------+---------+
1107 
 
1108 
====================================================================================
1109 
Device utilization summary:
1110 
---------------------------
1111 
 
1112 
Selected Device : 3sd1800acs484-4
1113 
 
1114 
 Number of Slices:                     1199  out of  16640     7%
1115 
 Number of Slice Flip Flops:            595  out of  33280     1%
1116 
 Number of 4 input LUTs:               2140  out of  33280     6%
1117 
 Number of IOs:                          80
1118 
 Number of bonded IOBs:                  80  out of    309    25%
1119 
    IOB Flip Flops:                       8
1120 
 Number of BRAMs:                         5  out of     84     5%
1121 
 Number of GCLKs:                         1  out of     24     4%
1122 
 
1123 
---------------------------
1124 
 
1125 
====================================================================================
1126 
#                            SYNTHESIS DONE
1127 
#####################################################################################
1128 
 
1129 
#####################################################################################
1130 
#                            START SYNTHESIS (AREA optimized)
1131 
#====================================================================================
1132 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
1133 
#====================================================================================
1134 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1135 
#     12          10          1         0            0          0            0
1136 
#====================================================================================
1137 
Clock to Setup on destination clock dco_clk
1138 
---------------+---------+---------+---------+---------+
1139 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1140 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1141 
---------------+---------+---------+---------+---------+
1142 
dco_clk        |   38.048|   20.537|         |    1.250|
1143 
---------------+---------+---------+---------+---------+
1144 
 
1145 
====================================================================================
1146 
Device utilization summary:
1147 
---------------------------
1148 
 
1149 
Selected Device : 3sd1800acs484-5
1150 
 
1151 
 Number of Slices:                     1197  out of  16640     7%
1152 
 Number of Slice Flip Flops:            595  out of  33280     1%
1153 
 Number of 4 input LUTs:               2136  out of  33280     6%
1154 
 Number of IOs:                          80
1155 
 Number of bonded IOBs:                  80  out of    309    25%
1156 
    IOB Flip Flops:                       8
1157 
 Number of BRAMs:                         5  out of     84     5%
1158 
 Number of GCLKs:                         1  out of     24     4%
1159 
 
1160 
---------------------------
1161 
 
1162 
====================================================================================
1163 
#                            SYNTHESIS DONE
1164 
#####################################################################################
1165 
 
1166 
#####################################################################################
1167 
#                            START SYNTHESIS (AREA optimized)
1168 
#====================================================================================
1169 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
1170 
#====================================================================================
1171 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1172 
#     12          10          1         0            0          0            0
1173 
#====================================================================================
1174 
Clock to Setup on destination clock dco_clk
1175 
---------------+---------+---------+---------+---------+
1176 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1177 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1178 
---------------+---------+---------+---------+---------+
1179 
dco_clk        |   29.658|   19.315|    5.207|    2.770|
1180 
---------------+---------+---------+---------+---------+
1181 
 
1182 
====================================================================================
1183 
Device utilization summary:
1184 
---------------------------
1185 
 
1186 
Selected Device : 6slx45tfgg484-2
1187 
 
1188 
 
1189 
Slice Logic Utilization:
1190 
 Number of Slice Registers:             595  out of  54576     1%
1191 
 Number of Slice LUTs:                 1620  out of  27288     5%
1192 
    Number used as Logic:              1620  out of  27288     5%
1193 
 
1194 
Slice Logic Distribution:
1195 
 Number of LUT Flip Flop pairs used:   1648
1196 
   Number with an unused Flip Flop:    1053  out of   1648    63%
1197 
   Number with an unused LUT:            28  out of   1648     1%
1198 
   Number of fully used LUT-FF pairs:   567  out of   1648    34%
1199 
   Number of unique control sets:        56
1200 
 
1201 
IO Utilization:
1202 
 Number of IOs:                          80
1203 
 Number of bonded IOBs:                  80  out of    296    27%
1204 
    IOB Flip Flops/Latches:               8
1205 
 
1206 
Specific Feature Utilization:
1207 
 Number of Block RAM/FIFO:                5  out of    348     1%
1208 
    Number using Block RAM only:          5
1209 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
1210 
 
1211 
---------------------------
1212 
 
1213 
====================================================================================
1214 
#                            SYNTHESIS DONE
1215 
#####################################################################################
1216 
 
1217 
#####################################################################################
1218 
#                            START SYNTHESIS (AREA optimized)
1219 
#====================================================================================
1220 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
1221 
#====================================================================================
1222 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1223 
#     12          10          1         0            0          0            0
1224 
#====================================================================================
1225 
Clock to Setup on destination clock dco_clk
1226 
---------------+---------+---------+---------+---------+
1227 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1228 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1229 
---------------+---------+---------+---------+---------+
1230 
dco_clk        |   24.045|   14.969|    3.841|    2.136|
1231 
---------------+---------+---------+---------+---------+
1232 
 
1233 
====================================================================================
1234 
Device utilization summary:
1235 
---------------------------
1236 
 
1237 
Selected Device : 6slx45tfgg484-3
1238 
 
1239 
 
1240 
Slice Logic Utilization:
1241 
 Number of Slice Registers:             595  out of  54576     1%
1242 
 Number of Slice LUTs:                 1603  out of  27288     5%
1243 
    Number used as Logic:              1603  out of  27288     5%
1244 
 
1245 
Slice Logic Distribution:
1246 
 Number of LUT Flip Flop pairs used:   1631
1247 
   Number with an unused Flip Flop:    1036  out of   1631    63%
1248 
   Number with an unused LUT:            28  out of   1631     1%
1249 
   Number of fully used LUT-FF pairs:   567  out of   1631    34%
1250 
   Number of unique control sets:        56
1251 
 
1252 
IO Utilization:
1253 
 Number of IOs:                          80
1254 
 Number of bonded IOBs:                  80  out of    296    27%
1255 
    IOB Flip Flops/Latches:               8
1256 
 
1257 
Specific Feature Utilization:
1258 
 Number of Block RAM/FIFO:                5  out of    348     1%
1259 
    Number using Block RAM only:          5
1260 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
1261 
 
1262 
---------------------------
1263 
 
1264 
====================================================================================
1265 
#                            SYNTHESIS DONE
1266 
#####################################################################################
1267 
 
1268 
#####################################################################################
1269 
#                            START SYNTHESIS (AREA optimized)
1270 
#====================================================================================
1271 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
1272 
#====================================================================================
1273 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1274 
#     12          10          1         0            0          0            0
1275 
#====================================================================================
1276 
Clock to Setup on destination clock dco_clk
1277 
---------------+---------+---------+---------+---------+
1278 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1279 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1280 
---------------+---------+---------+---------+---------+
1281 
dco_clk        |   20.652|   11.966|    3.681|    1.737|
1282 
---------------+---------+---------+---------+---------+
1283 
 
1284 
====================================================================================
1285 
Device utilization summary:
1286 
---------------------------
1287 
 
1288 
Selected Device : 6slx45tfgg484-4
1289 
 
1290 
 
1291 
Slice Logic Utilization:
1292 
 Number of Slice Registers:             595  out of  54576     1%
1293 
 Number of Slice LUTs:                 1603  out of  27288     5%
1294 
    Number used as Logic:              1603  out of  27288     5%
1295 
 
1296 
Slice Logic Distribution:
1297 
 Number of LUT Flip Flop pairs used:   1631
1298 
   Number with an unused Flip Flop:    1036  out of   1631    63%
1299 
   Number with an unused LUT:            28  out of   1631     1%
1300 
   Number of fully used LUT-FF pairs:   567  out of   1631    34%
1301 
   Number of unique control sets:        56
1302 
 
1303 
IO Utilization:
1304 
 Number of IOs:                          80
1305 
 Number of bonded IOBs:                  80  out of    296    27%
1306 
    IOB Flip Flops/Latches:               8
1307 
 
1308 
Specific Feature Utilization:
1309 
 Number of Block RAM/FIFO:                5  out of    348     1%
1310 
    Number using Block RAM only:          5
1311 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
1312 
 
1313 
---------------------------
1314 
 
1315 
====================================================================================
1316 
#                            SYNTHESIS DONE
1317 
#####################################################################################
1318 
 
1319 
#####################################################################################
1320 
#                            START SYNTHESIS (AREA optimized)
1321 
#====================================================================================
1322 
# virtex4 (xc4vlx25sf363), speedgrade: -10
1323 
#====================================================================================
1324 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1325 
#     12          10          1         0            0          0            0
1326 
#====================================================================================
1327 
Clock to Setup on destination clock dco_clk
1328 
---------------+---------+---------+---------+---------+
1329 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1330 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1331 
---------------+---------+---------+---------+---------+
1332 
dco_clk        |   24.165|   14.340|         |    1.208|
1333 
---------------+---------+---------+---------+---------+
1334 
 
1335 
====================================================================================
1336 
Device utilization summary:
1337 
---------------------------
1338 
 
1339 
Selected Device : 4vlx25sf363-10
1340 
 
1341 
 Number of Slices:                     1206  out of  10752    11%
1342 
 Number of Slice Flip Flops:            595  out of  21504     2%
1343 
 Number of 4 input LUTs:               2151  out of  21504    10%
1344 
 Number of IOs:                          80
1345 
 Number of bonded IOBs:                  80  out of    240    33%
1346 
    IOB Flip Flops:                       8
1347 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
1348 
    Number used as RAMB16s:               5
1349 
 Number of GCLKs:                         1  out of     32     3%
1350 
 
1351 
---------------------------
1352 
 
1353 
====================================================================================
1354 
#                            SYNTHESIS DONE
1355 
#####################################################################################
1356 
 
1357 
#####################################################################################
1358 
#                            START SYNTHESIS (AREA optimized)
1359 
#====================================================================================
1360 
# virtex4 (xc4vlx25sf363), speedgrade: -11
1361 
#====================================================================================
1362 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1363 
#     12          10          1         0            0          0            0
1364 
#====================================================================================
1365 
Clock to Setup on destination clock dco_clk
1366 
---------------+---------+---------+---------+---------+
1367 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1368 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1369 
---------------+---------+---------+---------+---------+
1370 
dco_clk        |   21.962|   12.473|         |    1.486|
1371 
---------------+---------+---------+---------+---------+
1372 
 
1373 
====================================================================================
1374 
Device utilization summary:
1375 
---------------------------
1376 
 
1377 
Selected Device : 4vlx25sf363-11
1378 
 
1379 
 Number of Slices:                     1206  out of  10752    11%
1380 
 Number of Slice Flip Flops:            595  out of  21504     2%
1381 
 Number of 4 input LUTs:               2152  out of  21504    10%
1382 
 Number of IOs:                          80
1383 
 Number of bonded IOBs:                  80  out of    240    33%
1384 
    IOB Flip Flops:                       8
1385 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
1386 
    Number used as RAMB16s:               5
1387 
 Number of GCLKs:                         1  out of     32     3%
1388 
 
1389 
---------------------------
1390 
 
1391 
====================================================================================
1392 
#                            SYNTHESIS DONE
1393 
#####################################################################################
1394 
 
1395 
#####################################################################################
1396 
#                            START SYNTHESIS (AREA optimized)
1397 
#====================================================================================
1398 
# virtex4 (xc4vlx25sf363), speedgrade: -12
1399 
#====================================================================================
1400 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1401 
#     12          10          1         0            0          0            0
1402 
#====================================================================================
1403 
Clock to Setup on destination clock dco_clk
1404 
---------------+---------+---------+---------+---------+
1405 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1406 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1407 
---------------+---------+---------+---------+---------+
1408 
dco_clk        |   18.351|   10.203|         |    0.914|
1409 
---------------+---------+---------+---------+---------+
1410 
 
1411 
====================================================================================
1412 
Device utilization summary:
1413 
---------------------------
1414 
 
1415 
Selected Device : 4vlx25sf363-12
1416 
 
1417 
 Number of Slices:                     1206  out of  10752    11%
1418 
 Number of Slice Flip Flops:            595  out of  21504     2%
1419 
 Number of 4 input LUTs:               2152  out of  21504    10%
1420 
 Number of IOs:                          80
1421 
 Number of bonded IOBs:                  80  out of    240    33%
1422 
    IOB Flip Flops:                       8
1423 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
1424 
    Number used as RAMB16s:               5
1425 
 Number of GCLKs:                         1  out of     32     3%
1426 
 
1427 
---------------------------
1428 
 
1429 
====================================================================================
1430 
#                            SYNTHESIS DONE
1431 
#####################################################################################
1432 
 
1433 
#####################################################################################
1434 
#                            START SYNTHESIS (AREA optimized)
1435 
#====================================================================================
1436 
# virtex5 (xc5vlx30ff324), speedgrade: -1
1437 
#====================================================================================
1438 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1439 
#     12          10          1         0            0          0            0
1440 
#====================================================================================
1441 
Clock to Setup on destination clock dco_clk
1442 
---------------+---------+---------+---------+---------+
1443 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1444 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1445 
---------------+---------+---------+---------+---------+
1446 
dco_clk        |   17.907|   10.911|         |    0.797|
1447 
---------------+---------+---------+---------+---------+
1448 
 
1449 
====================================================================================
1450 
Device utilization summary:
1451 
---------------------------
1452 
 
1453 
Selected Device : 5vlx30ff324-1
1454 
 
1455 
 
1456 
Slice Logic Utilization:
1457 
 Number of Slice Registers:             594  out of  19200     3%
1458 
 Number of Slice LUTs:                 1601  out of  19200     8%
1459 
    Number used as Logic:              1601  out of  19200     8%
1460 
 
1461 
Slice Logic Distribution:
1462 
 Number of LUT Flip Flop pairs used:   1625
1463 
   Number with an unused Flip Flop:    1031  out of   1625    63%
1464 
   Number with an unused LUT:            24  out of   1625     1%
1465 
   Number of fully used LUT-FF pairs:   570  out of   1625    35%
1466 
   Number of unique control sets:        55
1467 
 
1468 
IO Utilization:
1469 
 Number of IOs:                          80
1470 
 Number of bonded IOBs:                  80  out of    220    36%
1471 
    IOB Flip Flops/Latches:               8
1472 
 
1473 
Specific Feature Utilization:
1474 
 Number of Block RAM/FIFO:                3  out of     32     9%
1475 
    Number using Block RAM only:          3
1476 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1477 
 
1478 
---------------------------
1479 
 
1480 
====================================================================================
1481 
#                            SYNTHESIS DONE
1482 
#####################################################################################
1483 
 
1484 
#####################################################################################
1485 
#                            START SYNTHESIS (AREA optimized)
1486 
#====================================================================================
1487 
# virtex5 (xc5vlx30ff324), speedgrade: -2
1488 
#====================================================================================
1489 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1490 
#     12          10          1         0            0          0            0
1491 
#====================================================================================
1492 
Clock to Setup on destination clock dco_clk
1493 
---------------+---------+---------+---------+---------+
1494 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1495 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1496 
---------------+---------+---------+---------+---------+
1497 
dco_clk        |   15.682|   10.151|         |    0.677|
1498 
---------------+---------+---------+---------+---------+
1499 
 
1500 
====================================================================================
1501 
Device utilization summary:
1502 
---------------------------
1503 
 
1504 
Selected Device : 5vlx30ff324-2
1505 
 
1506 
 
1507 
Slice Logic Utilization:
1508 
 Number of Slice Registers:             594  out of  19200     3%
1509 
 Number of Slice LUTs:                 1601  out of  19200     8%
1510 
    Number used as Logic:              1601  out of  19200     8%
1511 
 
1512 
Slice Logic Distribution:
1513 
 Number of LUT Flip Flop pairs used:   1625
1514 
   Number with an unused Flip Flop:    1031  out of   1625    63%
1515 
   Number with an unused LUT:            24  out of   1625     1%
1516 
   Number of fully used LUT-FF pairs:   570  out of   1625    35%
1517 
   Number of unique control sets:        55
1518 
 
1519 
IO Utilization:
1520 
 Number of IOs:                          80
1521 
 Number of bonded IOBs:                  80  out of    220    36%
1522 
    IOB Flip Flops/Latches:               8
1523 
 
1524 
Specific Feature Utilization:
1525 
 Number of Block RAM/FIFO:                3  out of     32     9%
1526 
    Number using Block RAM only:          3
1527 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1528 
 
1529 
---------------------------
1530 
 
1531 
====================================================================================
1532 
#                            SYNTHESIS DONE
1533 
#####################################################################################
1534 
 
1535 
#####################################################################################
1536 
#                            START SYNTHESIS (AREA optimized)
1537 
#====================================================================================
1538 
# virtex5 (xc5vlx30ff324), speedgrade: -3
1539 
#====================================================================================
1540 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1541 
#     12          10          1         0            0          0            0
1542 
#====================================================================================
1543 
Clock to Setup on destination clock dco_clk
1544 
---------------+---------+---------+---------+---------+
1545 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1546 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1547 
---------------+---------+---------+---------+---------+
1548 
dco_clk        |   13.485|    7.831|         |    0.605|
1549 
---------------+---------+---------+---------+---------+
1550 
 
1551 
====================================================================================
1552 
Device utilization summary:
1553 
---------------------------
1554 
 
1555 
Selected Device : 5vlx30ff324-3
1556 
 
1557 
 
1558 
Slice Logic Utilization:
1559 
 Number of Slice Registers:             594  out of  19200     3%
1560 
 Number of Slice LUTs:                 1602  out of  19200     8%
1561 
    Number used as Logic:              1602  out of  19200     8%
1562 
 
1563 
Slice Logic Distribution:
1564 
 Number of LUT Flip Flop pairs used:   1626
1565 
   Number with an unused Flip Flop:    1032  out of   1626    63%
1566 
   Number with an unused LUT:            24  out of   1626     1%
1567 
   Number of fully used LUT-FF pairs:   570  out of   1626    35%
1568 
   Number of unique control sets:        55
1569 
 
1570 
IO Utilization:
1571 
 Number of IOs:                          80
1572 
 Number of bonded IOBs:                  80  out of    220    36%
1573 
    IOB Flip Flops/Latches:               8
1574 
 
1575 
Specific Feature Utilization:
1576 
 Number of Block RAM/FIFO:                3  out of     32     9%
1577 
    Number using Block RAM only:          3
1578 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1579 
 
1580 
---------------------------
1581 
 
1582 
====================================================================================
1583 
#                            SYNTHESIS DONE
1584 
#####################################################################################
1585 
 
1586 
#####################################################################################
1587 
#                            START SYNTHESIS (AREA optimized)
1588 
#====================================================================================
1589 
# virtex6 (xc6vlx75tff484), speedgrade: -1
1590 
#====================================================================================
1591 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1592 
#     12          10          1         0            0          0            0
1593 
#====================================================================================
1594 
Clock to Setup on destination clock dco_clk
1595 
---------------+---------+---------+---------+---------+
1596 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1597 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1598 
---------------+---------+---------+---------+---------+
1599 
dco_clk        |   14.710|    8.922|    2.179|    0.833|
1600 
---------------+---------+---------+---------+---------+
1601 
 
1602 
====================================================================================
1603 
Device utilization summary:
1604 
---------------------------
1605 
 
1606 
Selected Device : 6vlx75tff484-1
1607 
 
1608 
 
1609 
Slice Logic Utilization:
1610 
 Number of Slice Registers:             594  out of  93120     0%
1611 
 Number of Slice LUTs:                 1585  out of  46560     3%
1612 
    Number used as Logic:              1585  out of  46560     3%
1613 
 
1614 
Slice Logic Distribution:
1615 
 Number of LUT Flip Flop pairs used:   1612
1616 
   Number with an unused Flip Flop:    1018  out of   1612    63%
1617 
   Number with an unused LUT:            27  out of   1612     1%
1618 
   Number of fully used LUT-FF pairs:   567  out of   1612    35%
1619 
   Number of unique control sets:        55
1620 
 
1621 
IO Utilization:
1622 
 Number of IOs:                          80
1623 
 Number of bonded IOBs:                  80  out of    240    33%
1624 
    IOB Flip Flops/Latches:               8
1625 
 
1626 
Specific Feature Utilization:
1627 
 Number of Block RAM/FIFO:                3  out of    156     1%
1628 
    Number using Block RAM only:          3
1629 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1630 
 
1631 
---------------------------
1632 
 
1633 
====================================================================================
1634 
#                            SYNTHESIS DONE
1635 
#####################################################################################
1636 
 
1637 
#####################################################################################
1638 
#                            START SYNTHESIS (AREA optimized)
1639 
#====================================================================================
1640 
# virtex6 (xc6vlx75tff484), speedgrade: -2
1641 
#====================================================================================
1642 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1643 
#     12          10          1         0            0          0            0
1644 
#====================================================================================
1645 
Clock to Setup on destination clock dco_clk
1646 
---------------+---------+---------+---------+---------+
1647 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1648 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1649 
---------------+---------+---------+---------+---------+
1650 
dco_clk        |   13.667|    7.873|    2.748|    0.708|
1651 
---------------+---------+---------+---------+---------+
1652 
 
1653 
====================================================================================
1654 
Device utilization summary:
1655 
---------------------------
1656 
 
1657 
Selected Device : 6vlx75tff484-2
1658 
 
1659 
 
1660 
Slice Logic Utilization:
1661 
 Number of Slice Registers:             594  out of  93120     0%
1662 
 Number of Slice LUTs:                 1582  out of  46560     3%
1663 
    Number used as Logic:              1582  out of  46560     3%
1664 
 
1665 
Slice Logic Distribution:
1666 
 Number of LUT Flip Flop pairs used:   1609
1667 
   Number with an unused Flip Flop:    1015  out of   1609    63%
1668 
   Number with an unused LUT:            27  out of   1609     1%
1669 
   Number of fully used LUT-FF pairs:   567  out of   1609    35%
1670 
   Number of unique control sets:        55
1671 
 
1672 
IO Utilization:
1673 
 Number of IOs:                          80
1674 
 Number of bonded IOBs:                  80  out of    240    33%
1675 
    IOB Flip Flops/Latches:               8
1676 
 
1677 
Specific Feature Utilization:
1678 
 Number of Block RAM/FIFO:                3  out of    156     1%
1679 
    Number using Block RAM only:          3
1680 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1681 
 
1682 
---------------------------
1683 
 
1684 
====================================================================================
1685 
#                            SYNTHESIS DONE
1686 
#####################################################################################
1687 
 
1688 
#####################################################################################
1689 
#                            START SYNTHESIS (AREA optimized)
1690 
#====================================================================================
1691 
# virtex6 (xc6vlx75tff484), speedgrade: -3
1692 
#====================================================================================
1693 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1694 
#     12          10          1         0            0          0            0
1695 
#====================================================================================
1696 
Clock to Setup on destination clock dco_clk
1697 
---------------+---------+---------+---------+---------+
1698 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1699 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1700 
---------------+---------+---------+---------+---------+
1701 
dco_clk        |   11.845|    6.840|    1.931|    0.446|
1702 
---------------+---------+---------+---------+---------+
1703 
 
1704 
====================================================================================
1705 
Device utilization summary:
1706 
---------------------------
1707 
 
1708 
Selected Device : 6vlx75tff484-3
1709 
 
1710 
 
1711 
Slice Logic Utilization:
1712 
 Number of Slice Registers:             594  out of  93120     0%
1713 
 Number of Slice LUTs:                 1579  out of  46560     3%
1714 
    Number used as Logic:              1579  out of  46560     3%
1715 
 
1716 
Slice Logic Distribution:
1717 
 Number of LUT Flip Flop pairs used:   1606
1718 
   Number with an unused Flip Flop:    1012  out of   1606    63%
1719 
   Number with an unused LUT:            27  out of   1606     1%
1720 
   Number of fully used LUT-FF pairs:   567  out of   1606    35%
1721 
   Number of unique control sets:        55
1722 
 
1723 
IO Utilization:
1724 
 Number of IOs:                          80
1725 
 Number of bonded IOBs:                  80  out of    240    33%
1726 
    IOB Flip Flops/Latches:               8
1727 
 
1728 
Specific Feature Utilization:
1729 
 Number of Block RAM/FIFO:                3  out of    156     1%
1730 
    Number using Block RAM only:          3
1731 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
1732 
 
1733 
---------------------------
1734 
 
1735 
====================================================================================
1736 
#                            SYNTHESIS DONE
1737 
#####################################################################################
1738 
 
1739 
#####################################################################################
1740 
#                            START SYNTHESIS (AREA optimized)
1741 
#====================================================================================
1742 
# spartan3 (xc3s400pq208), speedgrade: -4
1743 
#====================================================================================
1744 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1745 
#     12          10          1         1            0          0            0
1746 
#====================================================================================
1747 
Clock to Setup on destination clock dco_clk
1748 
---------------+---------+---------+---------+---------+
1749 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1750 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1751 
---------------+---------+---------+---------+---------+
1752 
dco_clk        |   48.336|   23.967|         |    1.564|
1753 
---------------+---------+---------+---------+---------+
1754 
 
1755 
====================================================================================
1756 
Device utilization summary:
1757 
---------------------------
1758 
 
1759 
Selected Device : 3s400pq208-4
1760 
 
1761 
 Number of Slices:                     1211  out of   3584    33%
1762 
 Number of Slice Flip Flops:            637  out of   7168     8%
1763 
 Number of 4 input LUTs:               2165  out of   7168    30%
1764 
 Number of IOs:                          80
1765 
 Number of bonded IOBs:                  80  out of    141    56%
1766 
    IOB Flip Flops:                       8
1767 
 Number of BRAMs:                         6  out of     16    37%
1768 
 Number of GCLKs:                         1  out of      8    12%
1769 
 
1770 
---------------------------
1771 
 
1772 
====================================================================================
1773 
#                            SYNTHESIS DONE
1774 
#####################################################################################
1775 
 
1776 
#####################################################################################
1777 
#                            START SYNTHESIS (AREA optimized)
1778 
#====================================================================================
1779 
# spartan3 (xc3s400pq208), speedgrade: -5
1780 
#====================================================================================
1781 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1782 
#     12          10          1         1            0          0            0
1783 
#====================================================================================
1784 
Clock to Setup on destination clock dco_clk
1785 
---------------+---------+---------+---------+---------+
1786 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1787 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1788 
---------------+---------+---------+---------+---------+
1789 
dco_clk        |   43.503|   21.623|         |    1.361|
1790 
---------------+---------+---------+---------+---------+
1791 
 
1792 
====================================================================================
1793 
Device utilization summary:
1794 
---------------------------
1795 
 
1796 
Selected Device : 3s400pq208-5
1797 
 
1798 
 Number of Slices:                     1211  out of   3584    33%
1799 
 Number of Slice Flip Flops:            637  out of   7168     8%
1800 
 Number of 4 input LUTs:               2166  out of   7168    30%
1801 
 Number of IOs:                          80
1802 
 Number of bonded IOBs:                  80  out of    141    56%
1803 
    IOB Flip Flops:                       8
1804 
 Number of BRAMs:                         6  out of     16    37%
1805 
 Number of GCLKs:                         1  out of      8    12%
1806 
 
1807 
---------------------------
1808 
 
1809 
====================================================================================
1810 
#                            SYNTHESIS DONE
1811 
#####################################################################################
1812 
 
1813 
#####################################################################################
1814 
#                            START SYNTHESIS (AREA optimized)
1815 
#====================================================================================
1816 
# spartan3e (xc3s500epq208), speedgrade: -4
1817 
#====================================================================================
1818 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1819 
#     12          10          1         1            0          0            0
1820 
#====================================================================================
1821 
Clock to Setup on destination clock dco_clk
1822 
---------------+---------+---------+---------+---------+
1823 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1824 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1825 
---------------+---------+---------+---------+---------+
1826 
dco_clk        |   49.490|   24.741|         |    1.467|
1827 
---------------+---------+---------+---------+---------+
1828 
 
1829 
====================================================================================
1830 
Device utilization summary:
1831 
---------------------------
1832 
 
1833 
Selected Device : 3s500epq208-4
1834 
 
1835 
 Number of Slices:                     1220  out of   4656    26%
1836 
 Number of Slice Flip Flops:            637  out of   9312     6%
1837 
 Number of 4 input LUTs:               2185  out of   9312    23%
1838 
 Number of IOs:                          80
1839 
 Number of bonded IOBs:                  80  out of    158    50%
1840 
    IOB Flip Flops:                       8
1841 
 Number of BRAMs:                         6  out of     20    30%
1842 
 Number of GCLKs:                         1  out of     24     4%
1843 
 
1844 
---------------------------
1845 
 
1846 
====================================================================================
1847 
#                            SYNTHESIS DONE
1848 
#####################################################################################
1849 
 
1850 
#####################################################################################
1851 
#                            START SYNTHESIS (AREA optimized)
1852 
#====================================================================================
1853 
# spartan3e (xc3s500epq208), speedgrade: -5
1854 
#====================================================================================
1855 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1856 
#     12          10          1         1            0          0            0
1857 
#====================================================================================
1858 
Clock to Setup on destination clock dco_clk
1859 
---------------+---------+---------+---------+---------+
1860 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1861 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1862 
---------------+---------+---------+---------+---------+
1863 
dco_clk        |   41.827|   20.673|         |    1.276|
1864 
---------------+---------+---------+---------+---------+
1865 
 
1866 
====================================================================================
1867 
Device utilization summary:
1868 
---------------------------
1869 
 
1870 
Selected Device : 3s500epq208-5
1871 
 
1872 
 Number of Slices:                     1219  out of   4656    26%
1873 
 Number of Slice Flip Flops:            637  out of   9312     6%
1874 
 Number of 4 input LUTs:               2184  out of   9312    23%
1875 
 Number of IOs:                          80
1876 
 Number of bonded IOBs:                  80  out of    158    50%
1877 
    IOB Flip Flops:                       8
1878 
 Number of BRAMs:                         6  out of     20    30%
1879 
 Number of GCLKs:                         1  out of     24     4%
1880 
 
1881 
---------------------------
1882 
 
1883 
====================================================================================
1884 
#                            SYNTHESIS DONE
1885 
#####################################################################################
1886 
 
1887 
#####################################################################################
1888 
#                            START SYNTHESIS (AREA optimized)
1889 
#====================================================================================
1890 
# spartan3a (xc3s700aft256), speedgrade: -4
1891 
#====================================================================================
1892 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1893 
#     12          10          1         1            0          0            0
1894 
#====================================================================================
1895 
Clock to Setup on destination clock dco_clk
1896 
---------------+---------+---------+---------+---------+
1897 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1898 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1899 
---------------+---------+---------+---------+---------+
1900 
dco_clk        |   51.124|   25.734|         |    1.448|
1901 
---------------+---------+---------+---------+---------+
1902 
 
1903 
====================================================================================
1904 
Device utilization summary:
1905 
---------------------------
1906 
 
1907 
Selected Device : 3s700aft256-4
1908 
 
1909 
 Number of Slices:                     1225  out of   5888    20%
1910 
 Number of Slice Flip Flops:            638  out of  11776     5%
1911 
 Number of 4 input LUTs:               2191  out of  11776    18%
1912 
 Number of IOs:                          80
1913 
 Number of bonded IOBs:                  80  out of    161    49%
1914 
    IOB Flip Flops:                       8
1915 
 Number of BRAMs:                         5  out of     20    25%
1916 
 Number of GCLKs:                         1  out of     24     4%
1917 
 
1918 
---------------------------
1919 
 
1920 
====================================================================================
1921 
#                            SYNTHESIS DONE
1922 
#####################################################################################
1923 
 
1924 
#####################################################################################
1925 
#                            START SYNTHESIS (AREA optimized)
1926 
#====================================================================================
1927 
# spartan3a (xc3s700aft256), speedgrade: -5
1928 
#====================================================================================
1929 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1930 
#     12          10          1         1            0          0            0
1931 
#====================================================================================
1932 
Clock to Setup on destination clock dco_clk
1933 
---------------+---------+---------+---------+---------+
1934 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1935 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1936 
---------------+---------+---------+---------+---------+
1937 
dco_clk        |   39.403|   20.202|         |    1.192|
1938 
---------------+---------+---------+---------+---------+
1939 
 
1940 
====================================================================================
1941 
Device utilization summary:
1942 
---------------------------
1943 
 
1944 
Selected Device : 3s700aft256-5
1945 
 
1946 
 Number of Slices:                     1222  out of   5888    20%
1947 
 Number of Slice Flip Flops:            638  out of  11776     5%
1948 
 Number of 4 input LUTs:               2187  out of  11776    18%
1949 
 Number of IOs:                          80
1950 
 Number of bonded IOBs:                  80  out of    161    49%
1951 
    IOB Flip Flops:                       8
1952 
 Number of BRAMs:                         5  out of     20    25%
1953 
 Number of GCLKs:                         1  out of     24     4%
1954 
 
1955 
---------------------------
1956 
 
1957 
====================================================================================
1958 
#                            SYNTHESIS DONE
1959 
#####################################################################################
1960 
 
1961 
#####################################################################################
1962 
#                            START SYNTHESIS (AREA optimized)
1963 
#====================================================================================
1964 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
1965 
#====================================================================================
1966 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
1967 
#     12          10          1         1            0          0            0
1968 
#====================================================================================
1969 
Clock to Setup on destination clock dco_clk
1970 
---------------+---------+---------+---------+---------+
1971 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
1972 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
1973 
---------------+---------+---------+---------+---------+
1974 
dco_clk        |   47.780|   24.549|         |    1.448|
1975 
---------------+---------+---------+---------+---------+
1976 
 
1977 
====================================================================================
1978 
Device utilization summary:
1979 
---------------------------
1980 
 
1981 
Selected Device : 3sd1800acs484-4
1982 
 
1983 
 Number of Slices:                     1230  out of  16640     7%
1984 
 Number of Slice Flip Flops:            638  out of  33280     1%
1985 
 Number of 4 input LUTs:               2197  out of  33280     6%
1986 
 Number of IOs:                          80
1987 
 Number of bonded IOBs:                  80  out of    309    25%
1988 
    IOB Flip Flops:                       8
1989 
 Number of BRAMs:                         5  out of     84     5%
1990 
 Number of GCLKs:                         1  out of     24     4%
1991 
 
1992 
---------------------------
1993 
 
1994 
====================================================================================
1995 
#                            SYNTHESIS DONE
1996 
#####################################################################################
1997 
 
1998 
#####################################################################################
1999 
#                            START SYNTHESIS (AREA optimized)
2000 
#====================================================================================
2001 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
2002 
#====================================================================================
2003 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2004 
#     12          10          1         1            0          0            0
2005 
#====================================================================================
2006 
Clock to Setup on destination clock dco_clk
2007 
---------------+---------+---------+---------+---------+
2008 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2009 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2010 
---------------+---------+---------+---------+---------+
2011 
dco_clk        |   39.816|   19.647|         |    1.192|
2012 
---------------+---------+---------+---------+---------+
2013 
 
2014 
====================================================================================
2015 
Device utilization summary:
2016 
---------------------------
2017 
 
2018 
Selected Device : 3sd1800acs484-5
2019 
 
2020 
 Number of Slices:                     1229  out of  16640     7%
2021 
 Number of Slice Flip Flops:            638  out of  33280     1%
2022 
 Number of 4 input LUTs:               2196  out of  33280     6%
2023 
 Number of IOs:                          80
2024 
 Number of bonded IOBs:                  80  out of    309    25%
2025 
    IOB Flip Flops:                       8
2026 
 Number of BRAMs:                         5  out of     84     5%
2027 
 Number of GCLKs:                         1  out of     24     4%
2028 
 
2029 
---------------------------
2030 
 
2031 
====================================================================================
2032 
#                            SYNTHESIS DONE
2033 
#####################################################################################
2034 
 
2035 
#####################################################################################
2036 
#                            START SYNTHESIS (AREA optimized)
2037 
#====================================================================================
2038 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
2039 
#====================================================================================
2040 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2041 
#     12          10          1         1            0          0            0
2042 
#====================================================================================
2043 
Clock to Setup on destination clock dco_clk
2044 
---------------+---------+---------+---------+---------+
2045 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2046 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2047 
---------------+---------+---------+---------+---------+
2048 
dco_clk        |   38.405|   19.013|    4.808|    2.271|
2049 
---------------+---------+---------+---------+---------+
2050 
 
2051 
====================================================================================
2052 
Device utilization summary:
2053 
---------------------------
2054 
 
2055 
Selected Device : 6slx45tfgg484-2
2056 
 
2057 
 
2058 
Slice Logic Utilization:
2059 
 Number of Slice Registers:             638  out of  54576     1%
2060 
 Number of Slice LUTs:                 1705  out of  27288     6%
2061 
    Number used as Logic:              1705  out of  27288     6%
2062 
 
2063 
Slice Logic Distribution:
2064 
 Number of LUT Flip Flop pairs used:   1748
2065 
   Number with an unused Flip Flop:    1110  out of   1748    63%
2066 
   Number with an unused LUT:            43  out of   1748     2%
2067 
   Number of fully used LUT-FF pairs:   595  out of   1748    34%
2068 
   Number of unique control sets:        59
2069 
 
2070 
IO Utilization:
2071 
 Number of IOs:                          80
2072 
 Number of bonded IOBs:                  80  out of    296    27%
2073 
    IOB Flip Flops/Latches:               8
2074 
 
2075 
Specific Feature Utilization:
2076 
 Number of Block RAM/FIFO:                5  out of    348     1%
2077 
    Number using Block RAM only:          5
2078 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2079 
 
2080 
---------------------------
2081 
 
2082 
====================================================================================
2083 
#                            SYNTHESIS DONE
2084 
#####################################################################################
2085 
 
2086 
#####################################################################################
2087 
#                            START SYNTHESIS (AREA optimized)
2088 
#====================================================================================
2089 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
2090 
#====================================================================================
2091 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2092 
#     12          10          1         1            0          0            0
2093 
#====================================================================================
2094 
Clock to Setup on destination clock dco_clk
2095 
---------------+---------+---------+---------+---------+
2096 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2097 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2098 
---------------+---------+---------+---------+---------+
2099 
dco_clk        |   28.140|   15.305|    3.191|    2.136|
2100 
---------------+---------+---------+---------+---------+
2101 
 
2102 
====================================================================================
2103 
Device utilization summary:
2104 
---------------------------
2105 
 
2106 
Selected Device : 6slx45tfgg484-3
2107 
 
2108 
 
2109 
Slice Logic Utilization:
2110 
 Number of Slice Registers:             638  out of  54576     1%
2111 
 Number of Slice LUTs:                 1685  out of  27288     6%
2112 
    Number used as Logic:              1685  out of  27288     6%
2113 
 
2114 
Slice Logic Distribution:
2115 
 Number of LUT Flip Flop pairs used:   1728
2116 
   Number with an unused Flip Flop:    1090  out of   1728    63%
2117 
   Number with an unused LUT:            43  out of   1728     2%
2118 
   Number of fully used LUT-FF pairs:   595  out of   1728    34%
2119 
   Number of unique control sets:        59
2120 
 
2121 
IO Utilization:
2122 
 Number of IOs:                          80
2123 
 Number of bonded IOBs:                  80  out of    296    27%
2124 
    IOB Flip Flops/Latches:               8
2125 
 
2126 
Specific Feature Utilization:
2127 
 Number of Block RAM/FIFO:                5  out of    348     1%
2128 
    Number using Block RAM only:          5
2129 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2130 
 
2131 
---------------------------
2132 
 
2133 
====================================================================================
2134 
#                            SYNTHESIS DONE
2135 
#####################################################################################
2136 
 
2137 
#####################################################################################
2138 
#                            START SYNTHESIS (AREA optimized)
2139 
#====================================================================================
2140 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
2141 
#====================================================================================
2142 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2143 
#     12          10          1         1            0          0            0
2144 
#====================================================================================
2145 
Clock to Setup on destination clock dco_clk
2146 
---------------+---------+---------+---------+---------+
2147 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2148 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2149 
---------------+---------+---------+---------+---------+
2150 
dco_clk        |   24.628|   12.205|    3.755|    1.850|
2151 
---------------+---------+---------+---------+---------+
2152 
 
2153 
====================================================================================
2154 
Device utilization summary:
2155 
---------------------------
2156 
 
2157 
Selected Device : 6slx45tfgg484-4
2158 
 
2159 
 
2160 
Slice Logic Utilization:
2161 
 Number of Slice Registers:             638  out of  54576     1%
2162 
 Number of Slice LUTs:                 1681  out of  27288     6%
2163 
    Number used as Logic:              1681  out of  27288     6%
2164 
 
2165 
Slice Logic Distribution:
2166 
 Number of LUT Flip Flop pairs used:   1724
2167 
   Number with an unused Flip Flop:    1086  out of   1724    62%
2168 
   Number with an unused LUT:            43  out of   1724     2%
2169 
   Number of fully used LUT-FF pairs:   595  out of   1724    34%
2170 
   Number of unique control sets:        59
2171 
 
2172 
IO Utilization:
2173 
 Number of IOs:                          80
2174 
 Number of bonded IOBs:                  80  out of    296    27%
2175 
    IOB Flip Flops/Latches:               8
2176 
 
2177 
Specific Feature Utilization:
2178 
 Number of Block RAM/FIFO:                5  out of    348     1%
2179 
    Number using Block RAM only:          5
2180 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2181 
 
2182 
---------------------------
2183 
 
2184 
====================================================================================
2185 
#                            SYNTHESIS DONE
2186 
#####################################################################################
2187 
 
2188 
#####################################################################################
2189 
#                            START SYNTHESIS (AREA optimized)
2190 
#====================================================================================
2191 
# virtex4 (xc4vlx25sf363), speedgrade: -10
2192 
#====================================================================================
2193 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2194 
#     12          10          1         1            0          0            0
2195 
#====================================================================================
2196 
Clock to Setup on destination clock dco_clk
2197 
---------------+---------+---------+---------+---------+
2198 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2199 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2200 
---------------+---------+---------+---------+---------+
2201 
dco_clk        |   31.882|   16.025|         |    0.943|
2202 
---------------+---------+---------+---------+---------+
2203 
 
2204 
====================================================================================
2205 
Device utilization summary:
2206 
---------------------------
2207 
 
2208 
Selected Device : 4vlx25sf363-10
2209 
 
2210 
 Number of Slices:                     1229  out of  10752    11%
2211 
 Number of Slice Flip Flops:            638  out of  21504     2%
2212 
 Number of 4 input LUTs:               2200  out of  21504    10%
2213 
 Number of IOs:                          80
2214 
 Number of bonded IOBs:                  80  out of    240    33%
2215 
    IOB Flip Flops:                       8
2216 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
2217 
    Number used as RAMB16s:               5
2218 
 Number of GCLKs:                         1  out of     32     3%
2219 
 
2220 
---------------------------
2221 
 
2222 
====================================================================================
2223 
#                            SYNTHESIS DONE
2224 
#####################################################################################
2225 
 
2226 
#####################################################################################
2227 
#                            START SYNTHESIS (AREA optimized)
2228 
#====================================================================================
2229 
# virtex4 (xc4vlx25sf363), speedgrade: -11
2230 
#====================================================================================
2231 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2232 
#     12          10          1         1            0          0            0
2233 
#====================================================================================
2234 
Clock to Setup on destination clock dco_clk
2235 
---------------+---------+---------+---------+---------+
2236 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2237 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2238 
---------------+---------+---------+---------+---------+
2239 
dco_clk        |   28.466|   14.086|         |    0.793|
2240 
---------------+---------+---------+---------+---------+
2241 
 
2242 
====================================================================================
2243 
Device utilization summary:
2244 
---------------------------
2245 
 
2246 
Selected Device : 4vlx25sf363-11
2247 
 
2248 
 Number of Slices:                     1230  out of  10752    11%
2249 
 Number of Slice Flip Flops:            638  out of  21504     2%
2250 
 Number of 4 input LUTs:               2202  out of  21504    10%
2251 
 Number of IOs:                          80
2252 
 Number of bonded IOBs:                  80  out of    240    33%
2253 
    IOB Flip Flops:                       8
2254 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
2255 
    Number used as RAMB16s:               5
2256 
 Number of GCLKs:                         1  out of     32     3%
2257 
 
2258 
---------------------------
2259 
 
2260 
====================================================================================
2261 
#                            SYNTHESIS DONE
2262 
#####################################################################################
2263 
 
2264 
#####################################################################################
2265 
#                            START SYNTHESIS (AREA optimized)
2266 
#====================================================================================
2267 
# virtex4 (xc4vlx25sf363), speedgrade: -12
2268 
#====================================================================================
2269 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2270 
#     12          10          1         1            0          0            0
2271 
#====================================================================================
2272 
Clock to Setup on destination clock dco_clk
2273 
---------------+---------+---------+---------+---------+
2274 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2275 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2276 
---------------+---------+---------+---------+---------+
2277 
dco_clk        |   24.889|   12.458|         |    0.706|
2278 
---------------+---------+---------+---------+---------+
2279 
 
2280 
====================================================================================
2281 
Device utilization summary:
2282 
---------------------------
2283 
 
2284 
Selected Device : 4vlx25sf363-12
2285 
 
2286 
 Number of Slices:                     1229  out of  10752    11%
2287 
 Number of Slice Flip Flops:            638  out of  21504     2%
2288 
 Number of 4 input LUTs:               2199  out of  21504    10%
2289 
 Number of IOs:                          80
2290 
 Number of bonded IOBs:                  80  out of    240    33%
2291 
    IOB Flip Flops:                       8
2292 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
2293 
    Number used as RAMB16s:               5
2294 
 Number of GCLKs:                         1  out of     32     3%
2295 
 
2296 
---------------------------
2297 
 
2298 
====================================================================================
2299 
#                            SYNTHESIS DONE
2300 
#####################################################################################
2301 
 
2302 
#####################################################################################
2303 
#                            START SYNTHESIS (AREA optimized)
2304 
#====================================================================================
2305 
# virtex5 (xc5vlx30ff324), speedgrade: -1
2306 
#====================================================================================
2307 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2308 
#     12          10          1         1            0          0            0
2309 
#====================================================================================
2310 
Clock to Setup on destination clock dco_clk
2311 
---------------+---------+---------+---------+---------+
2312 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2313 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2314 
---------------+---------+---------+---------+---------+
2315 
dco_clk        |   19.493|    9.719|         |    1.337|
2316 
---------------+---------+---------+---------+---------+
2317 
 
2318 
====================================================================================
2319 
Device utilization summary:
2320 
---------------------------
2321 
 
2322 
Selected Device : 5vlx30ff324-1
2323 
 
2324 
 
2325 
Slice Logic Utilization:
2326 
 Number of Slice Registers:             637  out of  19200     3%
2327 
 Number of Slice LUTs:                 1691  out of  19200     8%
2328 
    Number used as Logic:              1691  out of  19200     8%
2329 
 
2330 
Slice Logic Distribution:
2331 
 Number of LUT Flip Flop pairs used:   1727
2332 
   Number with an unused Flip Flop:    1090  out of   1727    63%
2333 
   Number with an unused LUT:            36  out of   1727     2%
2334 
   Number of fully used LUT-FF pairs:   601  out of   1727    34%
2335 
   Number of unique control sets:        58
2336 
 
2337 
IO Utilization:
2338 
 Number of IOs:                          80
2339 
 Number of bonded IOBs:                  80  out of    220    36%
2340 
    IOB Flip Flops/Latches:               8
2341 
 
2342 
Specific Feature Utilization:
2343 
 Number of Block RAM/FIFO:                3  out of     32     9%
2344 
    Number using Block RAM only:          3
2345 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2346 
 
2347 
---------------------------
2348 
 
2349 
====================================================================================
2350 
#                            SYNTHESIS DONE
2351 
#####################################################################################
2352 
 
2353 
#####################################################################################
2354 
#                            START SYNTHESIS (AREA optimized)
2355 
#====================================================================================
2356 
# virtex5 (xc5vlx30ff324), speedgrade: -2
2357 
#====================================================================================
2358 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2359 
#     12          10          1         1            0          0            0
2360 
#====================================================================================
2361 
Clock to Setup on destination clock dco_clk
2362 
---------------+---------+---------+---------+---------+
2363 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2364 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2365 
---------------+---------+---------+---------+---------+
2366 
dco_clk        |   16.563|    8.229|         |    0.825|
2367 
---------------+---------+---------+---------+---------+
2368 
 
2369 
====================================================================================
2370 
Device utilization summary:
2371 
---------------------------
2372 
 
2373 
Selected Device : 5vlx30ff324-2
2374 
 
2375 
 
2376 
Slice Logic Utilization:
2377 
 Number of Slice Registers:             637  out of  19200     3%
2378 
 Number of Slice LUTs:                 1692  out of  19200     8%
2379 
    Number used as Logic:              1692  out of  19200     8%
2380 
 
2381 
Slice Logic Distribution:
2382 
 Number of LUT Flip Flop pairs used:   1728
2383 
   Number with an unused Flip Flop:    1091  out of   1728    63%
2384 
   Number with an unused LUT:            36  out of   1728     2%
2385 
   Number of fully used LUT-FF pairs:   601  out of   1728    34%
2386 
   Number of unique control sets:        58
2387 
 
2388 
IO Utilization:
2389 
 Number of IOs:                          80
2390 
 Number of bonded IOBs:                  80  out of    220    36%
2391 
    IOB Flip Flops/Latches:               8
2392 
 
2393 
Specific Feature Utilization:
2394 
 Number of Block RAM/FIFO:                3  out of     32     9%
2395 
    Number using Block RAM only:          3
2396 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2397 
 
2398 
---------------------------
2399 
 
2400 
====================================================================================
2401 
#                            SYNTHESIS DONE
2402 
#####################################################################################
2403 
 
2404 
#####################################################################################
2405 
#                            START SYNTHESIS (AREA optimized)
2406 
#====================================================================================
2407 
# virtex5 (xc5vlx30ff324), speedgrade: -3
2408 
#====================================================================================
2409 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2410 
#     12          10          1         1            0          0            0
2411 
#====================================================================================
2412 
Clock to Setup on destination clock dco_clk
2413 
---------------+---------+---------+---------+---------+
2414 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2415 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2416 
---------------+---------+---------+---------+---------+
2417 
dco_clk        |   15.059|    7.517|         |    0.971|
2418 
---------------+---------+---------+---------+---------+
2419 
 
2420 
====================================================================================
2421 
Device utilization summary:
2422 
---------------------------
2423 
 
2424 
Selected Device : 5vlx30ff324-3
2425 
 
2426 
 
2427 
Slice Logic Utilization:
2428 
 Number of Slice Registers:             637  out of  19200     3%
2429 
 Number of Slice LUTs:                 1692  out of  19200     8%
2430 
    Number used as Logic:              1692  out of  19200     8%
2431 
 
2432 
Slice Logic Distribution:
2433 
 Number of LUT Flip Flop pairs used:   1728
2434 
   Number with an unused Flip Flop:    1091  out of   1728    63%
2435 
   Number with an unused LUT:            36  out of   1728     2%
2436 
   Number of fully used LUT-FF pairs:   601  out of   1728    34%
2437 
   Number of unique control sets:        58
2438 
 
2439 
IO Utilization:
2440 
 Number of IOs:                          80
2441 
 Number of bonded IOBs:                  80  out of    220    36%
2442 
    IOB Flip Flops/Latches:               8
2443 
 
2444 
Specific Feature Utilization:
2445 
 Number of Block RAM/FIFO:                3  out of     32     9%
2446 
    Number using Block RAM only:          3
2447 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2448 
 
2449 
---------------------------
2450 
 
2451 
====================================================================================
2452 
#                            SYNTHESIS DONE
2453 
#####################################################################################
2454 
 
2455 
#####################################################################################
2456 
#                            START SYNTHESIS (AREA optimized)
2457 
#====================================================================================
2458 
# virtex6 (xc6vlx75tff484), speedgrade: -1
2459 
#====================================================================================
2460 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2461 
#     12          10          1         1            0          0            0
2462 
#====================================================================================
2463 
Clock to Setup on destination clock dco_clk
2464 
---------------+---------+---------+---------+---------+
2465 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2466 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2467 
---------------+---------+---------+---------+---------+
2468 
dco_clk        |   18.087|    9.148|    2.687|    0.849|
2469 
---------------+---------+---------+---------+---------+
2470 
 
2471 
====================================================================================
2472 
Device utilization summary:
2473 
---------------------------
2474 
 
2475 
Selected Device : 6vlx75tff484-1
2476 
 
2477 
 
2478 
Slice Logic Utilization:
2479 
 Number of Slice Registers:             637  out of  93120     0%
2480 
 Number of Slice LUTs:                 1673  out of  46560     3%
2481 
    Number used as Logic:              1673  out of  46560     3%
2482 
 
2483 
Slice Logic Distribution:
2484 
 Number of LUT Flip Flop pairs used:   1715
2485 
   Number with an unused Flip Flop:    1078  out of   1715    62%
2486 
   Number with an unused LUT:            42  out of   1715     2%
2487 
   Number of fully used LUT-FF pairs:   595  out of   1715    34%
2488 
   Number of unique control sets:        58
2489 
 
2490 
IO Utilization:
2491 
 Number of IOs:                          80
2492 
 Number of bonded IOBs:                  80  out of    240    33%
2493 
    IOB Flip Flops/Latches:               8
2494 
 
2495 
Specific Feature Utilization:
2496 
 Number of Block RAM/FIFO:                3  out of    156     1%
2497 
    Number using Block RAM only:          3
2498 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2499 
 
2500 
---------------------------
2501 
 
2502 
====================================================================================
2503 
#                            SYNTHESIS DONE
2504 
#####################################################################################
2505 
 
2506 
#####################################################################################
2507 
#                            START SYNTHESIS (AREA optimized)
2508 
#====================================================================================
2509 
# virtex6 (xc6vlx75tff484), speedgrade: -2
2510 
#====================================================================================
2511 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2512 
#     12          10          1         1            0          0            0
2513 
#====================================================================================
2514 
Clock to Setup on destination clock dco_clk
2515 
---------------+---------+---------+---------+---------+
2516 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2517 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2518 
---------------+---------+---------+---------+---------+
2519 
dco_clk        |   15.126|    7.696|    2.168|    0.568|
2520 
---------------+---------+---------+---------+---------+
2521 
 
2522 
====================================================================================
2523 
Device utilization summary:
2524 
---------------------------
2525 
 
2526 
Selected Device : 6vlx75tff484-2
2527 
 
2528 
 
2529 
Slice Logic Utilization:
2530 
 Number of Slice Registers:             637  out of  93120     0%
2531 
 Number of Slice LUTs:                 1668  out of  46560     3%
2532 
    Number used as Logic:              1668  out of  46560     3%
2533 
 
2534 
Slice Logic Distribution:
2535 
 Number of LUT Flip Flop pairs used:   1710
2536 
   Number with an unused Flip Flop:    1073  out of   1710    62%
2537 
   Number with an unused LUT:            42  out of   1710     2%
2538 
   Number of fully used LUT-FF pairs:   595  out of   1710    34%
2539 
   Number of unique control sets:        58
2540 
 
2541 
IO Utilization:
2542 
 Number of IOs:                          80
2543 
 Number of bonded IOBs:                  80  out of    240    33%
2544 
    IOB Flip Flops/Latches:               8
2545 
 
2546 
Specific Feature Utilization:
2547 
 Number of Block RAM/FIFO:                3  out of    156     1%
2548 
    Number using Block RAM only:          3
2549 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2550 
 
2551 
---------------------------
2552 
 
2553 
====================================================================================
2554 
#                            SYNTHESIS DONE
2555 
#####################################################################################
2556 
 
2557 
#####################################################################################
2558 
#                            START SYNTHESIS (AREA optimized)
2559 
#====================================================================================
2560 
# virtex6 (xc6vlx75tff484), speedgrade: -3
2561 
#====================================================================================
2562 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2563 
#     12          10          1         1            0          0            0
2564 
#====================================================================================
2565 
Clock to Setup on destination clock dco_clk
2566 
---------------+---------+---------+---------+---------+
2567 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2568 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2569 
---------------+---------+---------+---------+---------+
2570 
dco_clk        |   14.814|    7.705|    1.615|    0.540|
2571 
---------------+---------+---------+---------+---------+
2572 
 
2573 
====================================================================================
2574 
Device utilization summary:
2575 
---------------------------
2576 
 
2577 
Selected Device : 6vlx75tff484-3
2578 
 
2579 
 
2580 
Slice Logic Utilization:
2581 
 Number of Slice Registers:             637  out of  93120     0%
2582 
 Number of Slice LUTs:                 1668  out of  46560     3%
2583 
    Number used as Logic:              1668  out of  46560     3%
2584 
 
2585 
Slice Logic Distribution:
2586 
 Number of LUT Flip Flop pairs used:   1710
2587 
   Number with an unused Flip Flop:    1073  out of   1710    62%
2588 
   Number with an unused LUT:            42  out of   1710     2%
2589 
   Number of fully used LUT-FF pairs:   595  out of   1710    34%
2590 
   Number of unique control sets:        58
2591 
 
2592 
IO Utilization:
2593 
 Number of IOs:                          80
2594 
 Number of bonded IOBs:                  80  out of    240    33%
2595 
    IOB Flip Flops/Latches:               8
2596 
 
2597 
Specific Feature Utilization:
2598 
 Number of Block RAM/FIFO:                3  out of    156     1%
2599 
    Number using Block RAM only:          3
2600 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
2601 
 
2602 
---------------------------
2603 
 
2604 
====================================================================================
2605 
#                            SYNTHESIS DONE
2606 
#####################################################################################
2607 
 
2608 
#####################################################################################
2609 
#                            START SYNTHESIS (AREA optimized)
2610 
#====================================================================================
2611 
# spartan3 (xc3s400pq208), speedgrade: -4
2612 
#====================================================================================
2613 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2614 
#     12          10          1         1            1          0            0
2615 
#====================================================================================
2616 
Clock to Setup on destination clock dco_clk
2617 
---------------+---------+---------+---------+---------+
2618 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2619 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2620 
---------------+---------+---------+---------+---------+
2621 
dco_clk        |   49.666|   23.480|         |    1.564|
2622 
---------------+---------+---------+---------+---------+
2623 
 
2624 
====================================================================================
2625 
Device utilization summary:
2626 
---------------------------
2627 
 
2628 
Selected Device : 3s400pq208-4
2629 
 
2630 
 Number of Slices:                     1268  out of   3584    35%
2631 
 Number of Slice Flip Flops:            679  out of   7168     9%
2632 
 Number of 4 input LUTs:               2272  out of   7168    31%
2633 
 Number of IOs:                          80
2634 
 Number of bonded IOBs:                  80  out of    141    56%
2635 
    IOB Flip Flops:                       8
2636 
 Number of BRAMs:                         6  out of     16    37%
2637 
 Number of GCLKs:                         1  out of      8    12%
2638 
 
2639 
---------------------------
2640 
 
2641 
====================================================================================
2642 
#                            SYNTHESIS DONE
2643 
#####################################################################################
2644 
 
2645 
#####################################################################################
2646 
#                            START SYNTHESIS (AREA optimized)
2647 
#====================================================================================
2648 
# spartan3 (xc3s400pq208), speedgrade: -5
2649 
#====================================================================================
2650 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2651 
#     12          10          1         1            1          0            0
2652 
#====================================================================================
2653 
Clock to Setup on destination clock dco_clk
2654 
---------------+---------+---------+---------+---------+
2655 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2656 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2657 
---------------+---------+---------+---------+---------+
2658 
dco_clk        |   44.646|   22.025|         |    1.369|
2659 
---------------+---------+---------+---------+---------+
2660 
 
2661 
====================================================================================
2662 
Device utilization summary:
2663 
---------------------------
2664 
 
2665 
Selected Device : 3s400pq208-5
2666 
 
2667 
 Number of Slices:                     1271  out of   3584    35%
2668 
 Number of Slice Flip Flops:            679  out of   7168     9%
2669 
 Number of 4 input LUTs:               2276  out of   7168    31%
2670 
 Number of IOs:                          80
2671 
 Number of bonded IOBs:                  80  out of    141    56%
2672 
    IOB Flip Flops:                       8
2673 
 Number of BRAMs:                         6  out of     16    37%
2674 
 Number of GCLKs:                         1  out of      8    12%
2675 
 
2676 
---------------------------
2677 
 
2678 
====================================================================================
2679 
#                            SYNTHESIS DONE
2680 
#####################################################################################
2681 
 
2682 
#####################################################################################
2683 
#                            START SYNTHESIS (AREA optimized)
2684 
#====================================================================================
2685 
# spartan3e (xc3s500epq208), speedgrade: -4
2686 
#====================================================================================
2687 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2688 
#     12          10          1         1            1          0            0
2689 
#====================================================================================
2690 
Clock to Setup on destination clock dco_clk
2691 
---------------+---------+---------+---------+---------+
2692 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2693 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2694 
---------------+---------+---------+---------+---------+
2695 
dco_clk        |   48.181|   24.402|         |    1.467|
2696 
---------------+---------+---------+---------+---------+
2697 
 
2698 
====================================================================================
2699 
Device utilization summary:
2700 
---------------------------
2701 
 
2702 
Selected Device : 3s500epq208-4
2703 
 
2704 
 Number of Slices:                     1285  out of   4656    27%
2705 
 Number of Slice Flip Flops:            679  out of   9312     7%
2706 
 Number of 4 input LUTs:               2298  out of   9312    24%
2707 
 Number of IOs:                          80
2708 
 Number of bonded IOBs:                  80  out of    158    50%
2709 
    IOB Flip Flops:                       8
2710 
 Number of BRAMs:                         6  out of     20    30%
2711 
 Number of GCLKs:                         1  out of     24     4%
2712 
 
2713 
---------------------------
2714 
 
2715 
====================================================================================
2716 
#                            SYNTHESIS DONE
2717 
#####################################################################################
2718 
 
2719 
#####################################################################################
2720 
#                            START SYNTHESIS (AREA optimized)
2721 
#====================================================================================
2722 
# spartan3e (xc3s500epq208), speedgrade: -5
2723 
#====================================================================================
2724 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2725 
#     12          10          1         1            1          0            0
2726 
#====================================================================================
2727 
Clock to Setup on destination clock dco_clk
2728 
---------------+---------+---------+---------+---------+
2729 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2730 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2731 
---------------+---------+---------+---------+---------+
2732 
dco_clk        |   41.477|   20.632|         |    1.175|
2733 
---------------+---------+---------+---------+---------+
2734 
 
2735 
====================================================================================
2736 
Device utilization summary:
2737 
---------------------------
2738 
 
2739 
Selected Device : 3s500epq208-5
2740 
 
2741 
 Number of Slices:                     1283  out of   4656    27%
2742 
 Number of Slice Flip Flops:            679  out of   9312     7%
2743 
 Number of 4 input LUTs:               2295  out of   9312    24%
2744 
 Number of IOs:                          80
2745 
 Number of bonded IOBs:                  80  out of    158    50%
2746 
    IOB Flip Flops:                       8
2747 
 Number of BRAMs:                         6  out of     20    30%
2748 
 Number of GCLKs:                         1  out of     24     4%
2749 
 
2750 
---------------------------
2751 
 
2752 
====================================================================================
2753 
#                            SYNTHESIS DONE
2754 
#####################################################################################
2755 
 
2756 
#####################################################################################
2757 
#                            START SYNTHESIS (AREA optimized)
2758 
#====================================================================================
2759 
# spartan3a (xc3s700aft256), speedgrade: -4
2760 
#====================================================================================
2761 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2762 
#     12          10          1         1            1          0            0
2763 
#====================================================================================
2764 
Clock to Setup on destination clock dco_clk
2765 
---------------+---------+---------+---------+---------+
2766 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2767 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2768 
---------------+---------+---------+---------+---------+
2769 
dco_clk        |   49.676|   24.544|         |    1.954|
2770 
---------------+---------+---------+---------+---------+
2771 
 
2772 
====================================================================================
2773 
Device utilization summary:
2774 
---------------------------
2775 
 
2776 
Selected Device : 3s700aft256-4
2777 
 
2778 
 Number of Slices:                     1290  out of   5888    21%
2779 
 Number of Slice Flip Flops:            680  out of  11776     5%
2780 
 Number of 4 input LUTs:               2304  out of  11776    19%
2781 
 Number of IOs:                          80
2782 
 Number of bonded IOBs:                  80  out of    161    49%
2783 
    IOB Flip Flops:                       8
2784 
 Number of BRAMs:                         5  out of     20    25%
2785 
 Number of GCLKs:                         1  out of     24     4%
2786 
 
2787 
---------------------------
2788 
 
2789 
====================================================================================
2790 
#                            SYNTHESIS DONE
2791 
#####################################################################################
2792 
 
2793 
#####################################################################################
2794 
#                            START SYNTHESIS (AREA optimized)
2795 
#====================================================================================
2796 
# spartan3a (xc3s700aft256), speedgrade: -5
2797 
#====================================================================================
2798 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2799 
#     12          10          1         1            1          0            0
2800 
#====================================================================================
2801 
Clock to Setup on destination clock dco_clk
2802 
---------------+---------+---------+---------+---------+
2803 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2804 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2805 
---------------+---------+---------+---------+---------+
2806 
dco_clk        |   44.364|   21.845|         |    1.054|
2807 
---------------+---------+---------+---------+---------+
2808 
 
2809 
====================================================================================
2810 
Device utilization summary:
2811 
---------------------------
2812 
 
2813 
Selected Device : 3s700aft256-5
2814 
 
2815 
 Number of Slices:                     1289  out of   5888    21%
2816 
 Number of Slice Flip Flops:            680  out of  11776     5%
2817 
 Number of 4 input LUTs:               2302  out of  11776    19%
2818 
 Number of IOs:                          80
2819 
 Number of bonded IOBs:                  80  out of    161    49%
2820 
    IOB Flip Flops:                       8
2821 
 Number of BRAMs:                         5  out of     20    25%
2822 
 Number of GCLKs:                         1  out of     24     4%
2823 
 
2824 
---------------------------
2825 
 
2826 
====================================================================================
2827 
#                            SYNTHESIS DONE
2828 
#####################################################################################
2829 
 
2830 
#####################################################################################
2831 
#                            START SYNTHESIS (AREA optimized)
2832 
#====================================================================================
2833 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
2834 
#====================================================================================
2835 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2836 
#     12          10          1         1            1          0            0
2837 
#====================================================================================
2838 
Clock to Setup on destination clock dco_clk
2839 
---------------+---------+---------+---------+---------+
2840 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2841 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2842 
---------------+---------+---------+---------+---------+
2843 
dco_clk        |   50.009|   24.206|         |    1.448|
2844 
---------------+---------+---------+---------+---------+
2845 
 
2846 
====================================================================================
2847 
Device utilization summary:
2848 
---------------------------
2849 
 
2850 
Selected Device : 3sd1800acs484-4
2851 
 
2852 
 Number of Slices:                     1294  out of  16640     7%
2853 
 Number of Slice Flip Flops:            680  out of  33280     2%
2854 
 Number of 4 input LUTs:               2310  out of  33280     6%
2855 
 Number of IOs:                          80
2856 
 Number of bonded IOBs:                  80  out of    309    25%
2857 
    IOB Flip Flops:                       8
2858 
 Number of BRAMs:                         5  out of     84     5%
2859 
 Number of GCLKs:                         1  out of     24     4%
2860 
 
2861 
---------------------------
2862 
 
2863 
====================================================================================
2864 
#                            SYNTHESIS DONE
2865 
#####################################################################################
2866 
 
2867 
#####################################################################################
2868 
#                            START SYNTHESIS (AREA optimized)
2869 
#====================================================================================
2870 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
2871 
#====================================================================================
2872 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2873 
#     12          10          1         1            1          0            0
2874 
#====================================================================================
2875 
Clock to Setup on destination clock dco_clk
2876 
---------------+---------+---------+---------+---------+
2877 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2878 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2879 
---------------+---------+---------+---------+---------+
2880 
dco_clk        |   41.016|   20.465|         |    1.192|
2881 
---------------+---------+---------+---------+---------+
2882 
 
2883 
====================================================================================
2884 
Device utilization summary:
2885 
---------------------------
2886 
 
2887 
Selected Device : 3sd1800acs484-5
2888 
 
2889 
 Number of Slices:                     1295  out of  16640     7%
2890 
 Number of Slice Flip Flops:            680  out of  33280     2%
2891 
 Number of 4 input LUTs:               2312  out of  33280     6%
2892 
 Number of IOs:                          80
2893 
 Number of bonded IOBs:                  80  out of    309    25%
2894 
    IOB Flip Flops:                       8
2895 
 Number of BRAMs:                         5  out of     84     5%
2896 
 Number of GCLKs:                         1  out of     24     4%
2897 
 
2898 
---------------------------
2899 
 
2900 
====================================================================================
2901 
#                            SYNTHESIS DONE
2902 
#####################################################################################
2903 
 
2904 
#####################################################################################
2905 
#                            START SYNTHESIS (AREA optimized)
2906 
#====================================================================================
2907 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
2908 
#====================================================================================
2909 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2910 
#     12          10          1         1            1          0            0
2911 
#====================================================================================
2912 
Clock to Setup on destination clock dco_clk
2913 
---------------+---------+---------+---------+---------+
2914 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2915 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2916 
---------------+---------+---------+---------+---------+
2917 
dco_clk        |   38.244|   19.973|    3.594|    2.681|
2918 
---------------+---------+---------+---------+---------+
2919 
 
2920 
====================================================================================
2921 
Device utilization summary:
2922 
---------------------------
2923 
 
2924 
Selected Device : 6slx45tfgg484-2
2925 
 
2926 
 
2927 
Slice Logic Utilization:
2928 
 Number of Slice Registers:             680  out of  54576     1%
2929 
 Number of Slice LUTs:                 1774  out of  27288     6%
2930 
    Number used as Logic:              1774  out of  27288     6%
2931 
 
2932 
Slice Logic Distribution:
2933 
 Number of LUT Flip Flop pairs used:   1831
2934 
   Number with an unused Flip Flop:    1151  out of   1831    62%
2935 
   Number with an unused LUT:            57  out of   1831     3%
2936 
   Number of fully used LUT-FF pairs:   623  out of   1831    34%
2937 
   Number of unique control sets:        62
2938 
 
2939 
IO Utilization:
2940 
 Number of IOs:                          80
2941 
 Number of bonded IOBs:                  80  out of    296    27%
2942 
    IOB Flip Flops/Latches:               8
2943 
 
2944 
Specific Feature Utilization:
2945 
 Number of Block RAM/FIFO:                5  out of    348     1%
2946 
    Number using Block RAM only:          5
2947 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2948 
 
2949 
---------------------------
2950 
 
2951 
====================================================================================
2952 
#                            SYNTHESIS DONE
2953 
#####################################################################################
2954 
 
2955 
#####################################################################################
2956 
#                            START SYNTHESIS (AREA optimized)
2957 
#====================================================================================
2958 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
2959 
#====================================================================================
2960 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
2961 
#     12          10          1         1            1          0            0
2962 
#====================================================================================
2963 
Clock to Setup on destination clock dco_clk
2964 
---------------+---------+---------+---------+---------+
2965 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
2966 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
2967 
---------------+---------+---------+---------+---------+
2968 
dco_clk        |   28.378|   14.782|    3.376|    2.037|
2969 
---------------+---------+---------+---------+---------+
2970 
 
2971 
====================================================================================
2972 
Device utilization summary:
2973 
---------------------------
2974 
 
2975 
Selected Device : 6slx45tfgg484-3
2976 
 
2977 
 
2978 
Slice Logic Utilization:
2979 
 Number of Slice Registers:             680  out of  54576     1%
2980 
 Number of Slice LUTs:                 1753  out of  27288     6%
2981 
    Number used as Logic:              1753  out of  27288     6%
2982 
 
2983 
Slice Logic Distribution:
2984 
 Number of LUT Flip Flop pairs used:   1810
2985 
   Number with an unused Flip Flop:    1130  out of   1810    62%
2986 
   Number with an unused LUT:            57  out of   1810     3%
2987 
   Number of fully used LUT-FF pairs:   623  out of   1810    34%
2988 
   Number of unique control sets:        62
2989 
 
2990 
IO Utilization:
2991 
 Number of IOs:                          80
2992 
 Number of bonded IOBs:                  80  out of    296    27%
2993 
    IOB Flip Flops/Latches:               8
2994 
 
2995 
Specific Feature Utilization:
2996 
 Number of Block RAM/FIFO:                5  out of    348     1%
2997 
    Number using Block RAM only:          5
2998 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
2999 
 
3000 
---------------------------
3001 
 
3002 
====================================================================================
3003 
#                            SYNTHESIS DONE
3004 
#####################################################################################
3005 
 
3006 
#####################################################################################
3007 
#                            START SYNTHESIS (AREA optimized)
3008 
#====================================================================================
3009 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
3010 
#====================================================================================
3011 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3012 
#     12          10          1         1            1          0            0
3013 
#====================================================================================
3014 
Clock to Setup on destination clock dco_clk
3015 
---------------+---------+---------+---------+---------+
3016 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3017 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3018 
---------------+---------+---------+---------+---------+
3019 
dco_clk        |   26.515|   13.709|    3.445|    1.490|
3020 
---------------+---------+---------+---------+---------+
3021 
 
3022 
====================================================================================
3023 
Device utilization summary:
3024 
---------------------------
3025 
 
3026 
Selected Device : 6slx45tfgg484-4
3027 
 
3028 
 
3029 
Slice Logic Utilization:
3030 
 Number of Slice Registers:             680  out of  54576     1%
3031 
 Number of Slice LUTs:                 1750  out of  27288     6%
3032 
    Number used as Logic:              1750  out of  27288     6%
3033 
 
3034 
Slice Logic Distribution:
3035 
 Number of LUT Flip Flop pairs used:   1807
3036 
   Number with an unused Flip Flop:    1127  out of   1807    62%
3037 
   Number with an unused LUT:            57  out of   1807     3%
3038 
   Number of fully used LUT-FF pairs:   623  out of   1807    34%
3039 
   Number of unique control sets:        62
3040 
 
3041 
IO Utilization:
3042 
 Number of IOs:                          80
3043 
 Number of bonded IOBs:                  80  out of    296    27%
3044 
    IOB Flip Flops/Latches:               8
3045 
 
3046 
Specific Feature Utilization:
3047 
 Number of Block RAM/FIFO:                5  out of    348     1%
3048 
    Number using Block RAM only:          5
3049 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3050 
 
3051 
---------------------------
3052 
 
3053 
====================================================================================
3054 
#                            SYNTHESIS DONE
3055 
#####################################################################################
3056 
 
3057 
#####################################################################################
3058 
#                            START SYNTHESIS (AREA optimized)
3059 
#====================================================================================
3060 
# virtex4 (xc4vlx25sf363), speedgrade: -10
3061 
#====================================================================================
3062 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3063 
#     12          10          1         1            1          0            0
3064 
#====================================================================================
3065 
Clock to Setup on destination clock dco_clk
3066 
---------------+---------+---------+---------+---------+
3067 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3068 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3069 
---------------+---------+---------+---------+---------+
3070 
dco_clk        |   35.922|   17.864|         |    1.208|
3071 
---------------+---------+---------+---------+---------+
3072 
 
3073 
====================================================================================
3074 
Device utilization summary:
3075 
---------------------------
3076 
 
3077 
Selected Device : 4vlx25sf363-10
3078 
 
3079 
 Number of Slices:                     1287  out of  10752    11%
3080 
 Number of Slice Flip Flops:            680  out of  21504     3%
3081 
 Number of 4 input LUTs:               2305  out of  21504    10%
3082 
 Number of IOs:                          80
3083 
 Number of bonded IOBs:                  80  out of    240    33%
3084 
    IOB Flip Flops:                       8
3085 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3086 
    Number used as RAMB16s:               5
3087 
 Number of GCLKs:                         1  out of     32     3%
3088 
 
3089 
---------------------------
3090 
 
3091 
====================================================================================
3092 
#                            SYNTHESIS DONE
3093 
#####################################################################################
3094 
 
3095 
#####################################################################################
3096 
#                            START SYNTHESIS (AREA optimized)
3097 
#====================================================================================
3098 
# virtex4 (xc4vlx25sf363), speedgrade: -11
3099 
#====================================================================================
3100 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3101 
#     12          10          1         1            1          0            0
3102 
#====================================================================================
3103 
Clock to Setup on destination clock dco_clk
3104 
---------------+---------+---------+---------+---------+
3105 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3106 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3107 
---------------+---------+---------+---------+---------+
3108 
dco_clk        |   29.389|   14.672|         |    0.807|
3109 
---------------+---------+---------+---------+---------+
3110 
 
3111 
====================================================================================
3112 
Device utilization summary:
3113 
---------------------------
3114 
 
3115 
Selected Device : 4vlx25sf363-11
3116 
 
3117 
 Number of Slices:                     1288  out of  10752    11%
3118 
 Number of Slice Flip Flops:            680  out of  21504     3%
3119 
 Number of 4 input LUTs:               2307  out of  21504    10%
3120 
 Number of IOs:                          80
3121 
 Number of bonded IOBs:                  80  out of    240    33%
3122 
    IOB Flip Flops:                       8
3123 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3124 
    Number used as RAMB16s:               5
3125 
 Number of GCLKs:                         1  out of     32     3%
3126 
 
3127 
---------------------------
3128 
 
3129 
====================================================================================
3130 
#                            SYNTHESIS DONE
3131 
#####################################################################################
3132 
 
3133 
#####################################################################################
3134 
#                            START SYNTHESIS (AREA optimized)
3135 
#====================================================================================
3136 
# virtex4 (xc4vlx25sf363), speedgrade: -12
3137 
#====================================================================================
3138 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3139 
#     12          10          1         1            1          0            0
3140 
#====================================================================================
3141 
Clock to Setup on destination clock dco_clk
3142 
---------------+---------+---------+---------+---------+
3143 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3144 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3145 
---------------+---------+---------+---------+---------+
3146 
dco_clk        |   24.991|   12.374|         |    0.894|
3147 
---------------+---------+---------+---------+---------+
3148 
 
3149 
====================================================================================
3150 
Device utilization summary:
3151 
---------------------------
3152 
 
3153 
Selected Device : 4vlx25sf363-12
3154 
 
3155 
 Number of Slices:                     1287  out of  10752    11%
3156 
 Number of Slice Flip Flops:            680  out of  21504     3%
3157 
 Number of 4 input LUTs:               2305  out of  21504    10%
3158 
 Number of IOs:                          80
3159 
 Number of bonded IOBs:                  80  out of    240    33%
3160 
    IOB Flip Flops:                       8
3161 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3162 
    Number used as RAMB16s:               5
3163 
 Number of GCLKs:                         1  out of     32     3%
3164 
 
3165 
---------------------------
3166 
 
3167 
====================================================================================
3168 
#                            SYNTHESIS DONE
3169 
#####################################################################################
3170 
 
3171 
#####################################################################################
3172 
#                            START SYNTHESIS (AREA optimized)
3173 
#====================================================================================
3174 
# virtex5 (xc5vlx30ff324), speedgrade: -1
3175 
#====================================================================================
3176 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3177 
#     12          10          1         1            1          0            0
3178 
#====================================================================================
3179 
Clock to Setup on destination clock dco_clk
3180 
---------------+---------+---------+---------+---------+
3181 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3182 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3183 
---------------+---------+---------+---------+---------+
3184 
dco_clk        |   19.544|    9.824|         |    1.314|
3185 
---------------+---------+---------+---------+---------+
3186 
 
3187 
====================================================================================
3188 
Device utilization summary:
3189 
---------------------------
3190 
 
3191 
Selected Device : 5vlx30ff324-1
3192 
 
3193 
 
3194 
Slice Logic Utilization:
3195 
 Number of Slice Registers:             679  out of  19200     3%
3196 
 Number of Slice LUTs:                 1753  out of  19200     9%
3197 
    Number used as Logic:              1753  out of  19200     9%
3198 
 
3199 
Slice Logic Distribution:
3200 
 Number of LUT Flip Flop pairs used:   1812
3201 
   Number with an unused Flip Flop:    1133  out of   1812    62%
3202 
   Number with an unused LUT:            59  out of   1812     3%
3203 
   Number of fully used LUT-FF pairs:   620  out of   1812    34%
3204 
   Number of unique control sets:        61
3205 
 
3206 
IO Utilization:
3207 
 Number of IOs:                          80
3208 
 Number of bonded IOBs:                  80  out of    220    36%
3209 
    IOB Flip Flops/Latches:               8
3210 
 
3211 
Specific Feature Utilization:
3212 
 Number of Block RAM/FIFO:                3  out of     32     9%
3213 
    Number using Block RAM only:          3
3214 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3215 
 
3216 
---------------------------
3217 
 
3218 
====================================================================================
3219 
#                            SYNTHESIS DONE
3220 
#####################################################################################
3221 
 
3222 
#####################################################################################
3223 
#                            START SYNTHESIS (AREA optimized)
3224 
#====================================================================================
3225 
# virtex5 (xc5vlx30ff324), speedgrade: -2
3226 
#====================================================================================
3227 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3228 
#     12          10          1         1            1          0            0
3229 
#====================================================================================
3230 
Clock to Setup on destination clock dco_clk
3231 
---------------+---------+---------+---------+---------+
3232 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3233 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3234 
---------------+---------+---------+---------+---------+
3235 
dco_clk        |   17.151|    8.401|         |    0.715|
3236 
---------------+---------+---------+---------+---------+
3237 
 
3238 
====================================================================================
3239 
Device utilization summary:
3240 
---------------------------
3241 
 
3242 
Selected Device : 5vlx30ff324-2
3243 
 
3244 
 
3245 
Slice Logic Utilization:
3246 
 Number of Slice Registers:             679  out of  19200     3%
3247 
 Number of Slice LUTs:                 1752  out of  19200     9%
3248 
    Number used as Logic:              1752  out of  19200     9%
3249 
 
3250 
Slice Logic Distribution:
3251 
 Number of LUT Flip Flop pairs used:   1811
3252 
   Number with an unused Flip Flop:    1132  out of   1811    62%
3253 
   Number with an unused LUT:            59  out of   1811     3%
3254 
   Number of fully used LUT-FF pairs:   620  out of   1811    34%
3255 
   Number of unique control sets:        61
3256 
 
3257 
IO Utilization:
3258 
 Number of IOs:                          80
3259 
 Number of bonded IOBs:                  80  out of    220    36%
3260 
    IOB Flip Flops/Latches:               8
3261 
 
3262 
Specific Feature Utilization:
3263 
 Number of Block RAM/FIFO:                3  out of     32     9%
3264 
    Number using Block RAM only:          3
3265 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3266 
 
3267 
---------------------------
3268 
 
3269 
====================================================================================
3270 
#                            SYNTHESIS DONE
3271 
#####################################################################################
3272 
 
3273 
#####################################################################################
3274 
#                            START SYNTHESIS (AREA optimized)
3275 
#====================================================================================
3276 
# virtex5 (xc5vlx30ff324), speedgrade: -3
3277 
#====================================================================================
3278 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3279 
#     12          10          1         1            1          0            0
3280 
#====================================================================================
3281 
Clock to Setup on destination clock dco_clk
3282 
---------------+---------+---------+---------+---------+
3283 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3284 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3285 
---------------+---------+---------+---------+---------+
3286 
dco_clk        |   16.086|    8.135|         |    0.979|
3287 
---------------+---------+---------+---------+---------+
3288 
 
3289 
====================================================================================
3290 
Device utilization summary:
3291 
---------------------------
3292 
 
3293 
Selected Device : 5vlx30ff324-3
3294 
 
3295 
 
3296 
Slice Logic Utilization:
3297 
 Number of Slice Registers:             679  out of  19200     3%
3298 
 Number of Slice LUTs:                 1751  out of  19200     9%
3299 
    Number used as Logic:              1751  out of  19200     9%
3300 
 
3301 
Slice Logic Distribution:
3302 
 Number of LUT Flip Flop pairs used:   1810
3303 
   Number with an unused Flip Flop:    1131  out of   1810    62%
3304 
   Number with an unused LUT:            59  out of   1810     3%
3305 
   Number of fully used LUT-FF pairs:   620  out of   1810    34%
3306 
   Number of unique control sets:        61
3307 
 
3308 
IO Utilization:
3309 
 Number of IOs:                          80
3310 
 Number of bonded IOBs:                  80  out of    220    36%
3311 
    IOB Flip Flops/Latches:               8
3312 
 
3313 
Specific Feature Utilization:
3314 
 Number of Block RAM/FIFO:                3  out of     32     9%
3315 
    Number using Block RAM only:          3
3316 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3317 
 
3318 
---------------------------
3319 
 
3320 
====================================================================================
3321 
#                            SYNTHESIS DONE
3322 
#####################################################################################
3323 
 
3324 
#####################################################################################
3325 
#                            START SYNTHESIS (AREA optimized)
3326 
#====================================================================================
3327 
# virtex6 (xc6vlx75tff484), speedgrade: -1
3328 
#====================================================================================
3329 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3330 
#     12          10          1         1            1          0            0
3331 
#====================================================================================
3332 
Clock to Setup on destination clock dco_clk
3333 
---------------+---------+---------+---------+---------+
3334 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3335 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3336 
---------------+---------+---------+---------+---------+
3337 
dco_clk        |   18.029|    9.072|    2.246|    0.694|
3338 
---------------+---------+---------+---------+---------+
3339 
 
3340 
====================================================================================
3341 
Device utilization summary:
3342 
---------------------------
3343 
 
3344 
Selected Device : 6vlx75tff484-1
3345 
 
3346 
 
3347 
Slice Logic Utilization:
3348 
 Number of Slice Registers:             679  out of  93120     0%
3349 
 Number of Slice LUTs:                 1746  out of  46560     3%
3350 
    Number used as Logic:              1746  out of  46560     3%
3351 
 
3352 
Slice Logic Distribution:
3353 
 Number of LUT Flip Flop pairs used:   1802
3354 
   Number with an unused Flip Flop:    1123  out of   1802    62%
3355 
   Number with an unused LUT:            56  out of   1802     3%
3356 
   Number of fully used LUT-FF pairs:   623  out of   1802    34%
3357 
   Number of unique control sets:        61
3358 
 
3359 
IO Utilization:
3360 
 Number of IOs:                          80
3361 
 Number of bonded IOBs:                  80  out of    240    33%
3362 
    IOB Flip Flops/Latches:               8
3363 
 
3364 
Specific Feature Utilization:
3365 
 Number of Block RAM/FIFO:                3  out of    156     1%
3366 
    Number using Block RAM only:          3
3367 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3368 
 
3369 
---------------------------
3370 
 
3371 
====================================================================================
3372 
#                            SYNTHESIS DONE
3373 
#####################################################################################
3374 
 
3375 
#####################################################################################
3376 
#                            START SYNTHESIS (AREA optimized)
3377 
#====================================================================================
3378 
# virtex6 (xc6vlx75tff484), speedgrade: -2
3379 
#====================================================================================
3380 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3381 
#     12          10          1         1            1          0            0
3382 
#====================================================================================
3383 
Clock to Setup on destination clock dco_clk
3384 
---------------+---------+---------+---------+---------+
3385 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3386 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3387 
---------------+---------+---------+---------+---------+
3388 
dco_clk        |   17.490|    8.693|    2.120|    0.530|
3389 
---------------+---------+---------+---------+---------+
3390 
 
3391 
====================================================================================
3392 
Device utilization summary:
3393 
---------------------------
3394 
 
3395 
Selected Device : 6vlx75tff484-2
3396 
 
3397 
 
3398 
Slice Logic Utilization:
3399 
 Number of Slice Registers:             679  out of  93120     0%
3400 
 Number of Slice LUTs:                 1737  out of  46560     3%
3401 
    Number used as Logic:              1737  out of  46560     3%
3402 
 
3403 
Slice Logic Distribution:
3404 
 Number of LUT Flip Flop pairs used:   1793
3405 
   Number with an unused Flip Flop:    1114  out of   1793    62%
3406 
   Number with an unused LUT:            56  out of   1793     3%
3407 
   Number of fully used LUT-FF pairs:   623  out of   1793    34%
3408 
   Number of unique control sets:        61
3409 
 
3410 
IO Utilization:
3411 
 Number of IOs:                          80
3412 
 Number of bonded IOBs:                  80  out of    240    33%
3413 
    IOB Flip Flops/Latches:               8
3414 
 
3415 
Specific Feature Utilization:
3416 
 Number of Block RAM/FIFO:                3  out of    156     1%
3417 
    Number using Block RAM only:          3
3418 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3419 
 
3420 
---------------------------
3421 
 
3422 
====================================================================================
3423 
#                            SYNTHESIS DONE
3424 
#####################################################################################
3425 
 
3426 
#####################################################################################
3427 
#                            START SYNTHESIS (AREA optimized)
3428 
#====================================================================================
3429 
# virtex6 (xc6vlx75tff484), speedgrade: -3
3430 
#====================================================================================
3431 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3432 
#     12          10          1         1            1          0            0
3433 
#====================================================================================
3434 
Clock to Setup on destination clock dco_clk
3435 
---------------+---------+---------+---------+---------+
3436 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3437 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3438 
---------------+---------+---------+---------+---------+
3439 
dco_clk        |   14.359|    7.297|    1.747|    0.520|
3440 
---------------+---------+---------+---------+---------+
3441 
 
3442 
====================================================================================
3443 
Device utilization summary:
3444 
---------------------------
3445 
 
3446 
Selected Device : 6vlx75tff484-3
3447 
 
3448 
 
3449 
Slice Logic Utilization:
3450 
 Number of Slice Registers:             679  out of  93120     0%
3451 
 Number of Slice LUTs:                 1737  out of  46560     3%
3452 
    Number used as Logic:              1737  out of  46560     3%
3453 
 
3454 
Slice Logic Distribution:
3455 
 Number of LUT Flip Flop pairs used:   1793
3456 
   Number with an unused Flip Flop:    1114  out of   1793    62%
3457 
   Number with an unused LUT:            56  out of   1793     3%
3458 
   Number of fully used LUT-FF pairs:   623  out of   1793    34%
3459 
   Number of unique control sets:        61
3460 
 
3461 
IO Utilization:
3462 
 Number of IOs:                          80
3463 
 Number of bonded IOBs:                  80  out of    240    33%
3464 
    IOB Flip Flops/Latches:               8
3465 
 
3466 
Specific Feature Utilization:
3467 
 Number of Block RAM/FIFO:                3  out of    156     1%
3468 
    Number using Block RAM only:          3
3469 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
3470 
 
3471 
---------------------------
3472 
 
3473 
====================================================================================
3474 
#                            SYNTHESIS DONE
3475 
#####################################################################################
3476 
 
3477 
#####################################################################################
3478 
#                            START SYNTHESIS (AREA optimized)
3479 
#====================================================================================
3480 
# spartan3 (xc3s400pq208), speedgrade: -4
3481 
#====================================================================================
3482 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3483 
#     12          10          1         1            1          1            0
3484 
#====================================================================================
3485 
Clock to Setup on destination clock dco_clk
3486 
---------------+---------+---------+---------+---------+
3487 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3488 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3489 
---------------+---------+---------+---------+---------+
3490 
dco_clk        |   52.754|   25.719|         |    1.573|
3491 
---------------+---------+---------+---------+---------+
3492 
 
3493 
====================================================================================
3494 
Device utilization summary:
3495 
---------------------------
3496 
 
3497 
Selected Device : 3s400pq208-4
3498 
 
3499 
 Number of Slices:                     1322  out of   3584    36%
3500 
 Number of Slice Flip Flops:            721  out of   7168    10%
3501 
 Number of 4 input LUTs:               2366  out of   7168    33%
3502 
 Number of IOs:                          80
3503 
 Number of bonded IOBs:                  80  out of    141    56%
3504 
    IOB Flip Flops:                       8
3505 
 Number of BRAMs:                         6  out of     16    37%
3506 
 Number of GCLKs:                         1  out of      8    12%
3507 
 
3508 
---------------------------
3509 
 
3510 
====================================================================================
3511 
#                            SYNTHESIS DONE
3512 
#####################################################################################
3513 
 
3514 
#####################################################################################
3515 
#                            START SYNTHESIS (AREA optimized)
3516 
#====================================================================================
3517 
# spartan3 (xc3s400pq208), speedgrade: -5
3518 
#====================================================================================
3519 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3520 
#     12          10          1         1            1          1            0
3521 
#====================================================================================
3522 
Clock to Setup on destination clock dco_clk
3523 
---------------+---------+---------+---------+---------+
3524 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3525 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3526 
---------------+---------+---------+---------+---------+
3527 
dco_clk        |   46.221|   21.960|         |    1.361|
3528 
---------------+---------+---------+---------+---------+
3529 
 
3530 
====================================================================================
3531 
Device utilization summary:
3532 
---------------------------
3533 
 
3534 
Selected Device : 3s400pq208-5
3535 
 
3536 
 Number of Slices:                     1323  out of   3584    36%
3537 
 Number of Slice Flip Flops:            721  out of   7168    10%
3538 
 Number of 4 input LUTs:               2367  out of   7168    33%
3539 
 Number of IOs:                          80
3540 
 Number of bonded IOBs:                  80  out of    141    56%
3541 
    IOB Flip Flops:                       8
3542 
 Number of BRAMs:                         6  out of     16    37%
3543 
 Number of GCLKs:                         1  out of      8    12%
3544 
 
3545 
---------------------------
3546 
 
3547 
====================================================================================
3548 
#                            SYNTHESIS DONE
3549 
#####################################################################################
3550 
 
3551 
#####################################################################################
3552 
#                            START SYNTHESIS (AREA optimized)
3553 
#====================================================================================
3554 
# spartan3e (xc3s500epq208), speedgrade: -4
3555 
#====================================================================================
3556 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3557 
#     12          10          1         1            1          1            0
3558 
#====================================================================================
3559 
Clock to Setup on destination clock dco_clk
3560 
---------------+---------+---------+---------+---------+
3561 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3562 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3563 
---------------+---------+---------+---------+---------+
3564 
dco_clk        |   48.773|   23.787|         |    1.467|
3565 
---------------+---------+---------+---------+---------+
3566 
 
3567 
====================================================================================
3568 
Device utilization summary:
3569 
---------------------------
3570 
 
3571 
Selected Device : 3s500epq208-4
3572 
 
3573 
 Number of Slices:                     1329  out of   4656    28%
3574 
 Number of Slice Flip Flops:            721  out of   9312     7%
3575 
 Number of 4 input LUTs:               2383  out of   9312    25%
3576 
 Number of IOs:                          80
3577 
 Number of bonded IOBs:                  80  out of    158    50%
3578 
    IOB Flip Flops:                       8
3579 
 Number of BRAMs:                         6  out of     20    30%
3580 
 Number of GCLKs:                         1  out of     24     4%
3581 
 
3582 
---------------------------
3583 
 
3584 
====================================================================================
3585 
#                            SYNTHESIS DONE
3586 
#####################################################################################
3587 
 
3588 
#####################################################################################
3589 
#                            START SYNTHESIS (AREA optimized)
3590 
#====================================================================================
3591 
# spartan3e (xc3s500epq208), speedgrade: -5
3592 
#====================================================================================
3593 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3594 
#     12          10          1         1            1          1            0
3595 
#====================================================================================
3596 
Clock to Setup on destination clock dco_clk
3597 
---------------+---------+---------+---------+---------+
3598 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3599 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3600 
---------------+---------+---------+---------+---------+
3601 
dco_clk        |   42.392|   20.984|         |    1.475|
3602 
---------------+---------+---------+---------+---------+
3603 
 
3604 
====================================================================================
3605 
Device utilization summary:
3606 
---------------------------
3607 
 
3608 
Selected Device : 3s500epq208-5
3609 
 
3610 
 Number of Slices:                     1329  out of   4656    28%
3611 
 Number of Slice Flip Flops:            721  out of   9312     7%
3612 
 Number of 4 input LUTs:               2383  out of   9312    25%
3613 
 Number of IOs:                          80
3614 
 Number of bonded IOBs:                  80  out of    158    50%
3615 
    IOB Flip Flops:                       8
3616 
 Number of BRAMs:                         6  out of     20    30%
3617 
 Number of GCLKs:                         1  out of     24     4%
3618 
 
3619 
---------------------------
3620 
 
3621 
====================================================================================
3622 
#                            SYNTHESIS DONE
3623 
#####################################################################################
3624 
 
3625 
#####################################################################################
3626 
#                            START SYNTHESIS (AREA optimized)
3627 
#====================================================================================
3628 
# spartan3a (xc3s700aft256), speedgrade: -4
3629 
#====================================================================================
3630 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3631 
#     12          10          1         1            1          1            0
3632 
#====================================================================================
3633 
Clock to Setup on destination clock dco_clk
3634 
---------------+---------+---------+---------+---------+
3635 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3636 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3637 
---------------+---------+---------+---------+---------+
3638 
dco_clk        |   49.972|   25.346|         |    1.448|
3639 
---------------+---------+---------+---------+---------+
3640 
 
3641 
====================================================================================
3642 
Device utilization summary:
3643 
---------------------------
3644 
 
3645 
Selected Device : 3s700aft256-4
3646 
 
3647 
 Number of Slices:                     1338  out of   5888    22%
3648 
 Number of Slice Flip Flops:            722  out of  11776     6%
3649 
 Number of 4 input LUTs:               2396  out of  11776    20%
3650 
 Number of IOs:                          80
3651 
 Number of bonded IOBs:                  80  out of    161    49%
3652 
    IOB Flip Flops:                       8
3653 
 Number of BRAMs:                         5  out of     20    25%
3654 
 Number of GCLKs:                         1  out of     24     4%
3655 
 
3656 
---------------------------
3657 
 
3658 
====================================================================================
3659 
#                            SYNTHESIS DONE
3660 
#####################################################################################
3661 
 
3662 
#####################################################################################
3663 
#                            START SYNTHESIS (AREA optimized)
3664 
#====================================================================================
3665 
# spartan3a (xc3s700aft256), speedgrade: -5
3666 
#====================================================================================
3667 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3668 
#     12          10          1         1            1          1            0
3669 
#====================================================================================
3670 
Clock to Setup on destination clock dco_clk
3671 
---------------+---------+---------+---------+---------+
3672 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3673 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3674 
---------------+---------+---------+---------+---------+
3675 
dco_clk        |   43.331|   22.040|         |    1.215|
3676 
---------------+---------+---------+---------+---------+
3677 
 
3678 
====================================================================================
3679 
Device utilization summary:
3680 
---------------------------
3681 
 
3682 
Selected Device : 3s700aft256-5
3683 
 
3684 
 Number of Slices:                     1333  out of   5888    22%
3685 
 Number of Slice Flip Flops:            722  out of  11776     6%
3686 
 Number of 4 input LUTs:               2388  out of  11776    20%
3687 
 Number of IOs:                          80
3688 
 Number of bonded IOBs:                  80  out of    161    49%
3689 
    IOB Flip Flops:                       8
3690 
 Number of BRAMs:                         5  out of     20    25%
3691 
 Number of GCLKs:                         1  out of     24     4%
3692 
 
3693 
---------------------------
3694 
 
3695 
====================================================================================
3696 
#                            SYNTHESIS DONE
3697 
#####################################################################################
3698 
 
3699 
#####################################################################################
3700 
#                            START SYNTHESIS (AREA optimized)
3701 
#====================================================================================
3702 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
3703 
#====================================================================================
3704 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3705 
#     12          10          1         1            1          1            0
3706 
#====================================================================================
3707 
Clock to Setup on destination clock dco_clk
3708 
---------------+---------+---------+---------+---------+
3709 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3710 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3711 
---------------+---------+---------+---------+---------+
3712 
dco_clk        |   50.455|   24.701|         |    1.448|
3713 
---------------+---------+---------+---------+---------+
3714 
 
3715 
====================================================================================
3716 
Device utilization summary:
3717 
---------------------------
3718 
 
3719 
Selected Device : 3sd1800acs484-4
3720 
 
3721 
 Number of Slices:                     1343  out of  16640     8%
3722 
 Number of Slice Flip Flops:            722  out of  33280     2%
3723 
 Number of 4 input LUTs:               2402  out of  33280     7%
3724 
 Number of IOs:                          80
3725 
 Number of bonded IOBs:                  80  out of    309    25%
3726 
    IOB Flip Flops:                       8
3727 
 Number of BRAMs:                         5  out of     84     5%
3728 
 Number of GCLKs:                         1  out of     24     4%
3729 
 
3730 
---------------------------
3731 
 
3732 
====================================================================================
3733 
#                            SYNTHESIS DONE
3734 
#####################################################################################
3735 
 
3736 
#####################################################################################
3737 
#                            START SYNTHESIS (AREA optimized)
3738 
#====================================================================================
3739 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
3740 
#====================================================================================
3741 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3742 
#     12          10          1         1            1          1            0
3743 
#====================================================================================
3744 
Clock to Setup on destination clock dco_clk
3745 
---------------+---------+---------+---------+---------+
3746 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3747 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3748 
---------------+---------+---------+---------+---------+
3749 
dco_clk        |   41.805|   20.761|         |    1.302|
3750 
---------------+---------+---------+---------+---------+
3751 
 
3752 
====================================================================================
3753 
Device utilization summary:
3754 
---------------------------
3755 
 
3756 
Selected Device : 3sd1800acs484-5
3757 
 
3758 
 Number of Slices:                     1343  out of  16640     8%
3759 
 Number of Slice Flip Flops:            722  out of  33280     2%
3760 
 Number of 4 input LUTs:               2400  out of  33280     7%
3761 
 Number of IOs:                          80
3762 
 Number of bonded IOBs:                  80  out of    309    25%
3763 
    IOB Flip Flops:                       8
3764 
 Number of BRAMs:                         5  out of     84     5%
3765 
 Number of GCLKs:                         1  out of     24     4%
3766 
 
3767 
---------------------------
3768 
 
3769 
====================================================================================
3770 
#                            SYNTHESIS DONE
3771 
#####################################################################################
3772 
 
3773 
#####################################################################################
3774 
#                            START SYNTHESIS (AREA optimized)
3775 
#====================================================================================
3776 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
3777 
#====================================================================================
3778 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3779 
#     12          10          1         1            1          1            0
3780 
#====================================================================================
3781 
Clock to Setup on destination clock dco_clk
3782 
---------------+---------+---------+---------+---------+
3783 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3784 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3785 
---------------+---------+---------+---------+---------+
3786 
dco_clk        |   39.545|   19.046|    3.890|    2.332|
3787 
---------------+---------+---------+---------+---------+
3788 
 
3789 
====================================================================================
3790 
Device utilization summary:
3791 
---------------------------
3792 
 
3793 
Selected Device : 6slx45tfgg484-2
3794 
 
3795 
 
3796 
Slice Logic Utilization:
3797 
 Number of Slice Registers:             722  out of  54576     1%
3798 
 Number of Slice LUTs:                 1851  out of  27288     6%
3799 
    Number used as Logic:              1851  out of  27288     6%
3800 
 
3801 
Slice Logic Distribution:
3802 
 Number of LUT Flip Flop pairs used:   1924
3803 
   Number with an unused Flip Flop:    1202  out of   1924    62%
3804 
   Number with an unused LUT:            73  out of   1924     3%
3805 
   Number of fully used LUT-FF pairs:   649  out of   1924    33%
3806 
   Number of unique control sets:        65
3807 
 
3808 
IO Utilization:
3809 
 Number of IOs:                          80
3810 
 Number of bonded IOBs:                  80  out of    296    27%
3811 
    IOB Flip Flops/Latches:               8
3812 
 
3813 
Specific Feature Utilization:
3814 
 Number of Block RAM/FIFO:                5  out of    348     1%
3815 
    Number using Block RAM only:          5
3816 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3817 
 
3818 
---------------------------
3819 
 
3820 
====================================================================================
3821 
#                            SYNTHESIS DONE
3822 
#####################################################################################
3823 
 
3824 
#####################################################################################
3825 
#                            START SYNTHESIS (AREA optimized)
3826 
#====================================================================================
3827 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
3828 
#====================================================================================
3829 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3830 
#     12          10          1         1            1          1            0
3831 
#====================================================================================
3832 
Clock to Setup on destination clock dco_clk
3833 
---------------+---------+---------+---------+---------+
3834 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3835 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3836 
---------------+---------+---------+---------+---------+
3837 
dco_clk        |   29.257|   15.691|    3.516|    2.136|
3838 
---------------+---------+---------+---------+---------+
3839 
 
3840 
====================================================================================
3841 
Device utilization summary:
3842 
---------------------------
3843 
 
3844 
Selected Device : 6slx45tfgg484-3
3845 
 
3846 
 
3847 
Slice Logic Utilization:
3848 
 Number of Slice Registers:             722  out of  54576     1%
3849 
 Number of Slice LUTs:                 1829  out of  27288     6%
3850 
    Number used as Logic:              1829  out of  27288     6%
3851 
 
3852 
Slice Logic Distribution:
3853 
 Number of LUT Flip Flop pairs used:   1902
3854 
   Number with an unused Flip Flop:    1180  out of   1902    62%
3855 
   Number with an unused LUT:            73  out of   1902     3%
3856 
   Number of fully used LUT-FF pairs:   649  out of   1902    34%
3857 
   Number of unique control sets:        65
3858 
 
3859 
IO Utilization:
3860 
 Number of IOs:                          80
3861 
 Number of bonded IOBs:                  80  out of    296    27%
3862 
    IOB Flip Flops/Latches:               8
3863 
 
3864 
Specific Feature Utilization:
3865 
 Number of Block RAM/FIFO:                5  out of    348     1%
3866 
    Number using Block RAM only:          5
3867 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3868 
 
3869 
---------------------------
3870 
 
3871 
====================================================================================
3872 
#                            SYNTHESIS DONE
3873 
#####################################################################################
3874 
 
3875 
#####################################################################################
3876 
#                            START SYNTHESIS (AREA optimized)
3877 
#====================================================================================
3878 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
3879 
#====================================================================================
3880 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3881 
#     12          10          1         1            1          1            0
3882 
#====================================================================================
3883 
Clock to Setup on destination clock dco_clk
3884 
---------------+---------+---------+---------+---------+
3885 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3886 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3887 
---------------+---------+---------+---------+---------+
3888 
dco_clk        |   26.058|   12.330|    3.145|    1.813|
3889 
---------------+---------+---------+---------+---------+
3890 
 
3891 
====================================================================================
3892 
Device utilization summary:
3893 
---------------------------
3894 
 
3895 
Selected Device : 6slx45tfgg484-4
3896 
 
3897 
 
3898 
Slice Logic Utilization:
3899 
 Number of Slice Registers:             722  out of  54576     1%
3900 
 Number of Slice LUTs:                 1828  out of  27288     6%
3901 
    Number used as Logic:              1828  out of  27288     6%
3902 
 
3903 
Slice Logic Distribution:
3904 
 Number of LUT Flip Flop pairs used:   1901
3905 
   Number with an unused Flip Flop:    1179  out of   1901    62%
3906 
   Number with an unused LUT:            73  out of   1901     3%
3907 
   Number of fully used LUT-FF pairs:   649  out of   1901    34%
3908 
   Number of unique control sets:        65
3909 
 
3910 
IO Utilization:
3911 
 Number of IOs:                          80
3912 
 Number of bonded IOBs:                  80  out of    296    27%
3913 
    IOB Flip Flops/Latches:               8
3914 
 
3915 
Specific Feature Utilization:
3916 
 Number of Block RAM/FIFO:                5  out of    348     1%
3917 
    Number using Block RAM only:          5
3918 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
3919 
 
3920 
---------------------------
3921 
 
3922 
====================================================================================
3923 
#                            SYNTHESIS DONE
3924 
#####################################################################################
3925 
 
3926 
#####################################################################################
3927 
#                            START SYNTHESIS (AREA optimized)
3928 
#====================================================================================
3929 
# virtex4 (xc4vlx25sf363), speedgrade: -10
3930 
#====================================================================================
3931 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3932 
#     12          10          1         1            1          1            0
3933 
#====================================================================================
3934 
Clock to Setup on destination clock dco_clk
3935 
---------------+---------+---------+---------+---------+
3936 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3937 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3938 
---------------+---------+---------+---------+---------+
3939 
dco_clk        |   35.320|   17.572|         |    0.943|
3940 
---------------+---------+---------+---------+---------+
3941 
 
3942 
====================================================================================
3943 
Device utilization summary:
3944 
---------------------------
3945 
 
3946 
Selected Device : 4vlx25sf363-10
3947 
 
3948 
 Number of Slices:                     1338  out of  10752    12%
3949 
 Number of Slice Flip Flops:            722  out of  21504     3%
3950 
 Number of 4 input LUTs:               2395  out of  21504    11%
3951 
 Number of IOs:                          80
3952 
 Number of bonded IOBs:                  80  out of    240    33%
3953 
    IOB Flip Flops:                       8
3954 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3955 
    Number used as RAMB16s:               5
3956 
 Number of GCLKs:                         1  out of     32     3%
3957 
 
3958 
---------------------------
3959 
 
3960 
====================================================================================
3961 
#                            SYNTHESIS DONE
3962 
#####################################################################################
3963 
 
3964 
#####################################################################################
3965 
#                            START SYNTHESIS (AREA optimized)
3966 
#====================================================================================
3967 
# virtex4 (xc4vlx25sf363), speedgrade: -11
3968 
#====================================================================================
3969 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
3970 
#     12          10          1         1            1          1            0
3971 
#====================================================================================
3972 
Clock to Setup on destination clock dco_clk
3973 
---------------+---------+---------+---------+---------+
3974 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
3975 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
3976 
---------------+---------+---------+---------+---------+
3977 
dco_clk        |   28.130|   14.160|         |    0.807|
3978 
---------------+---------+---------+---------+---------+
3979 
 
3980 
====================================================================================
3981 
Device utilization summary:
3982 
---------------------------
3983 
 
3984 
Selected Device : 4vlx25sf363-11
3985 
 
3986 
 Number of Slices:                     1339  out of  10752    12%
3987 
 Number of Slice Flip Flops:            722  out of  21504     3%
3988 
 Number of 4 input LUTs:               2396  out of  21504    11%
3989 
 Number of IOs:                          80
3990 
 Number of bonded IOBs:                  80  out of    240    33%
3991 
    IOB Flip Flops:                       8
3992 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
3993 
    Number used as RAMB16s:               5
3994 
 Number of GCLKs:                         1  out of     32     3%
3995 
 
3996 
---------------------------
3997 
 
3998 
====================================================================================
3999 
#                            SYNTHESIS DONE
4000 
#####################################################################################
4001 
 
4002 
#####################################################################################
4003 
#                            START SYNTHESIS (AREA optimized)
4004 
#====================================================================================
4005 
# virtex4 (xc4vlx25sf363), speedgrade: -12
4006 
#====================================================================================
4007 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4008 
#     12          10          1         1            1          1            0
4009 
#====================================================================================
4010 
Clock to Setup on destination clock dco_clk
4011 
---------------+---------+---------+---------+---------+
4012 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4013 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4014 
---------------+---------+---------+---------+---------+
4015 
dco_clk        |   27.704|   13.422|         |    0.717|
4016 
---------------+---------+---------+---------+---------+
4017 
 
4018 
====================================================================================
4019 
Device utilization summary:
4020 
---------------------------
4021 
 
4022 
Selected Device : 4vlx25sf363-12
4023 
 
4024 
 Number of Slices:                     1338  out of  10752    12%
4025 
 Number of Slice Flip Flops:            722  out of  21504     3%
4026 
 Number of 4 input LUTs:               2394  out of  21504    11%
4027 
 Number of IOs:                          80
4028 
 Number of bonded IOBs:                  80  out of    240    33%
4029 
    IOB Flip Flops:                       8
4030 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4031 
    Number used as RAMB16s:               5
4032 
 Number of GCLKs:                         1  out of     32     3%
4033 
 
4034 
---------------------------
4035 
 
4036 
====================================================================================
4037 
#                            SYNTHESIS DONE
4038 
#####################################################################################
4039 
 
4040 
#####################################################################################
4041 
#                            START SYNTHESIS (AREA optimized)
4042 
#====================================================================================
4043 
# virtex5 (xc5vlx30ff324), speedgrade: -1
4044 
#====================================================================================
4045 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4046 
#     12          10          1         1            1          1            0
4047 
#====================================================================================
4048 
Clock to Setup on destination clock dco_clk
4049 
---------------+---------+---------+---------+---------+
4050 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4051 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4052 
---------------+---------+---------+---------+---------+
4053 
dco_clk        |   20.632|   10.345|         |    0.804|
4054 
---------------+---------+---------+---------+---------+
4055 
 
4056 
====================================================================================
4057 
Device utilization summary:
4058 
---------------------------
4059 
 
4060 
Selected Device : 5vlx30ff324-1
4061 
 
4062 
 
4063 
Slice Logic Utilization:
4064 
 Number of Slice Registers:             721  out of  19200     3%
4065 
 Number of Slice LUTs:                 1832  out of  19200     9%
4066 
    Number used as Logic:              1832  out of  19200     9%
4067 
 
4068 
Slice Logic Distribution:
4069 
 Number of LUT Flip Flop pairs used:   1905
4070 
   Number with an unused Flip Flop:    1184  out of   1905    62%
4071 
   Number with an unused LUT:            73  out of   1905     3%
4072 
   Number of fully used LUT-FF pairs:   648  out of   1905    34%
4073 
   Number of unique control sets:        64
4074 
 
4075 
IO Utilization:
4076 
 Number of IOs:                          80
4077 
 Number of bonded IOBs:                  80  out of    220    36%
4078 
    IOB Flip Flops/Latches:               8
4079 
 
4080 
Specific Feature Utilization:
4081 
 Number of Block RAM/FIFO:                3  out of     32     9%
4082 
    Number using Block RAM only:          3
4083 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4084 
 
4085 
---------------------------
4086 
 
4087 
====================================================================================
4088 
#                            SYNTHESIS DONE
4089 
#####################################################################################
4090 
 
4091 
#####################################################################################
4092 
#                            START SYNTHESIS (AREA optimized)
4093 
#====================================================================================
4094 
# virtex5 (xc5vlx30ff324), speedgrade: -2
4095 
#====================================================================================
4096 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4097 
#     12          10          1         1            1          1            0
4098 
#====================================================================================
4099 
Clock to Setup on destination clock dco_clk
4100 
---------------+---------+---------+---------+---------+
4101 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4102 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4103 
---------------+---------+---------+---------+---------+
4104 
dco_clk        |   17.682|    8.867|         |    0.703|
4105 
---------------+---------+---------+---------+---------+
4106 
 
4107 
====================================================================================
4108 
Device utilization summary:
4109 
---------------------------
4110 
 
4111 
Selected Device : 5vlx30ff324-2
4112 
 
4113 
 
4114 
Slice Logic Utilization:
4115 
 Number of Slice Registers:             721  out of  19200     3%
4116 
 Number of Slice LUTs:                 1831  out of  19200     9%
4117 
    Number used as Logic:              1831  out of  19200     9%
4118 
 
4119 
Slice Logic Distribution:
4120 
 Number of LUT Flip Flop pairs used:   1904
4121 
   Number with an unused Flip Flop:    1183  out of   1904    62%
4122 
   Number with an unused LUT:            73  out of   1904     3%
4123 
   Number of fully used LUT-FF pairs:   648  out of   1904    34%
4124 
   Number of unique control sets:        64
4125 
 
4126 
IO Utilization:
4127 
 Number of IOs:                          80
4128 
 Number of bonded IOBs:                  80  out of    220    36%
4129 
    IOB Flip Flops/Latches:               8
4130 
 
4131 
Specific Feature Utilization:
4132 
 Number of Block RAM/FIFO:                3  out of     32     9%
4133 
    Number using Block RAM only:          3
4134 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4135 
 
4136 
---------------------------
4137 
 
4138 
====================================================================================
4139 
#                            SYNTHESIS DONE
4140 
#####################################################################################
4141 
 
4142 
#####################################################################################
4143 
#                            START SYNTHESIS (AREA optimized)
4144 
#====================================================================================
4145 
# virtex5 (xc5vlx30ff324), speedgrade: -3
4146 
#====================================================================================
4147 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4148 
#     12          10          1         1            1          1            0
4149 
#====================================================================================
4150 
Clock to Setup on destination clock dco_clk
4151 
---------------+---------+---------+---------+---------+
4152 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4153 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4154 
---------------+---------+---------+---------+---------+
4155 
dco_clk        |   16.053|    8.002|         |    0.601|
4156 
---------------+---------+---------+---------+---------+
4157 
 
4158 
====================================================================================
4159 
Device utilization summary:
4160 
---------------------------
4161 
 
4162 
Selected Device : 5vlx30ff324-3
4163 
 
4164 
 
4165 
Slice Logic Utilization:
4166 
 Number of Slice Registers:             721  out of  19200     3%
4167 
 Number of Slice LUTs:                 1831  out of  19200     9%
4168 
    Number used as Logic:              1831  out of  19200     9%
4169 
 
4170 
Slice Logic Distribution:
4171 
 Number of LUT Flip Flop pairs used:   1904
4172 
   Number with an unused Flip Flop:    1183  out of   1904    62%
4173 
   Number with an unused LUT:            73  out of   1904     3%
4174 
   Number of fully used LUT-FF pairs:   648  out of   1904    34%
4175 
   Number of unique control sets:        64
4176 
 
4177 
IO Utilization:
4178 
 Number of IOs:                          80
4179 
 Number of bonded IOBs:                  80  out of    220    36%
4180 
    IOB Flip Flops/Latches:               8
4181 
 
4182 
Specific Feature Utilization:
4183 
 Number of Block RAM/FIFO:                3  out of     32     9%
4184 
    Number using Block RAM only:          3
4185 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4186 
 
4187 
---------------------------
4188 
 
4189 
====================================================================================
4190 
#                            SYNTHESIS DONE
4191 
#####################################################################################
4192 
 
4193 
#####################################################################################
4194 
#                            START SYNTHESIS (AREA optimized)
4195 
#====================================================================================
4196 
# virtex6 (xc6vlx75tff484), speedgrade: -1
4197 
#====================================================================================
4198 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4199 
#     12          10          1         1            1          1            0
4200 
#====================================================================================
4201 
Clock to Setup on destination clock dco_clk
4202 
---------------+---------+---------+---------+---------+
4203 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4204 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4205 
---------------+---------+---------+---------+---------+
4206 
dco_clk        |   18.604|    9.337|    2.737|    0.591|
4207 
---------------+---------+---------+---------+---------+
4208 
 
4209 
====================================================================================
4210 
Device utilization summary:
4211 
---------------------------
4212 
 
4213 
Selected Device : 6vlx75tff484-1
4214 
 
4215 
 
4216 
Slice Logic Utilization:
4217 
 Number of Slice Registers:             721  out of  93120     0%
4218 
 Number of Slice LUTs:                 1818  out of  46560     3%
4219 
    Number used as Logic:              1818  out of  46560     3%
4220 
 
4221 
Slice Logic Distribution:
4222 
 Number of LUT Flip Flop pairs used:   1890
4223 
   Number with an unused Flip Flop:    1169  out of   1890    61%
4224 
   Number with an unused LUT:            72  out of   1890     3%
4225 
   Number of fully used LUT-FF pairs:   649  out of   1890    34%
4226 
   Number of unique control sets:        64
4227 
 
4228 
IO Utilization:
4229 
 Number of IOs:                          80
4230 
 Number of bonded IOBs:                  80  out of    240    33%
4231 
    IOB Flip Flops/Latches:               8
4232 
 
4233 
Specific Feature Utilization:
4234 
 Number of Block RAM/FIFO:                3  out of    156     1%
4235 
    Number using Block RAM only:          3
4236 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4237 
 
4238 
---------------------------
4239 
 
4240 
====================================================================================
4241 
#                            SYNTHESIS DONE
4242 
#####################################################################################
4243 
 
4244 
#####################################################################################
4245 
#                            START SYNTHESIS (AREA optimized)
4246 
#====================================================================================
4247 
# virtex6 (xc6vlx75tff484), speedgrade: -2
4248 
#====================================================================================
4249 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4250 
#     12          10          1         1            1          1            0
4251 
#====================================================================================
4252 
Clock to Setup on destination clock dco_clk
4253 
---------------+---------+---------+---------+---------+
4254 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4255 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4256 
---------------+---------+---------+---------+---------+
4257 
dco_clk        |   17.834|    8.854|    1.885|    0.530|
4258 
---------------+---------+---------+---------+---------+
4259 
 
4260 
====================================================================================
4261 
Device utilization summary:
4262 
---------------------------
4263 
 
4264 
Selected Device : 6vlx75tff484-2
4265 
 
4266 
 
4267 
Slice Logic Utilization:
4268 
 Number of Slice Registers:             721  out of  93120     0%
4269 
 Number of Slice LUTs:                 1816  out of  46560     3%
4270 
    Number used as Logic:              1816  out of  46560     3%
4271 
 
4272 
Slice Logic Distribution:
4273 
 Number of LUT Flip Flop pairs used:   1888
4274 
   Number with an unused Flip Flop:    1167  out of   1888    61%
4275 
   Number with an unused LUT:            72  out of   1888     3%
4276 
   Number of fully used LUT-FF pairs:   649  out of   1888    34%
4277 
   Number of unique control sets:        64
4278 
 
4279 
IO Utilization:
4280 
 Number of IOs:                          80
4281 
 Number of bonded IOBs:                  80  out of    240    33%
4282 
    IOB Flip Flops/Latches:               8
4283 
 
4284 
Specific Feature Utilization:
4285 
 Number of Block RAM/FIFO:                3  out of    156     1%
4286 
    Number using Block RAM only:          3
4287 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4288 
 
4289 
---------------------------
4290 
 
4291 
====================================================================================
4292 
#                            SYNTHESIS DONE
4293 
#####################################################################################
4294 
 
4295 
#####################################################################################
4296 
#                            START SYNTHESIS (AREA optimized)
4297 
#====================================================================================
4298 
# virtex6 (xc6vlx75tff484), speedgrade: -3
4299 
#====================================================================================
4300 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4301 
#     12          10          1         1            1          1            0
4302 
#====================================================================================
4303 
Clock to Setup on destination clock dco_clk
4304 
---------------+---------+---------+---------+---------+
4305 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4306 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4307 
---------------+---------+---------+---------+---------+
4308 
dco_clk        |   14.418|    6.976|    1.945|    0.791|
4309 
---------------+---------+---------+---------+---------+
4310 
 
4311 
====================================================================================
4312 
Device utilization summary:
4313 
---------------------------
4314 
 
4315 
Selected Device : 6vlx75tff484-3
4316 
 
4317 
 
4318 
Slice Logic Utilization:
4319 
 Number of Slice Registers:             721  out of  93120     0%
4320 
 Number of Slice LUTs:                 1815  out of  46560     3%
4321 
    Number used as Logic:              1815  out of  46560     3%
4322 
 
4323 
Slice Logic Distribution:
4324 
 Number of LUT Flip Flop pairs used:   1887
4325 
   Number with an unused Flip Flop:    1166  out of   1887    61%
4326 
   Number with an unused LUT:            72  out of   1887     3%
4327 
   Number of fully used LUT-FF pairs:   649  out of   1887    34%
4328 
   Number of unique control sets:        64
4329 
 
4330 
IO Utilization:
4331 
 Number of IOs:                          80
4332 
 Number of bonded IOBs:                  80  out of    240    33%
4333 
    IOB Flip Flops/Latches:               8
4334 
 
4335 
Specific Feature Utilization:
4336 
 Number of Block RAM/FIFO:                3  out of    156     1%
4337 
    Number using Block RAM only:          3
4338 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4339 
 
4340 
---------------------------
4341 
 
4342 
====================================================================================
4343 
#                            SYNTHESIS DONE
4344 
#####################################################################################
4345 
 
4346 
#####################################################################################
4347 
#                            START SYNTHESIS (AREA optimized)
4348 
#====================================================================================
4349 
# spartan3 (xc3s400pq208), speedgrade: -4
4350 
#====================================================================================
4351 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4352 
#     12          10          1         1            1          1            1
4353 
#====================================================================================
4354 
Clock to Setup on destination clock dco_clk
4355 
---------------+---------+---------+---------+---------+
4356 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4357 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4358 
---------------+---------+---------+---------+---------+
4359 
dco_clk        |   52.228|   25.655|         |    1.564|
4360 
---------------+---------+---------+---------+---------+
4361 
 
4362 
====================================================================================
4363 
Device utilization summary:
4364 
---------------------------
4365 
 
4366 
Selected Device : 3s400pq208-4
4367 
 
4368 
 Number of Slices:                     1370  out of   3584    38%
4369 
 Number of Slice Flip Flops:            763  out of   7168    10%
4370 
 Number of 4 input LUTs:               2458  out of   7168    34%
4371 
 Number of IOs:                          80
4372 
 Number of bonded IOBs:                  80  out of    141    56%
4373 
    IOB Flip Flops:                       8
4374 
 Number of BRAMs:                         6  out of     16    37%
4375 
 Number of GCLKs:                         1  out of      8    12%
4376 
 
4377 
---------------------------
4378 
 
4379 
====================================================================================
4380 
#                            SYNTHESIS DONE
4381 
#####################################################################################
4382 
 
4383 
#####################################################################################
4384 
#                            START SYNTHESIS (AREA optimized)
4385 
#====================================================================================
4386 
# spartan3 (xc3s400pq208), speedgrade: -5
4387 
#====================================================================================
4388 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4389 
#     12          10          1         1            1          1            1
4390 
#====================================================================================
4391 
Clock to Setup on destination clock dco_clk
4392 
---------------+---------+---------+---------+---------+
4393 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4394 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4395 
---------------+---------+---------+---------+---------+
4396 
dco_clk        |   47.015|   21.993|         |    1.361|
4397 
---------------+---------+---------+---------+---------+
4398 
 
4399 
====================================================================================
4400 
Device utilization summary:
4401 
---------------------------
4402 
 
4403 
Selected Device : 3s400pq208-5
4404 
 
4405 
 Number of Slices:                     1371  out of   3584    38%
4406 
 Number of Slice Flip Flops:            763  out of   7168    10%
4407 
 Number of 4 input LUTs:               2459  out of   7168    34%
4408 
 Number of IOs:                          80
4409 
 Number of bonded IOBs:                  80  out of    141    56%
4410 
    IOB Flip Flops:                       8
4411 
 Number of BRAMs:                         6  out of     16    37%
4412 
 Number of GCLKs:                         1  out of      8    12%
4413 
 
4414 
---------------------------
4415 
 
4416 
====================================================================================
4417 
#                            SYNTHESIS DONE
4418 
#####################################################################################
4419 
 
4420 
#####################################################################################
4421 
#                            START SYNTHESIS (AREA optimized)
4422 
#====================================================================================
4423 
# spartan3e (xc3s500epq208), speedgrade: -4
4424 
#====================================================================================
4425 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4426 
#     12          10          1         1            1          1            1
4427 
#====================================================================================
4428 
Clock to Setup on destination clock dco_clk
4429 
---------------+---------+---------+---------+---------+
4430 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4431 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4432 
---------------+---------+---------+---------+---------+
4433 
dco_clk        |   52.731|   25.844|         |    1.649|
4434 
---------------+---------+---------+---------+---------+
4435 
 
4436 
====================================================================================
4437 
Device utilization summary:
4438 
---------------------------
4439 
 
4440 
Selected Device : 3s500epq208-4
4441 
 
4442 
 Number of Slices:                     1380  out of   4656    29%
4443 
 Number of Slice Flip Flops:            763  out of   9312     8%
4444 
 Number of 4 input LUTs:               2474  out of   9312    26%
4445 
 Number of IOs:                          80
4446 
 Number of bonded IOBs:                  80  out of    158    50%
4447 
    IOB Flip Flops:                       8
4448 
 Number of BRAMs:                         6  out of     20    30%
4449 
 Number of GCLKs:                         1  out of     24     4%
4450 
 
4451 
---------------------------
4452 
 
4453 
====================================================================================
4454 
#                            SYNTHESIS DONE
4455 
#####################################################################################
4456 
 
4457 
#####################################################################################
4458 
#                            START SYNTHESIS (AREA optimized)
4459 
#====================================================================================
4460 
# spartan3e (xc3s500epq208), speedgrade: -5
4461 
#====================================================================================
4462 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4463 
#     12          10          1         1            1          1            1
4464 
#====================================================================================
4465 
Clock to Setup on destination clock dco_clk
4466 
---------------+---------+---------+---------+---------+
4467 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4468 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4469 
---------------+---------+---------+---------+---------+
4470 
dco_clk        |   46.301|   22.868|         |    1.276|
4471 
---------------+---------+---------+---------+---------+
4472 
 
4473 
====================================================================================
4474 
Device utilization summary:
4475 
---------------------------
4476 
 
4477 
Selected Device : 3s500epq208-5
4478 
 
4479 
 Number of Slices:                     1380  out of   4656    29%
4480 
 Number of Slice Flip Flops:            763  out of   9312     8%
4481 
 Number of 4 input LUTs:               2474  out of   9312    26%
4482 
 Number of IOs:                          80
4483 
 Number of bonded IOBs:                  80  out of    158    50%
4484 
    IOB Flip Flops:                       8
4485 
 Number of BRAMs:                         6  out of     20    30%
4486 
 Number of GCLKs:                         1  out of     24     4%
4487 
 
4488 
---------------------------
4489 
 
4490 
====================================================================================
4491 
#                            SYNTHESIS DONE
4492 
#####################################################################################
4493 
 
4494 
#####################################################################################
4495 
#                            START SYNTHESIS (AREA optimized)
4496 
#====================================================================================
4497 
# spartan3a (xc3s700aft256), speedgrade: -4
4498 
#====================================================================================
4499 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4500 
#     12          10          1         1            1          1            1
4501 
#====================================================================================
4502 
Clock to Setup on destination clock dco_clk
4503 
---------------+---------+---------+---------+---------+
4504 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4505 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4506 
---------------+---------+---------+---------+---------+
4507 
dco_clk        |   52.651|   26.184|         |    1.448|
4508 
---------------+---------+---------+---------+---------+
4509 
 
4510 
====================================================================================
4511 
Device utilization summary:
4512 
---------------------------
4513 
 
4514 
Selected Device : 3s700aft256-4
4515 
 
4516 
 Number of Slices:                     1389  out of   5888    23%
4517 
 Number of Slice Flip Flops:            764  out of  11776     6%
4518 
 Number of 4 input LUTs:               2489  out of  11776    21%
4519 
 Number of IOs:                          80
4520 
 Number of bonded IOBs:                  80  out of    161    49%
4521 
    IOB Flip Flops:                       8
4522 
 Number of BRAMs:                         5  out of     20    25%
4523 
 Number of GCLKs:                         1  out of     24     4%
4524 
 
4525 
---------------------------
4526 
 
4527 
====================================================================================
4528 
#                            SYNTHESIS DONE
4529 
#####################################################################################
4530 
 
4531 
#####################################################################################
4532 
#                            START SYNTHESIS (AREA optimized)
4533 
#====================================================================================
4534 
# spartan3a (xc3s700aft256), speedgrade: -5
4535 
#====================================================================================
4536 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4537 
#     12          10          1         1            1          1            1
4538 
#====================================================================================
4539 
Clock to Setup on destination clock dco_clk
4540 
---------------+---------+---------+---------+---------+
4541 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4542 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4543 
---------------+---------+---------+---------+---------+
4544 
dco_clk        |   45.027|   22.345|         |    1.192|
4545 
---------------+---------+---------+---------+---------+
4546 
 
4547 
====================================================================================
4548 
Device utilization summary:
4549 
---------------------------
4550 
 
4551 
Selected Device : 3s700aft256-5
4552 
 
4553 
 Number of Slices:                     1385  out of   5888    23%
4554 
 Number of Slice Flip Flops:            764  out of  11776     6%
4555 
 Number of 4 input LUTs:               2483  out of  11776    21%
4556 
 Number of IOs:                          80
4557 
 Number of bonded IOBs:                  80  out of    161    49%
4558 
    IOB Flip Flops:                       8
4559 
 Number of BRAMs:                         5  out of     20    25%
4560 
 Number of GCLKs:                         1  out of     24     4%
4561 
 
4562 
---------------------------
4563 
 
4564 
====================================================================================
4565 
#                            SYNTHESIS DONE
4566 
#####################################################################################
4567 
 
4568 
#####################################################################################
4569 
#                            START SYNTHESIS (AREA optimized)
4570 
#====================================================================================
4571 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
4572 
#====================================================================================
4573 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4574 
#     12          10          1         1            1          1            1
4575 
#====================================================================================
4576 
Clock to Setup on destination clock dco_clk
4577 
---------------+---------+---------+---------+---------+
4578 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4579 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4580 
---------------+---------+---------+---------+---------+
4581 
dco_clk        |   53.430|   26.704|         |    1.448|
4582 
---------------+---------+---------+---------+---------+
4583 
 
4584 
====================================================================================
4585 
Device utilization summary:
4586 
---------------------------
4587 
 
4588 
Selected Device : 3sd1800acs484-4
4589 
 
4590 
 Number of Slices:                     1396  out of  16640     8%
4591 
 Number of Slice Flip Flops:            764  out of  33280     2%
4592 
 Number of 4 input LUTs:               2497  out of  33280     7%
4593 
 Number of IOs:                          80
4594 
 Number of bonded IOBs:                  80  out of    309    25%
4595 
    IOB Flip Flops:                       8
4596 
 Number of BRAMs:                         5  out of     84     5%
4597 
 Number of GCLKs:                         1  out of     24     4%
4598 
 
4599 
---------------------------
4600 
 
4601 
====================================================================================
4602 
#                            SYNTHESIS DONE
4603 
#####################################################################################
4604 
 
4605 
#####################################################################################
4606 
#                            START SYNTHESIS (AREA optimized)
4607 
#====================================================================================
4608 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
4609 
#====================================================================================
4610 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4611 
#     12          10          1         1            1          1            1
4612 
#====================================================================================
4613 
Clock to Setup on destination clock dco_clk
4614 
---------------+---------+---------+---------+---------+
4615 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4616 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4617 
---------------+---------+---------+---------+---------+
4618 
dco_clk        |   43.087|   21.070|         |    1.054|
4619 
---------------+---------+---------+---------+---------+
4620 
 
4621 
====================================================================================
4622 
Device utilization summary:
4623 
---------------------------
4624 
 
4625 
Selected Device : 3sd1800acs484-5
4626 
 
4627 
 Number of Slices:                     1394  out of  16640     8%
4628 
 Number of Slice Flip Flops:            764  out of  33280     2%
4629 
 Number of 4 input LUTs:               2495  out of  33280     7%
4630 
 Number of IOs:                          80
4631 
 Number of bonded IOBs:                  80  out of    309    25%
4632 
    IOB Flip Flops:                       8
4633 
 Number of BRAMs:                         5  out of     84     5%
4634 
 Number of GCLKs:                         1  out of     24     4%
4635 
 
4636 
---------------------------
4637 
 
4638 
====================================================================================
4639 
#                            SYNTHESIS DONE
4640 
#####################################################################################
4641 
 
4642 
#####################################################################################
4643 
#                            START SYNTHESIS (AREA optimized)
4644 
#====================================================================================
4645 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
4646 
#====================================================================================
4647 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4648 
#     12          10          1         1            1          1            1
4649 
#====================================================================================
4650 
Clock to Setup on destination clock dco_clk
4651 
---------------+---------+---------+---------+---------+
4652 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4653 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4654 
---------------+---------+---------+---------+---------+
4655 
dco_clk        |   42.798|   21.477|    4.280|    2.401|
4656 
---------------+---------+---------+---------+---------+
4657 
 
4658 
====================================================================================
4659 
Device utilization summary:
4660 
---------------------------
4661 
 
4662 
Selected Device : 6slx45tfgg484-2
4663 
 
4664 
 
4665 
Slice Logic Utilization:
4666 
 Number of Slice Registers:             764  out of  54576     1%
4667 
 Number of Slice LUTs:                 1905  out of  27288     6%
4668 
    Number used as Logic:              1905  out of  27288     6%
4669 
 
4670 
Slice Logic Distribution:
4671 
 Number of LUT Flip Flop pairs used:   1995
4672 
   Number with an unused Flip Flop:    1231  out of   1995    61%
4673 
   Number with an unused LUT:            90  out of   1995     4%
4674 
   Number of fully used LUT-FF pairs:   674  out of   1995    33%
4675 
   Number of unique control sets:        68
4676 
 
4677 
IO Utilization:
4678 
 Number of IOs:                          80
4679 
 Number of bonded IOBs:                  80  out of    296    27%
4680 
    IOB Flip Flops/Latches:               8
4681 
 
4682 
Specific Feature Utilization:
4683 
 Number of Block RAM/FIFO:                5  out of    348     1%
4684 
    Number using Block RAM only:          5
4685 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
4686 
 
4687 
---------------------------
4688 
 
4689 
====================================================================================
4690 
#                            SYNTHESIS DONE
4691 
#####################################################################################
4692 
 
4693 
#####################################################################################
4694 
#                            START SYNTHESIS (AREA optimized)
4695 
#====================================================================================
4696 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
4697 
#====================================================================================
4698 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4699 
#     12          10          1         1            1          1            1
4700 
#====================================================================================
4701 
Clock to Setup on destination clock dco_clk
4702 
---------------+---------+---------+---------+---------+
4703 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4704 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4705 
---------------+---------+---------+---------+---------+
4706 
dco_clk        |   32.947|   17.341|    4.440|    1.523|
4707 
---------------+---------+---------+---------+---------+
4708 
 
4709 
====================================================================================
4710 
Device utilization summary:
4711 
---------------------------
4712 
 
4713 
Selected Device : 6slx45tfgg484-3
4714 
 
4715 
 
4716 
Slice Logic Utilization:
4717 
 Number of Slice Registers:             764  out of  54576     1%
4718 
 Number of Slice LUTs:                 1876  out of  27288     6%
4719 
    Number used as Logic:              1876  out of  27288     6%
4720 
 
4721 
Slice Logic Distribution:
4722 
 Number of LUT Flip Flop pairs used:   1965
4723 
   Number with an unused Flip Flop:    1201  out of   1965    61%
4724 
   Number with an unused LUT:            89  out of   1965     4%
4725 
   Number of fully used LUT-FF pairs:   675  out of   1965    34%
4726 
   Number of unique control sets:        68
4727 
 
4728 
IO Utilization:
4729 
 Number of IOs:                          80
4730 
 Number of bonded IOBs:                  80  out of    296    27%
4731 
    IOB Flip Flops/Latches:               8
4732 
 
4733 
Specific Feature Utilization:
4734 
 Number of Block RAM/FIFO:                5  out of    348     1%
4735 
    Number using Block RAM only:          5
4736 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
4737 
 
4738 
---------------------------
4739 
 
4740 
====================================================================================
4741 
#                            SYNTHESIS DONE
4742 
#####################################################################################
4743 
 
4744 
#####################################################################################
4745 
#                            START SYNTHESIS (AREA optimized)
4746 
#====================================================================================
4747 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
4748 
#====================================================================================
4749 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4750 
#     12          10          1         1            1          1            1
4751 
#====================================================================================
4752 
Clock to Setup on destination clock dco_clk
4753 
---------------+---------+---------+---------+---------+
4754 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4755 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4756 
---------------+---------+---------+---------+---------+
4757 
dco_clk        |   25.947|   12.651|    2.499|    1.393|
4758 
---------------+---------+---------+---------+---------+
4759 
 
4760 
====================================================================================
4761 
Device utilization summary:
4762 
---------------------------
4763 
 
4764 
Selected Device : 6slx45tfgg484-4
4765 
 
4766 
 
4767 
Slice Logic Utilization:
4768 
 Number of Slice Registers:             764  out of  54576     1%
4769 
 Number of Slice LUTs:                 1873  out of  27288     6%
4770 
    Number used as Logic:              1873  out of  27288     6%
4771 
 
4772 
Slice Logic Distribution:
4773 
 Number of LUT Flip Flop pairs used:   1962
4774 
   Number with an unused Flip Flop:    1198  out of   1962    61%
4775 
   Number with an unused LUT:            89  out of   1962     4%
4776 
   Number of fully used LUT-FF pairs:   675  out of   1962    34%
4777 
   Number of unique control sets:        68
4778 
 
4779 
IO Utilization:
4780 
 Number of IOs:                          80
4781 
 Number of bonded IOBs:                  80  out of    296    27%
4782 
    IOB Flip Flops/Latches:               8
4783 
 
4784 
Specific Feature Utilization:
4785 
 Number of Block RAM/FIFO:                5  out of    348     1%
4786 
    Number using Block RAM only:          5
4787 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
4788 
 
4789 
---------------------------
4790 
 
4791 
====================================================================================
4792 
#                            SYNTHESIS DONE
4793 
#####################################################################################
4794 
 
4795 
#####################################################################################
4796 
#                            START SYNTHESIS (AREA optimized)
4797 
#====================================================================================
4798 
# virtex4 (xc4vlx25sf363), speedgrade: -10
4799 
#====================================================================================
4800 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4801 
#     12          10          1         1            1          1            1
4802 
#====================================================================================
4803 
Clock to Setup on destination clock dco_clk
4804 
---------------+---------+---------+---------+---------+
4805 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4806 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4807 
---------------+---------+---------+---------+---------+
4808 
dco_clk        |   36.919|   17.928|         |    1.112|
4809 
---------------+---------+---------+---------+---------+
4810 
 
4811 
====================================================================================
4812 
Device utilization summary:
4813 
---------------------------
4814 
 
4815 
Selected Device : 4vlx25sf363-10
4816 
 
4817 
 Number of Slices:                     1390  out of  10752    12%
4818 
 Number of Slice Flip Flops:            764  out of  21504     3%
4819 
 Number of 4 input LUTs:               2490  out of  21504    11%
4820 
 Number of IOs:                          80
4821 
 Number of bonded IOBs:                  80  out of    240    33%
4822 
    IOB Flip Flops:                       8
4823 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4824 
    Number used as RAMB16s:               5
4825 
 Number of GCLKs:                         1  out of     32     3%
4826 
 
4827 
---------------------------
4828 
 
4829 
====================================================================================
4830 
#                            SYNTHESIS DONE
4831 
#####################################################################################
4832 
 
4833 
#####################################################################################
4834 
#                            START SYNTHESIS (AREA optimized)
4835 
#====================================================================================
4836 
# virtex4 (xc4vlx25sf363), speedgrade: -11
4837 
#====================================================================================
4838 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4839 
#     12          10          1         1            1          1            1
4840 
#====================================================================================
4841 
Clock to Setup on destination clock dco_clk
4842 
---------------+---------+---------+---------+---------+
4843 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4844 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4845 
---------------+---------+---------+---------+---------+
4846 
dco_clk        |   29.250|   14.353|         |    0.807|
4847 
---------------+---------+---------+---------+---------+
4848 
 
4849 
====================================================================================
4850 
Device utilization summary:
4851 
---------------------------
4852 
 
4853 
Selected Device : 4vlx25sf363-11
4854 
 
4855 
 Number of Slices:                     1390  out of  10752    12%
4856 
 Number of Slice Flip Flops:            764  out of  21504     3%
4857 
 Number of 4 input LUTs:               2491  out of  21504    11%
4858 
 Number of IOs:                          80
4859 
 Number of bonded IOBs:                  80  out of    240    33%
4860 
    IOB Flip Flops:                       8
4861 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4862 
    Number used as RAMB16s:               5
4863 
 Number of GCLKs:                         1  out of     32     3%
4864 
 
4865 
---------------------------
4866 
 
4867 
====================================================================================
4868 
#                            SYNTHESIS DONE
4869 
#####################################################################################
4870 
 
4871 
#####################################################################################
4872 
#                            START SYNTHESIS (AREA optimized)
4873 
#====================================================================================
4874 
# virtex4 (xc4vlx25sf363), speedgrade: -12
4875 
#====================================================================================
4876 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4877 
#     12          10          1         1            1          1            1
4878 
#====================================================================================
4879 
Clock to Setup on destination clock dco_clk
4880 
---------------+---------+---------+---------+---------+
4881 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4882 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4883 
---------------+---------+---------+---------+---------+
4884 
dco_clk        |   27.322|   13.405|         |    0.914|
4885 
---------------+---------+---------+---------+---------+
4886 
 
4887 
====================================================================================
4888 
Device utilization summary:
4889 
---------------------------
4890 
 
4891 
Selected Device : 4vlx25sf363-12
4892 
 
4893 
 Number of Slices:                     1390  out of  10752    12%
4894 
 Number of Slice Flip Flops:            764  out of  21504     3%
4895 
 Number of 4 input LUTs:               2489  out of  21504    11%
4896 
 Number of IOs:                          80
4897 
 Number of bonded IOBs:                  80  out of    240    33%
4898 
    IOB Flip Flops:                       8
4899 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
4900 
    Number used as RAMB16s:               5
4901 
 Number of GCLKs:                         1  out of     32     3%
4902 
 
4903 
---------------------------
4904 
 
4905 
====================================================================================
4906 
#                            SYNTHESIS DONE
4907 
#####################################################################################
4908 
 
4909 
#####################################################################################
4910 
#                            START SYNTHESIS (AREA optimized)
4911 
#====================================================================================
4912 
# virtex5 (xc5vlx30ff324), speedgrade: -1
4913 
#====================================================================================
4914 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4915 
#     12          10          1         1            1          1            1
4916 
#====================================================================================
4917 
Clock to Setup on destination clock dco_clk
4918 
---------------+---------+---------+---------+---------+
4919 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4920 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4921 
---------------+---------+---------+---------+---------+
4922 
dco_clk        |   21.123|   10.740|         |    0.971|
4923 
---------------+---------+---------+---------+---------+
4924 
 
4925 
====================================================================================
4926 
Device utilization summary:
4927 
---------------------------
4928 
 
4929 
Selected Device : 5vlx30ff324-1
4930 
 
4931 
 
4932 
Slice Logic Utilization:
4933 
 Number of Slice Registers:             763  out of  19200     3%
4934 
 Number of Slice LUTs:                 1881  out of  19200     9%
4935 
    Number used as Logic:              1881  out of  19200     9%
4936 
 
4937 
Slice Logic Distribution:
4938 
 Number of LUT Flip Flop pairs used:   1968
4939 
   Number with an unused Flip Flop:    1205  out of   1968    61%
4940 
   Number with an unused LUT:            87  out of   1968     4%
4941 
   Number of fully used LUT-FF pairs:   676  out of   1968    34%
4942 
   Number of unique control sets:        67
4943 
 
4944 
IO Utilization:
4945 
 Number of IOs:                          80
4946 
 Number of bonded IOBs:                  80  out of    220    36%
4947 
    IOB Flip Flops/Latches:               8
4948 
 
4949 
Specific Feature Utilization:
4950 
 Number of Block RAM/FIFO:                3  out of     32     9%
4951 
    Number using Block RAM only:          3
4952 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
4953 
 
4954 
---------------------------
4955 
 
4956 
====================================================================================
4957 
#                            SYNTHESIS DONE
4958 
#####################################################################################
4959 
 
4960 
#####################################################################################
4961 
#                            START SYNTHESIS (AREA optimized)
4962 
#====================================================================================
4963 
# virtex5 (xc5vlx30ff324), speedgrade: -2
4964 
#====================================================================================
4965 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
4966 
#     12          10          1         1            1          1            1
4967 
#====================================================================================
4968 
Clock to Setup on destination clock dco_clk
4969 
---------------+---------+---------+---------+---------+
4970 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
4971 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
4972 
---------------+---------+---------+---------+---------+
4973 
dco_clk        |   17.586|    8.843|         |    0.688|
4974 
---------------+---------+---------+---------+---------+
4975 
 
4976 
====================================================================================
4977 
Device utilization summary:
4978 
---------------------------
4979 
 
4980 
Selected Device : 5vlx30ff324-2
4981 
 
4982 
 
4983 
Slice Logic Utilization:
4984 
 Number of Slice Registers:             763  out of  19200     3%
4985 
 Number of Slice LUTs:                 1881  out of  19200     9%
4986 
    Number used as Logic:              1881  out of  19200     9%
4987 
 
4988 
Slice Logic Distribution:
4989 
 Number of LUT Flip Flop pairs used:   1968
4990 
   Number with an unused Flip Flop:    1205  out of   1968    61%
4991 
   Number with an unused LUT:            87  out of   1968     4%
4992 
   Number of fully used LUT-FF pairs:   676  out of   1968    34%
4993 
   Number of unique control sets:        67
4994 
 
4995 
IO Utilization:
4996 
 Number of IOs:                          80
4997 
 Number of bonded IOBs:                  80  out of    220    36%
4998 
    IOB Flip Flops/Latches:               8
4999 
 
5000 
Specific Feature Utilization:
5001 
 Number of Block RAM/FIFO:                3  out of     32     9%
5002 
    Number using Block RAM only:          3
5003 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5004 
 
5005 
---------------------------
5006 
 
5007 
====================================================================================
5008 
#                            SYNTHESIS DONE
5009 
#####################################################################################
5010 
 
5011 
#####################################################################################
5012 
#                            START SYNTHESIS (AREA optimized)
5013 
#====================================================================================
5014 
# virtex5 (xc5vlx30ff324), speedgrade: -3
5015 
#====================================================================================
5016 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
5017 
#     12          10          1         1            1          1            1
5018 
#====================================================================================
5019 
Clock to Setup on destination clock dco_clk
5020 
---------------+---------+---------+---------+---------+
5021 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
5022 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
5023 
---------------+---------+---------+---------+---------+
5024 
dco_clk        |   16.288|    8.115|         |    0.641|
5025 
---------------+---------+---------+---------+---------+
5026 
 
5027 
====================================================================================
5028 
Device utilization summary:
5029 
---------------------------
5030 
 
5031 
Selected Device : 5vlx30ff324-3
5032 
 
5033 
 
5034 
Slice Logic Utilization:
5035 
 Number of Slice Registers:             763  out of  19200     3%
5036 
 Number of Slice LUTs:                 1882  out of  19200     9%
5037 
    Number used as Logic:              1882  out of  19200     9%
5038 
 
5039 
Slice Logic Distribution:
5040 
 Number of LUT Flip Flop pairs used:   1969
5041 
   Number with an unused Flip Flop:    1206  out of   1969    61%
5042 
   Number with an unused LUT:            87  out of   1969     4%
5043 
   Number of fully used LUT-FF pairs:   676  out of   1969    34%
5044 
   Number of unique control sets:        67
5045 
 
5046 
IO Utilization:
5047 
 Number of IOs:                          80
5048 
 Number of bonded IOBs:                  80  out of    220    36%
5049 
    IOB Flip Flops/Latches:               8
5050 
 
5051 
Specific Feature Utilization:
5052 
 Number of Block RAM/FIFO:                3  out of     32     9%
5053 
    Number using Block RAM only:          3
5054 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5055 
 
5056 
---------------------------
5057 
 
5058 
====================================================================================
5059 
#                            SYNTHESIS DONE
5060 
#####################################################################################
5061 
 
5062 
#####################################################################################
5063 
#                            START SYNTHESIS (AREA optimized)
5064 
#====================================================================================
5065 
# virtex6 (xc6vlx75tff484), speedgrade: -1
5066 
#====================================================================================
5067 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
5068 
#     12          10          1         1            1          1            1
5069 
#====================================================================================
5070 
Clock to Setup on destination clock dco_clk
5071 
---------------+---------+---------+---------+---------+
5072 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
5073 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
5074 
---------------+---------+---------+---------+---------+
5075 
dco_clk        |   18.783|    9.311|    2.378|    0.606|
5076 
---------------+---------+---------+---------+---------+
5077 
 
5078 
====================================================================================
5079 
Device utilization summary:
5080 
---------------------------
5081 
 
5082 
Selected Device : 6vlx75tff484-1
5083 
 
5084 
 
5085 
Slice Logic Utilization:
5086 
 Number of Slice Registers:             763  out of  93120     0%
5087 
 Number of Slice LUTs:                 1866  out of  46560     4%
5088 
    Number used as Logic:              1866  out of  46560     4%
5089 
 
5090 
Slice Logic Distribution:
5091 
 Number of LUT Flip Flop pairs used:   1954
5092 
   Number with an unused Flip Flop:    1191  out of   1954    60%
5093 
   Number with an unused LUT:            88  out of   1954     4%
5094 
   Number of fully used LUT-FF pairs:   675  out of   1954    34%
5095 
   Number of unique control sets:        67
5096 
 
5097 
IO Utilization:
5098 
 Number of IOs:                          80
5099 
 Number of bonded IOBs:                  80  out of    240    33%
5100 
    IOB Flip Flops/Latches:               8
5101 
 
5102 
Specific Feature Utilization:
5103 
 Number of Block RAM/FIFO:                3  out of    156     1%
5104 
    Number using Block RAM only:          3
5105 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5106 
 
5107 
---------------------------
5108 
 
5109 
====================================================================================
5110 
#                            SYNTHESIS DONE
5111 
#####################################################################################
5112 
 
5113 
#####################################################################################
5114 
#                            START SYNTHESIS (AREA optimized)
5115 
#====================================================================================
5116 
# virtex6 (xc6vlx75tff484), speedgrade: -2
5117 
#====================================================================================
5118 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
5119 
#     12          10          1         1            1          1            1
5120 
#====================================================================================
5121 
Clock to Setup on destination clock dco_clk
5122 
---------------+---------+---------+---------+---------+
5123 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
5124 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
5125 
---------------+---------+---------+---------+---------+
5126 
dco_clk        |   16.497|    8.056|    2.484|    0.530|
5127 
---------------+---------+---------+---------+---------+
5128 
 
5129 
====================================================================================
5130 
Device utilization summary:
5131 
---------------------------
5132 
 
5133 
Selected Device : 6vlx75tff484-2
5134 
 
5135 
 
5136 
Slice Logic Utilization:
5137 
 Number of Slice Registers:             763  out of  93120     0%
5138 
 Number of Slice LUTs:                 1860  out of  46560     3%
5139 
    Number used as Logic:              1860  out of  46560     3%
5140 
 
5141 
Slice Logic Distribution:
5142 
 Number of LUT Flip Flop pairs used:   1948
5143 
   Number with an unused Flip Flop:    1185  out of   1948    60%
5144 
   Number with an unused LUT:            88  out of   1948     4%
5145 
   Number of fully used LUT-FF pairs:   675  out of   1948    34%
5146 
   Number of unique control sets:        67
5147 
 
5148 
IO Utilization:
5149 
 Number of IOs:                          80
5150 
 Number of bonded IOBs:                  80  out of    240    33%
5151 
    IOB Flip Flops/Latches:               8
5152 
 
5153 
Specific Feature Utilization:
5154 
 Number of Block RAM/FIFO:                3  out of    156     1%
5155 
    Number using Block RAM only:          3
5156 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5157 
 
5158 
---------------------------
5159 
 
5160 
====================================================================================
5161 
#                            SYNTHESIS DONE
5162 
#####################################################################################
5163 
 
5164 
#####################################################################################
5165 
#                            START SYNTHESIS (AREA optimized)
5166 
#====================================================================================
5167 
# virtex6 (xc6vlx75tff484), speedgrade: -3
5168 
#====================================================================================
5169 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3
5170 
#     12          10          1         1            1          1            1
5171 
#====================================================================================
5172 
Clock to Setup on destination clock dco_clk
5173 
---------------+---------+---------+---------+---------+
5174 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
5175 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
5176 
---------------+---------+---------+---------+---------+
5177 
dco_clk        |   15.988|    8.110|    1.485|    0.729|
5178 
---------------+---------+---------+---------+---------+
5179 
 
5180 
====================================================================================
5181 
Device utilization summary:
5182 
---------------------------
5183 
 
5184 
Selected Device : 6vlx75tff484-3
5185 
 
5186 
 
5187 
Slice Logic Utilization:
5188 
 Number of Slice Registers:             763  out of  93120     0%
5189 
 Number of Slice LUTs:                 1860  out of  46560     3%
5190 
    Number used as Logic:              1860  out of  46560     3%
5191 
 
5192 
Slice Logic Distribution:
5193 
 Number of LUT Flip Flop pairs used:   1948
5194 
   Number with an unused Flip Flop:    1185  out of   1948    60%
5195 
   Number with an unused LUT:            88  out of   1948     4%
5196 
   Number of fully used LUT-FF pairs:   675  out of   1948    34%
5197 
   Number of unique control sets:        67
5198 
 
5199 
IO Utilization:
5200 
 Number of IOs:                          80
5201 
 Number of bonded IOBs:                  80  out of    240    33%
5202 
    IOB Flip Flops/Latches:               8
5203 
 
5204 
Specific Feature Utilization:
5205 
 Number of Block RAM/FIFO:                3  out of    156     1%
5206 
    Number using Block RAM only:          3
5207 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
5208 
 
5209 
---------------------------
5210 
 
5211 
====================================================================================
5212 
#                            SYNTHESIS DONE
5213 
#####################################################################################
5214 
 

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