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[/] [openmsp430/] [trunk/] [core/] [synthesis/] [xilinx/] [run_analysis.area.mpy.log] - Blame information for rev 68

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Line No. Rev Author Line
1 68 olivier.gi 
#####################################################################################
2 
#                            START SYNTHESIS (AREA optimized)
3 
#====================================================================================
4 
# spartan3 (xc3s400pq208), speedgrade: -4
5 
#====================================================================================
6 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
7 
#     12          10          0         0            0          0            0         1
8 
#====================================================================================
9 
Clock to Setup on destination clock dco_clk
10 
---------------+---------+---------+---------+---------+
11 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
12 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
13 
---------------+---------+---------+---------+---------+
14 
dco_clk        |   36.357|         |         |    1.641|
15 
---------------+---------+---------+---------+---------+
16 
 
17 
====================================================================================
18 
Device utilization summary:
19 
---------------------------
20 
 
21 
Selected Device : 3s400pq208-4
22 
 
23 
 Number of Slices:                     1008  out of   3584    28%
24 
 Number of Slice Flip Flops:            533  out of   7168     7%
25 
 Number of 4 input LUTs:               1811  out of   7168    25%
26 
 Number of IOs:                          80
27 
 Number of bonded IOBs:                  79  out of    141    56%
28 
    IOB Flip Flops:                      10
29 
 Number of BRAMs:                         6  out of     16    37%
30 
 Number of MULT18X18s:                    1  out of     16     6%
31 
 Number of GCLKs:                         1  out of      8    12%
32 
 
33 
---------------------------
34 
 
35 
====================================================================================
36 
#                            SYNTHESIS DONE
37 
#####################################################################################
38 
 
39 
#####################################################################################
40 
#                            START SYNTHESIS (AREA optimized)
41 
#====================================================================================
42 
# spartan3 (xc3s400pq208), speedgrade: -5
43 
#====================================================================================
44 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
45 
#     12          10          0         0            0          0            0         1
46 
#====================================================================================
47 
Clock to Setup on destination clock dco_clk
48 
---------------+---------+---------+---------+---------+
49 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
50 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
51 
---------------+---------+---------+---------+---------+
52 
dco_clk        |   33.554|         |         |    1.468|
53 
---------------+---------+---------+---------+---------+
54 
 
55 
====================================================================================
56 
Device utilization summary:
57 
---------------------------
58 
 
59 
Selected Device : 3s400pq208-5
60 
 
61 
 Number of Slices:                     1008  out of   3584    28%
62 
 Number of Slice Flip Flops:            533  out of   7168     7%
63 
 Number of 4 input LUTs:               1811  out of   7168    25%
64 
 Number of IOs:                          80
65 
 Number of bonded IOBs:                  79  out of    141    56%
66 
    IOB Flip Flops:                      10
67 
 Number of BRAMs:                         6  out of     16    37%
68 
 Number of MULT18X18s:                    1  out of     16     6%
69 
 Number of GCLKs:                         1  out of      8    12%
70 
 
71 
---------------------------
72 
 
73 
====================================================================================
74 
#                            SYNTHESIS DONE
75 
#####################################################################################
76 
 
77 
#####################################################################################
78 
#                            START SYNTHESIS (AREA optimized)
79 
#====================================================================================
80 
# spartan3e (xc3s500epq208), speedgrade: -4
81 
#====================================================================================
82 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
83 
#     12          10          0         0            0          0            0         1
84 
#====================================================================================
85 
Clock to Setup on destination clock dco_clk
86 
---------------+---------+---------+---------+---------+
87 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
88 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
89 
---------------+---------+---------+---------+---------+
90 
dco_clk        |   35.454|         |         |    2.328|
91 
---------------+---------+---------+---------+---------+
92 
 
93 
====================================================================================
94 
Device utilization summary:
95 
---------------------------
96 
 
97 
Selected Device : 3s500epq208-4
98 
 
99 
 Number of Slices:                     1013  out of   4656    21%
100 
 Number of Slice Flip Flops:            533  out of   9312     5%
101 
 Number of 4 input LUTs:               1816  out of   9312    19%
102 
 Number of IOs:                          80
103 
 Number of bonded IOBs:                  79  out of    158    50%
104 
    IOB Flip Flops:                      10
105 
 Number of BRAMs:                         6  out of     20    30%
106 
 Number of MULT18X18SIOs:                 1  out of     20     5%
107 
 Number of GCLKs:                         1  out of     24     4%
108 
 
109 
---------------------------
110 
 
111 
====================================================================================
112 
#                            SYNTHESIS DONE
113 
#####################################################################################
114 
 
115 
#####################################################################################
116 
#                            START SYNTHESIS (AREA optimized)
117 
#====================================================================================
118 
# spartan3e (xc3s500epq208), speedgrade: -5
119 
#====================================================================================
120 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
121 
#     12          10          0         0            0          0            0         1
122 
#====================================================================================
123 
Clock to Setup on destination clock dco_clk
124 
---------------+---------+---------+---------+---------+
125 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
126 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
127 
---------------+---------+---------+---------+---------+
128 
dco_clk        |   30.742|         |         |    1.538|
129 
---------------+---------+---------+---------+---------+
130 
 
131 
====================================================================================
132 
Device utilization summary:
133 
---------------------------
134 
 
135 
Selected Device : 3s500epq208-5
136 
 
137 
 Number of Slices:                     1013  out of   4656    21%
138 
 Number of Slice Flip Flops:            533  out of   9312     5%
139 
 Number of 4 input LUTs:               1816  out of   9312    19%
140 
 Number of IOs:                          80
141 
 Number of bonded IOBs:                  79  out of    158    50%
142 
    IOB Flip Flops:                      10
143 
 Number of BRAMs:                         6  out of     20    30%
144 
 Number of MULT18X18SIOs:                 1  out of     20     5%
145 
 Number of GCLKs:                         1  out of     24     4%
146 
 
147 
---------------------------
148 
 
149 
====================================================================================
150 
#                            SYNTHESIS DONE
151 
#####################################################################################
152 
 
153 
#####################################################################################
154 
#                            START SYNTHESIS (AREA optimized)
155 
#====================================================================================
156 
# spartan3a (xc3s700aft256), speedgrade: -4
157 
#====================================================================================
158 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
159 
#     12          10          0         0            0          0            0         1
160 
#====================================================================================
161 
Clock to Setup on destination clock dco_clk
162 
---------------+---------+---------+---------+---------+
163 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
164 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
165 
---------------+---------+---------+---------+---------+
166 
dco_clk        |   39.532|         |         |    1.688|
167 
---------------+---------+---------+---------+---------+
168 
 
169 
====================================================================================
170 
Device utilization summary:
171 
---------------------------
172 
 
173 
Selected Device : 3s700aft256-4
174 
 
175 
 Number of Slices:                     1022  out of   5888    17%
176 
 Number of Slice Flip Flops:            534  out of  11776     4%
177 
 Number of 4 input LUTs:               1832  out of  11776    15%
178 
 Number of IOs:                          80
179 
 Number of bonded IOBs:                  79  out of    161    49%
180 
    IOB Flip Flops:                      10
181 
 Number of BRAMs:                         5  out of     20    25%
182 
 Number of MULT18X18SIOs:                 1  out of     20     5%
183 
 Number of GCLKs:                         1  out of     24     4%
184 
 
185 
---------------------------
186 
 
187 
====================================================================================
188 
#                            SYNTHESIS DONE
189 
#####################################################################################
190 
 
191 
#####################################################################################
192 
#                            START SYNTHESIS (AREA optimized)
193 
#====================================================================================
194 
# spartan3a (xc3s700aft256), speedgrade: -5
195 
#====================================================================================
196 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
197 
#     12          10          0         0            0          0            0         1
198 
#====================================================================================
199 
Clock to Setup on destination clock dco_clk
200 
---------------+---------+---------+---------+---------+
201 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
202 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
203 
---------------+---------+---------+---------+---------+
204 
dco_clk        |   30.273|         |         |    1.532|
205 
---------------+---------+---------+---------+---------+
206 
 
207 
====================================================================================
208 
Device utilization summary:
209 
---------------------------
210 
 
211 
Selected Device : 3s700aft256-5
212 
 
213 
 Number of Slices:                     1020  out of   5888    17%
214 
 Number of Slice Flip Flops:            534  out of  11776     4%
215 
 Number of 4 input LUTs:               1827  out of  11776    15%
216 
 Number of IOs:                          80
217 
 Number of bonded IOBs:                  79  out of    161    49%
218 
    IOB Flip Flops:                      10
219 
 Number of BRAMs:                         5  out of     20    25%
220 
 Number of MULT18X18SIOs:                 1  out of     20     5%
221 
 Number of GCLKs:                         1  out of     24     4%
222 
 
223 
---------------------------
224 
 
225 
====================================================================================
226 
#                            SYNTHESIS DONE
227 
#####################################################################################
228 
 
229 
#####################################################################################
230 
#                            START SYNTHESIS (AREA optimized)
231 
#====================================================================================
232 
# spartan3adsp (xc3sd1800acs484), speedgrade: -4
233 
#====================================================================================
234 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
235 
#     12          10          0         0            0          0            0         1
236 
#====================================================================================
237 
Clock to Setup on destination clock dco_clk
238 
---------------+---------+---------+---------+---------+
239 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
240 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
241 
---------------+---------+---------+---------+---------+
242 
dco_clk        |   36.164|         |         |    1.777|
243 
---------------+---------+---------+---------+---------+
244 
 
245 
====================================================================================
246 
Device utilization summary:
247 
---------------------------
248 
 
249 
Selected Device : 3sd1800acs484-4
250 
 
251 
 Number of Slices:                     1024  out of  16640     6%
252 
 Number of Slice Flip Flops:            534  out of  33280     1%
253 
 Number of 4 input LUTs:               1831  out of  33280     5%
254 
 Number of IOs:                          80
255 
 Number of bonded IOBs:                  79  out of    309    25%
256 
    IOB Flip Flops:                      10
257 
 Number of BRAMs:                         5  out of     84     5%
258 
 Number of GCLKs:                         1  out of     24     4%
259 
 Number of DSP48s:                        1  out of     84     1%
260 
 
261 
---------------------------
262 
 
263 
====================================================================================
264 
#                            SYNTHESIS DONE
265 
#####################################################################################
266 
 
267 
#####################################################################################
268 
#                            START SYNTHESIS (AREA optimized)
269 
#====================================================================================
270 
# spartan3adsp (xc3sd1800acs484), speedgrade: -5
271 
#====================================================================================
272 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
273 
#     12          10          0         0            0          0            0         1
274 
#====================================================================================
275 
Clock to Setup on destination clock dco_clk
276 
---------------+---------+---------+---------+---------+
277 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
278 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
279 
---------------+---------+---------+---------+---------+
280 
dco_clk        |   28.990|         |         |    1.440|
281 
---------------+---------+---------+---------+---------+
282 
 
283 
====================================================================================
284 
Device utilization summary:
285 
---------------------------
286 
 
287 
Selected Device : 3sd1800acs484-5
288 
 
289 
 Number of Slices:                     1022  out of  16640     6%
290 
 Number of Slice Flip Flops:            534  out of  33280     1%
291 
 Number of 4 input LUTs:               1826  out of  33280     5%
292 
 Number of IOs:                          80
293 
 Number of bonded IOBs:                  79  out of    309    25%
294 
    IOB Flip Flops:                      10
295 
 Number of BRAMs:                         5  out of     84     5%
296 
 Number of GCLKs:                         1  out of     24     4%
297 
 Number of DSP48s:                        1  out of     84     1%
298 
 
299 
---------------------------
300 
 
301 
====================================================================================
302 
#                            SYNTHESIS DONE
303 
#####################################################################################
304 
 
305 
#####################################################################################
306 
#                            START SYNTHESIS (AREA optimized)
307 
#====================================================================================
308 
# spartan6 (xc6slx45tfgg484), speedgrade: -2
309 
#====================================================================================
310 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
311 
#     12          10          0         0            0          0            0         1
312 
#====================================================================================
313 
Clock to Setup on destination clock dco_clk
314 
---------------+---------+---------+---------+---------+
315 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
316 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
317 
---------------+---------+---------+---------+---------+
318 
dco_clk        |   29.715|    5.512|    2.728|    2.769|
319 
---------------+---------+---------+---------+---------+
320 
 
321 
====================================================================================
322 
Device utilization summary:
323 
---------------------------
324 
 
325 
Selected Device : 6slx45tfgg484-2
326 
 
327 
 
328 
Slice Logic Utilization:
329 
 Number of Slice Registers:             533  out of  54576     0%
330 
 Number of Slice LUTs:                 1436  out of  27288     5%
331 
    Number used as Logic:              1436  out of  27288     5%
332 
 
333 
Slice Logic Distribution:
334 
 Number of LUT Flip Flop pairs used:   1466
335 
   Number with an unused Flip Flop:     933  out of   1466    63%
336 
   Number with an unused LUT:            30  out of   1466     2%
337 
   Number of fully used LUT-FF pairs:   503  out of   1466    34%
338 
   Number of unique control sets:        50
339 
 
340 
IO Utilization:
341 
 Number of IOs:                          80
342 
 Number of bonded IOBs:                  79  out of    296    26%
343 
    IOB Flip Flops/Latches:              10
344 
 
345 
Specific Feature Utilization:
346 
 Number of Block RAM/FIFO:                5  out of    348     1%
347 
    Number using Block RAM only:          5
348 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
349 
 Number of DSP48A1s:                      1  out of     58     1%
350 
 
351 
---------------------------
352 
 
353 
====================================================================================
354 
#                            SYNTHESIS DONE
355 
#####################################################################################
356 
 
357 
#####################################################################################
358 
#                            START SYNTHESIS (AREA optimized)
359 
#====================================================================================
360 
# spartan6 (xc6slx45tfgg484), speedgrade: -3
361 
#====================================================================================
362 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
363 
#     12          10          0         0            0          0            0         1
364 
#====================================================================================
365 
Clock to Setup on destination clock dco_clk
366 
---------------+---------+---------+---------+---------+
367 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
368 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
369 
---------------+---------+---------+---------+---------+
370 
dco_clk        |   23.010|    5.235|    2.087|    2.062|
371 
---------------+---------+---------+---------+---------+
372 
 
373 
====================================================================================
374 
Device utilization summary:
375 
---------------------------
376 
 
377 
Selected Device : 6slx45tfgg484-3
378 
 
379 
 
380 
Slice Logic Utilization:
381 
 Number of Slice Registers:             533  out of  54576     0%
382 
 Number of Slice LUTs:                 1425  out of  27288     5%
383 
    Number used as Logic:              1425  out of  27288     5%
384 
 
385 
Slice Logic Distribution:
386 
 Number of LUT Flip Flop pairs used:   1452
387 
   Number with an unused Flip Flop:     919  out of   1452    63%
388 
   Number with an unused LUT:            27  out of   1452     1%
389 
   Number of fully used LUT-FF pairs:   506  out of   1452    34%
390 
   Number of unique control sets:        50
391 
 
392 
IO Utilization:
393 
 Number of IOs:                          80
394 
 Number of bonded IOBs:                  79  out of    296    26%
395 
    IOB Flip Flops/Latches:              10
396 
 
397 
Specific Feature Utilization:
398 
 Number of Block RAM/FIFO:                5  out of    348     1%
399 
    Number using Block RAM only:          5
400 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
401 
 Number of DSP48A1s:                      1  out of     58     1%
402 
 
403 
---------------------------
404 
 
405 
====================================================================================
406 
#                            SYNTHESIS DONE
407 
#####################################################################################
408 
 
409 
#####################################################################################
410 
#                            START SYNTHESIS (AREA optimized)
411 
#====================================================================================
412 
# spartan6 (xc6slx45tfgg484), speedgrade: -4
413 
#====================================================================================
414 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
415 
#     12          10          0         0            0          0            0         1
416 
#====================================================================================
417 
Clock to Setup on destination clock dco_clk
418 
---------------+---------+---------+---------+---------+
419 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
420 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
421 
---------------+---------+---------+---------+---------+
422 
dco_clk        |   19.001|    4.893|    1.806|    1.570|
423 
---------------+---------+---------+---------+---------+
424 
 
425 
====================================================================================
426 
Device utilization summary:
427 
---------------------------
428 
 
429 
Selected Device : 6slx45tfgg484-4
430 
 
431 
 
432 
Slice Logic Utilization:
433 
 Number of Slice Registers:             533  out of  54576     0%
434 
 Number of Slice LUTs:                 1424  out of  27288     5%
435 
    Number used as Logic:              1424  out of  27288     5%
436 
 
437 
Slice Logic Distribution:
438 
 Number of LUT Flip Flop pairs used:   1451
439 
   Number with an unused Flip Flop:     918  out of   1451    63%
440 
   Number with an unused LUT:            27  out of   1451     1%
441 
   Number of fully used LUT-FF pairs:   506  out of   1451    34%
442 
   Number of unique control sets:        50
443 
 
444 
IO Utilization:
445 
 Number of IOs:                          80
446 
 Number of bonded IOBs:                  79  out of    296    26%
447 
    IOB Flip Flops/Latches:              10
448 
 
449 
Specific Feature Utilization:
450 
 Number of Block RAM/FIFO:                5  out of    348     1%
451 
    Number using Block RAM only:          5
452 
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%
453 
 Number of DSP48A1s:                      1  out of     58     1%
454 
 
455 
---------------------------
456 
 
457 
====================================================================================
458 
#                            SYNTHESIS DONE
459 
#####################################################################################
460 
 
461 
#####################################################################################
462 
#                            START SYNTHESIS (AREA optimized)
463 
#====================================================================================
464 
# virtex4 (xc4vlx25sf363), speedgrade: -10
465 
#====================================================================================
466 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
467 
#     12          10          0         0            0          0            0         1
468 
#====================================================================================
469 
Clock to Setup on destination clock dco_clk
470 
---------------+---------+---------+---------+---------+
471 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
472 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
473 
---------------+---------+---------+---------+---------+
474 
dco_clk        |   23.262|         |         |    0.954|
475 
---------------+---------+---------+---------+---------+
476 
 
477 
====================================================================================
478 
Device utilization summary:
479 
---------------------------
480 
 
481 
Selected Device : 4vlx25sf363-10
482 
 
483 
 Number of Slices:                     1021  out of  10752     9%
484 
 Number of Slice Flip Flops:            534  out of  21504     2%
485 
 Number of 4 input LUTs:               1829  out of  21504     8%
486 
 Number of IOs:                          80
487 
 Number of bonded IOBs:                  79  out of    240    32%
488 
    IOB Flip Flops:                      10
489 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
490 
    Number used as RAMB16s:               5
491 
 Number of GCLKs:                         1  out of     32     3%
492 
 Number of DSP48s:                        1  out of     48     2%
493 
 
494 
---------------------------
495 
 
496 
====================================================================================
497 
#                            SYNTHESIS DONE
498 
#####################################################################################
499 
 
500 
#####################################################################################
501 
#                            START SYNTHESIS (AREA optimized)
502 
#====================================================================================
503 
# virtex4 (xc4vlx25sf363), speedgrade: -11
504 
#====================================================================================
505 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
506 
#     12          10          0         0            0          0            0         1
507 
#====================================================================================
508 
Clock to Setup on destination clock dco_clk
509 
---------------+---------+---------+---------+---------+
510 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
511 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
512 
---------------+---------+---------+---------+---------+
513 
dco_clk        |   21.546|         |         |    0.850|
514 
---------------+---------+---------+---------+---------+
515 
 
516 
====================================================================================
517 
Device utilization summary:
518 
---------------------------
519 
 
520 
Selected Device : 4vlx25sf363-11
521 
 
522 
 Number of Slices:                     1015  out of  10752     9%
523 
 Number of Slice Flip Flops:            534  out of  21504     2%
524 
 Number of 4 input LUTs:               1810  out of  21504     8%
525 
 Number of IOs:                          80
526 
 Number of bonded IOBs:                  79  out of    240    32%
527 
    IOB Flip Flops:                      10
528 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
529 
    Number used as RAMB16s:               5
530 
 Number of GCLKs:                         1  out of     32     3%
531 
 Number of DSP48s:                        1  out of     48     2%
532 
 
533 
---------------------------
534 
 
535 
====================================================================================
536 
#                            SYNTHESIS DONE
537 
#####################################################################################
538 
 
539 
#####################################################################################
540 
#                            START SYNTHESIS (AREA optimized)
541 
#====================================================================================
542 
# virtex4 (xc4vlx25sf363), speedgrade: -12
543 
#====================================================================================
544 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
545 
#     12          10          0         0            0          0            0         1
546 
#====================================================================================
547 
Clock to Setup on destination clock dco_clk
548 
---------------+---------+---------+---------+---------+
549 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
550 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
551 
---------------+---------+---------+---------+---------+
552 
dco_clk        |   18.274|         |         |    0.914|
553 
---------------+---------+---------+---------+---------+
554 
 
555 
====================================================================================
556 
Device utilization summary:
557 
---------------------------
558 
 
559 
Selected Device : 4vlx25sf363-12
560 
 
561 
 Number of Slices:                     1018  out of  10752     9%
562 
 Number of Slice Flip Flops:            534  out of  21504     2%
563 
 Number of 4 input LUTs:               1819  out of  21504     8%
564 
 Number of IOs:                          80
565 
 Number of bonded IOBs:                  79  out of    240    32%
566 
    IOB Flip Flops:                      10
567 
 Number of FIFO16/RAMB16s:                5  out of     72     6%
568 
    Number used as RAMB16s:               5
569 
 Number of GCLKs:                         1  out of     32     3%
570 
 Number of DSP48s:                        1  out of     48     2%
571 
 
572 
---------------------------
573 
 
574 
====================================================================================
575 
#                            SYNTHESIS DONE
576 
#####################################################################################
577 
 
578 
#####################################################################################
579 
#                            START SYNTHESIS (AREA optimized)
580 
#====================================================================================
581 
# virtex5 (xc5vlx30ff324), speedgrade: -1
582 
#====================================================================================
583 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
584 
#     12          10          0         0            0          0            0         1
585 
#====================================================================================
586 
Clock to Setup on destination clock dco_clk
587 
---------------+---------+---------+---------+---------+
588 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
589 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
590 
---------------+---------+---------+---------+---------+
591 
dco_clk        |   16.985|         |         |    0.781|
592 
---------------+---------+---------+---------+---------+
593 
 
594 
====================================================================================
595 
Device utilization summary:
596 
---------------------------
597 
 
598 
Selected Device : 5vlx30ff324-1
599 
 
600 
 
601 
Slice Logic Utilization:
602 
 Number of Slice Registers:             532  out of  19200     2%
603 
 Number of Slice LUTs:                 1372  out of  19200     7%
604 
    Number used as Logic:              1372  out of  19200     7%
605 
 
606 
Slice Logic Distribution:
607 
 Number of LUT Flip Flop pairs used:   1398
608 
   Number with an unused Flip Flop:     866  out of   1398    61%
609 
   Number with an unused LUT:            26  out of   1398     1%
610 
   Number of fully used LUT-FF pairs:   506  out of   1398    36%
611 
   Number of unique control sets:        48
612 
 
613 
IO Utilization:
614 
 Number of IOs:                          80
615 
 Number of bonded IOBs:                  79  out of    220    35%
616 
    IOB Flip Flops/Latches:              10
617 
 
618 
Specific Feature Utilization:
619 
 Number of Block RAM/FIFO:                3  out of     32     9%
620 
    Number using Block RAM only:          3
621 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
622 
 Number of DSP48Es:                       1  out of     32     3%
623 
 
624 
---------------------------
625 
 
626 
====================================================================================
627 
#                            SYNTHESIS DONE
628 
#####################################################################################
629 
 
630 
#####################################################################################
631 
#                            START SYNTHESIS (AREA optimized)
632 
#====================================================================================
633 
# virtex5 (xc5vlx30ff324), speedgrade: -2
634 
#====================================================================================
635 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
636 
#     12          10          0         0            0          0            0         1
637 
#====================================================================================
638 
Clock to Setup on destination clock dco_clk
639 
---------------+---------+---------+---------+---------+
640 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
641 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
642 
---------------+---------+---------+---------+---------+
643 
dco_clk        |   14.207|         |         |    0.680|
644 
---------------+---------+---------+---------+---------+
645 
 
646 
====================================================================================
647 
Device utilization summary:
648 
---------------------------
649 
 
650 
Selected Device : 5vlx30ff324-2
651 
 
652 
 
653 
Slice Logic Utilization:
654 
 Number of Slice Registers:             532  out of  19200     2%
655 
 Number of Slice LUTs:                 1372  out of  19200     7%
656 
    Number used as Logic:              1372  out of  19200     7%
657 
 
658 
Slice Logic Distribution:
659 
 Number of LUT Flip Flop pairs used:   1399
660 
   Number with an unused Flip Flop:     867  out of   1399    61%
661 
   Number with an unused LUT:            27  out of   1399     1%
662 
   Number of fully used LUT-FF pairs:   505  out of   1399    36%
663 
   Number of unique control sets:        48
664 
 
665 
IO Utilization:
666 
 Number of IOs:                          80
667 
 Number of bonded IOBs:                  79  out of    220    35%
668 
    IOB Flip Flops/Latches:              10
669 
 
670 
Specific Feature Utilization:
671 
 Number of Block RAM/FIFO:                3  out of     32     9%
672 
    Number using Block RAM only:          3
673 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
674 
 Number of DSP48Es:                       1  out of     32     3%
675 
 
676 
---------------------------
677 
 
678 
====================================================================================
679 
#                            SYNTHESIS DONE
680 
#####################################################################################
681 
 
682 
#####################################################################################
683 
#                            START SYNTHESIS (AREA optimized)
684 
#====================================================================================
685 
# virtex5 (xc5vlx30ff324), speedgrade: -3
686 
#====================================================================================
687 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
688 
#     12          10          0         0            0          0            0         1
689 
#====================================================================================
690 
Clock to Setup on destination clock dco_clk
691 
---------------+---------+---------+---------+---------+
692 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
693 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
694 
---------------+---------+---------+---------+---------+
695 
dco_clk        |   13.429|         |         |    0.601|
696 
---------------+---------+---------+---------+---------+
697 
 
698 
====================================================================================
699 
Device utilization summary:
700 
---------------------------
701 
 
702 
Selected Device : 5vlx30ff324-3
703 
 
704 
 
705 
Slice Logic Utilization:
706 
 Number of Slice Registers:             532  out of  19200     2%
707 
 Number of Slice LUTs:                 1367  out of  19200     7%
708 
    Number used as Logic:              1367  out of  19200     7%
709 
 
710 
Slice Logic Distribution:
711 
 Number of LUT Flip Flop pairs used:   1395
712 
   Number with an unused Flip Flop:     863  out of   1395    61%
713 
   Number with an unused LUT:            28  out of   1395     2%
714 
   Number of fully used LUT-FF pairs:   504  out of   1395    36%
715 
   Number of unique control sets:        48
716 
 
717 
IO Utilization:
718 
 Number of IOs:                          80
719 
 Number of bonded IOBs:                  79  out of    220    35%
720 
    IOB Flip Flops/Latches:              10
721 
 
722 
Specific Feature Utilization:
723 
 Number of Block RAM/FIFO:                3  out of     32     9%
724 
    Number using Block RAM only:          3
725 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
726 
 Number of DSP48Es:                       1  out of     32     3%
727 
 
728 
---------------------------
729 
 
730 
====================================================================================
731 
#                            SYNTHESIS DONE
732 
#####################################################################################
733 
 
734 
#####################################################################################
735 
#                            START SYNTHESIS (AREA optimized)
736 
#====================================================================================
737 
# virtex6 (xc6vlx75tff484), speedgrade: -1
738 
#====================================================================================
739 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
740 
#     12          10          0         0            0          0            0         1
741 
#====================================================================================
742 
Clock to Setup on destination clock dco_clk
743 
---------------+---------+---------+---------+---------+
744 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
745 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
746 
---------------+---------+---------+---------+---------+
747 
dco_clk        |   14.414|    3.474|    1.579|    0.604|
748 
---------------+---------+---------+---------+---------+
749 
 
750 
====================================================================================
751 
Device utilization summary:
752 
---------------------------
753 
 
754 
Selected Device : 6vlx75tff484-1
755 
 
756 
 
757 
Slice Logic Utilization:
758 
 Number of Slice Registers:             532  out of  93120     0%
759 
 Number of Slice LUTs:                 1390  out of  46560     2%
760 
    Number used as Logic:              1390  out of  46560     2%
761 
 
762 
Slice Logic Distribution:
763 
 Number of LUT Flip Flop pairs used:   1419
764 
   Number with an unused Flip Flop:     887  out of   1419    62%
765 
   Number with an unused LUT:            29  out of   1419     2%
766 
   Number of fully used LUT-FF pairs:   503  out of   1419    35%
767 
   Number of unique control sets:        49
768 
 
769 
IO Utilization:
770 
 Number of IOs:                          80
771 
 Number of bonded IOBs:                  79  out of    240    32%
772 
    IOB Flip Flops/Latches:              10
773 
 
774 
Specific Feature Utilization:
775 
 Number of Block RAM/FIFO:                3  out of    156     1%
776 
    Number using Block RAM only:          3
777 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
778 
 Number of DSP48E1s:                      1  out of    288     0%
779 
 
780 
---------------------------
781 
 
782 
====================================================================================
783 
#                            SYNTHESIS DONE
784 
#####################################################################################
785 
 
786 
#####################################################################################
787 
#                            START SYNTHESIS (AREA optimized)
788 
#====================================================================================
789 
# virtex6 (xc6vlx75tff484), speedgrade: -2
790 
#====================================================================================
791 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
792 
#     12          10          0         0            0          0            0         1
793 
#====================================================================================
794 
Clock to Setup on destination clock dco_clk
795 
---------------+---------+---------+---------+---------+
796 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
797 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
798 
---------------+---------+---------+---------+---------+
799 
dco_clk        |   12.694|    3.071|    1.435|    0.508|
800 
---------------+---------+---------+---------+---------+
801 
 
802 
====================================================================================
803 
Device utilization summary:
804 
---------------------------
805 
 
806 
Selected Device : 6vlx75tff484-2
807 
 
808 
 
809 
Slice Logic Utilization:
810 
 Number of Slice Registers:             532  out of  93120     0%
811 
 Number of Slice LUTs:                 1388  out of  46560     2%
812 
    Number used as Logic:              1388  out of  46560     2%
813 
 
814 
Slice Logic Distribution:
815 
 Number of LUT Flip Flop pairs used:   1418
816 
   Number with an unused Flip Flop:     886  out of   1418    62%
817 
   Number with an unused LUT:            30  out of   1418     2%
818 
   Number of fully used LUT-FF pairs:   502  out of   1418    35%
819 
   Number of unique control sets:        49
820 
 
821 
IO Utilization:
822 
 Number of IOs:                          80
823 
 Number of bonded IOBs:                  79  out of    240    32%
824 
    IOB Flip Flops/Latches:              10
825 
 
826 
Specific Feature Utilization:
827 
 Number of Block RAM/FIFO:                3  out of    156     1%
828 
    Number using Block RAM only:          3
829 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
830 
 Number of DSP48E1s:                      1  out of    288     0%
831 
 
832 
---------------------------
833 
 
834 
====================================================================================
835 
#                            SYNTHESIS DONE
836 
#####################################################################################
837 
 
838 
#####################################################################################
839 
#                            START SYNTHESIS (AREA optimized)
840 
#====================================================================================
841 
# virtex6 (xc6vlx75tff484), speedgrade: -3
842 
#====================================================================================
843 
# PMEM_AWIDTH DMEM_AWIDTH  DBG_EN  DBG_HWBRK_0 DBG_HWBRK_1 DBG_HWBRK_2 DBG_HWBRK_3 MULTIPLIER
844 
#     12          10          0         0            0          0            0         1
845 
#====================================================================================
846 
Clock to Setup on destination clock dco_clk
847 
---------------+---------+---------+---------+---------+
848 
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
849 
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
850 
---------------+---------+---------+---------+---------+
851 
dco_clk        |   10.953|    3.120|    1.173|    0.463|
852 
---------------+---------+---------+---------+---------+
853 
 
854 
====================================================================================
855 
Device utilization summary:
856 
---------------------------
857 
 
858 
Selected Device : 6vlx75tff484-3
859 
 
860 
 
861 
Slice Logic Utilization:
862 
 Number of Slice Registers:             532  out of  93120     0%
863 
 Number of Slice LUTs:                 1387  out of  46560     2%
864 
    Number used as Logic:              1387  out of  46560     2%
865 
 
866 
Slice Logic Distribution:
867 
 Number of LUT Flip Flop pairs used:   1416
868 
   Number with an unused Flip Flop:     884  out of   1416    62%
869 
   Number with an unused LUT:            29  out of   1416     2%
870 
   Number of fully used LUT-FF pairs:   503  out of   1416    35%
871 
   Number of unique control sets:        49
872 
 
873 
IO Utilization:
874 
 Number of IOs:                          80
875 
 Number of bonded IOBs:                  79  out of    240    32%
876 
    IOB Flip Flops/Latches:              10
877 
 
878 
Specific Feature Utilization:
879 
 Number of Block RAM/FIFO:                3  out of    156     1%
880 
    Number using Block RAM only:          3
881 
 Number of BUFG/BUFGCTRLs:                1  out of     32     3%
882 
 Number of DSP48E1s:                      1  out of    288     0%
883 
 
884 
---------------------------
885 
 
886 
====================================================================================
887 
#                            SYNTHESIS DONE
888 
#####################################################################################
889 
 

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